ETC CXG1115AER

CXG1115AER
Dual-band Low Noise Amplifier/Mixer
Description
The CXG1115AER is a dual-band (CDMA/GPS) low
noise amplifier/mixer MMIC for the Japan CDMA
cellular phones (J-CDMA). This IC is designed using
the Sony’s GaAs J-FET process.
24 pin VQFN (Plastic)
Features
• High gain:
CDMA LNA High current mode
Gp = 14.5dB (Typ.)
CDMA MIX
Gc = 12dB (Typ.)
GPS
LNA
Gp = 18dB (Typ.)
GPS
MIX
Gc = 9.5dB (Typ.)
• Low noise figure:
CDMA LNA High current mode
NF = 1.5dB (Typ.)
CDMA MIX
NF = 4.5dB (Typ.)
GPS
LNA
NF = 1.7dB (Typ.)
GPS
MIX
NF = 5dB (Typ.)
• Low distortion
CDMA LNA High current mode
Input IP3 = +3.5dBm (Typ.)
CDMA MIX
Input IP3 = +2dBm (Typ.)
GPS
LNA
Input IP3 = –5.5dBm (Typ.)
GPS
MIX
Input IP3 = +2dBm (Typ.)
• Low noise amplifier with by-pass switch
• J-CDMA/GPS supported dual band
• Sharing the two-system LO signal source by the
doubler system
• 24-pin VQFN small package
Structure
GaAs J-FET MMIC
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
4.5
V
• Input power
PIN
+5
dBm
• Operating temperature Topr
–35 to +85 °C
• Storage temperature
Tstg
–65 to +150 °C
CDMA LNAIN
GND
LNA OPT
GPS LNAIN
CAP
Recommended Operating Conditions
• Supply voltage
VDD
2.7 to 3.3
• Control voltage
VCTL (H) 2.4 to 3.3
VCTL (L) 0 to 0.3
CAP
Block Diagram and Pin Configuration
Applications
J-CDMA
12
11
10
9
8
7
CDMA LNAOUT/VDD (LNA) 13
V
V
V
6 GPS LNAOUT/VDD (LNA)
5 CTL1
CTL2 14
NC 15
4 MPX OPT
3 GND
GND 16
2 GPS MIX RFIN
CDMA MIX RFIN 17
CTL3 18
1 GPS IFOUT/VDD (MIX)
19
20
21
22
23
24
LOIN
VDD (GPS LO)
GND
VDD (Logic)
VDD (CDMA LO)
CDMA IFOUT/VDD (MIX)
×2
GaAs MMICs are ESD sensitive devices. Special handling precautions are required.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E02609A34
CXG1115AER
Electrical Characteristics
Conditions: VDD = 2.7V, VCTL (H) = 2.7V, VCTL (L) = 0V, (Ta = 25°C)
Logic Block
Symbol
Item
Min.
Typ.
Max.
Unit
Control pin current
ICTL (H)
—
35
50
µA
Logic power current consumption
IDD
—
0.3
0.6
mA
Condition
When no signal
CDMA-LNA Block Conditions: fRF = 850MHz
Control pin condition
Item
Current consumption
Power gain
Noise figure
Input IP3
Isolation
Min.
Typ.
Max.
IDDSW
—
0.1
0.3
H
IDDM
—
5
7
H
L
IDDL
—
3.2
5
L
H
H
IDDH
—
5.3
7.5
L
L
L
GPSW
–4.3
–3.8
–3.3
L
L
H
GPM
6
7
8
L
H
L
GPL
12
13.5
15
L
H
H
GPH
13
14.5
16
H
—
—
GPOFF
—
–13
–8
L
L
H
NFM
—
8
10
L
H
L
NFL
—
1.5
2
L
H
H
NFH
—
1.5
2
L
L
L
IIP3SW
20
28
—
L
L
H
IIP3M
6
8.5
—
L
H
L
IIP3L
–1.5
1
—
L
H
H
IIP3H
1.5
3.5
—
L
L
H
ISOM
21
26
—
L
H
L
ISOL
13
18
—
L
H
H
ISOH
13
18
—
VCTL1
VCTL2
VCTL3
L
L
L
L
L
L
Symbol
Unit
mA
When no
signal
dB
When a
small signal
dB
dBm
dB
∗1 Conversion from the IM3 suppression ratio for two-wave input: fRF = 850MHz/850.9MHz,
PRF = 0dBm (GPSW mode), PRF = –20dBm (GPM mode), PRF = –25dBm (GPL/GPH mode).
–2–
Condition
∗1
When a
small signal
CXG1115AER
CDMA-MIX Block Conditions: fRF = 850MHz, fLO = fRF – fIF, fIF = 110MHz, PLO = –10dBm
Control pin condition
Symbol
Min.
Typ.
Max.
Unit
Condition
IDD
—
8
11
mA
When no signal
—
GC
10.5
12
13.5
—
—
GCOFF
—
–55
–45
dB
When a small
signal
L
—
—
NF
—
4.5
6
Input IP3
L
—
—
IIP3
0
2
—
LO – RF leak
L
—
—
PLK
—
–23
–18
Item
VCTL1
VCTL2
VCTL3
L
—
—
L
—
H
Noise figure
Current consumption
Conversion gain
dB
dBm ∗2
dBm
—
∗2 Conversion from the IM3 suppression ratio for two-wave input: fRF = 850MHz/850.9MHz, PRF = –25dBm.
GPS-LNA Block Conditions: fRF = 1575MHz
Control pin condition
Min.
Typ.
Max.
Unit
Condition
IDD
—
5.5
7.5
mA
When no signal
—
GP
16.5
18
19.5
—
—
GPOFF
—
–22
–17
dB
When a small
signal
H
—
—
NF
—
1.7
2.2
Input IP3
H
—
—
IIP3
–8
–5.5
—
Isolation
H
—
—
ISO
23
28
—
Item
VCTL1
VCTL2
VCTL3
H
—
—
H
—
L
Noise figure
Current consumption
Power gain
Symbol
dB
dBm ∗3
dB
When a small
signal
∗3 Conversion from the IM3 suppression ratio for two-wave input: fRF = 1574.5MHz/1575.5MHz, PRF = –30dBm.
GPS-MIX Block Conditions: fRF = 1575MHz, fLO = (fRF – fIF)/2, fIF = 110MHz, PLO = –10dBm
Control pin condition
Min.
Typ.
Max.
Unit
Condition
IDD
—
8
11
mA
When no signal
—
GC
8
9.5
11
—
—
GCOFF
—
–50
–40
dB
When a small
signal
H
—
—
NF
—
5
6.5
Input IP3
H
—
—
IIP3
–1.5
2
—
LO – RF leak
H
—
—
PLK
—
–15
–10
Item
VCTL1
VCTL2
VCTL3
H
—
—
H
—
L
Noise figure
Current consumption
Conversion gain
Symbol
dB
dBm ∗4
dBm
@fLO =
fRF – fIF
∗4 Conversion from the IM3 suppression ratio for two-wave input: fRF = 1574.5MHz/1575.5MHz, PRF = –25dBm.
–3–
CXG1115AER
Recommended Evaluation Circuit
GPS LNAIN
CDMA LNAIN
L16
L17
R
C8
CDMA LNAOUT
C5
C7
L11
L
L14
L13
L15
L12
12
11
10
9
8
7
CTL2
C10
L19
VDD (LNA)
C6
GPS LNAOUT
L18
C9
13
6
14
5
C11
CTL1
R1
CDMA MIXIN
L9
15
4
16
3
17
2
L8
L20
L10
18
CTL3
20
21
L21
1
×2
19
GPS MIXIN
L22
22
23
GPS IFOUT
24
C12
L6
LOIN
L3
L5
L7
L23
L2
L1
L4
VDD (MIX)
C14
CDMA IFOUT
C2
C1
C4
C13
C3
VDD
(LO AMP)
VDD (Logic)
∗ The IC mounted pattern on the back side is electrically in the open state.
L1
220nH
L16
3.3nH
C8
100pF
L2
220nH
L17
8.2nH
C9
18pF
L3
27nH
L18
6.8nH
C10
100pF
L4
5.6nH
L19
3.9nH
C11
1000pF
L5
6.8nH
L20
10nH
C12
8pF
L6
33nH
L21
2.7nH
C13
1000pF
L7
12nH
L22
220nH
C14
1000pF
L8
27nH
L23
220nH
100Ω
L9
18nH
C1
8pF
R1
L∗1
L10
22nH
C2
1000pF
R∗1
L11
22nH
C3
1000pF
L12
27nH
C4
100pF
L13
2.2nH
C5
100pF
L14
22nH
C6
1000pF
L15
5.6nH
C7
1000pF
33nH
—
∗1 L and R of Pin 9 are used when the optional resistor is added in the low noise amplifier block.
–4–
CXG1115AER
Example of Representative Characteristics (Ta = 25°C)
Low Noise Amplifier Block
CDMA GPL, NFL vs. fRF
16
8
13
15
12
14
GPM – Power gain [dB]
11
6
5
4
VDD = 2.7V
VCTL1 = 0V
VCTL2 = 0V
VCTL3 = 2.7V
10
9
8
3
NFM
2
1
0
800
820
840
860
880
GPL – Power gain [dB]
GPM
7
NFM – Noise figure [dB]
14
GPL
12
11
10
VDD = 2.7V
VCTL1 = 0V
VCTL2 = 2.7V
VCTL3 = 0V
8
2
6
7
6
800
NFL
1
820
860
840
880
0
900
fRF – RF frequency [MHz]
GPS GP, NF vs. fRF
CDMA GPH, NFH vs. fRF
20
5
GPH
15
3
9
fRF – RF frequency [MHz]
16
4
13
7
5
900
5
NFL – Noise figure [dB]
CDMA GPM, NFM vs. fRF
9
5
19
GP
11
3
2
10
NFH
9
GP – Power gain [dB]
12
VDD = 2.7V
VCTL1 = 0V
VCTL2 = 2.7V
VCTL3 = 2.7V
NF – Noise figure [dB]
GPH – Power gain [dB]
13
1
8
17
16
15
VDD = 2.7V
VCTL1 = 2.7V
VCTL2 = 0V
VCTL3 = 0V
3
2
14
13
NF
1
12
7
6
800
4
18
11
820
840
860
880
10
1525
0
900
fRF – RF frequency [MHz]
1545
1565
1585
1605
fRF – RF frequency [MHz]
–5–
0
1625
NF – Noise figure [dB]
4
14
CXG1115AER
Low Noise Amplifier Block
CDMA POUT, IM3M vs. PIN
CDMA POUT IM3L vs. PIN
20
20
10
10
0
POUT
–10
POUT – RF output power [dBm]
POUT – RF output power [dBm]
0
–20
–30
–40
IM3M
VDD = 2.7V
VCTL1 = 0V
VCTL2 = 0V
VCTL3 = 2.7V
fRF1 = 850MHz
fRF2 = 850.9MHz
–50
–60
–70
–80
–40
–30
–20
–10
0
10
POUT
–10
–20
–30
–40
–60
–70
–80
–40
CDMA POUT, IM3H vs. PIN
10
10
–10
0
10
0
POUT
POUT – RF output power [dBm]
POUT – RF output power [dBm]
–20
GPS POUT IM3 vs. PIN
20
–10
–20
–30
IM3H
–40
VDD = 2.7V
VCTL1 = 0V
VCTL2 = 2.7V
VCTL3 = 2.7V
fRF1 = 850MHz
fRF2 = 850.9MHz
–50
–60
–70
–30
–30
PIN – RF input power [dBm]
20
–80
–40
VDD = 2.7V
VCTL1 = 0V
VCTL2 = 2.7V
VCTL3 = 0V
fRF1 = 850MHz
fRF2 = 850.9MHz
–50
PIN – RF input power [dBm]
0
IM3L
–20
–10
0
10
–10
POUT
–20
–30
IM3
–40
VDD = 2.7V
VCTL1 = 2.7V
VCTL2 = 0V
VCTL3 = 0V
fRF1 = 1574.5MHz
fRF2 = 1575.5MHz
–50
–60
–70
–80
–40
PIN – RF input power [dBm]
–30
–20
–10
0
PIN – RF input power [dBm]
–6–
10
CXG1115AER
Mixer Block
GPS Gc, NF vs. fRF
14
12
10
11
9
13
GC
10
12
11
9
VDD = 2.7V
VCTL1 = 0V
VCTL2 = 0V
VCTL3 = 0V
fLO = fRF – 110MHz
PLO = –10dBm
10
9
8
8
7
6
NF
7
6
5
800
840
820
860
880
13
GC
11
8
7
6
5
4
8
7
6
NF
3
5
4
2
4
3
900
1
1525
1545
1565
1585
1605
3
1625
fRF – RF frequency [MHz]
CDMA POUT, IM3 vs. PIN
GPS POUT, IM3 vs. PIN
20
10
10
0
POUT – RF output power [dBm]
0
POUT – RF output power [dBm]
9
5
20
POUT
–20
–30
–40
IM3
VDD = 2.7V
VCTL1 = 0V
VCTL2 = 0V
VCTL3 = 0V
fRF1 = 850MHz
fRF2 = 850.9MHz
fLO = 740MHz
–50
–60
–70
–80
–40
10
VDD = 2.7V
VCTL1 = 2.7V
VCTL2 = 0V
VCTL3 = 0V
fLO = fRF – 110MHz
PLO = –10dBm
fRF – RF frequency [MHz]
–10
12
NF – Noise figure [dB]
11
Gc – Conversion gain [dB]
13
NF – Noise figure [dB]
Gc – Conversion gain [dB]
CDMA Gc, NF vs. fRF
15
–30
–20
–10
0
10
–10
POUT
–20
–30
–40
IM3
VDD = 2.7V
VCTL1 = 2.7V
VCTL2 = 0V
VCTL3 = 0V
fRF1 = 1574.5MHz
fRF2 = 1575.5MHz
fLO = 732.5MHz
–50
–60
–70
–80
–40
PIN – RF input power [dBm]
–30
–20
–10
0
PIN – RF input power [dBm]
–7–
10
CXG1115AER
Mixer Block
CDMA Gc, NF vs. PLO
GPS Gc, NF vs. PLO
12
14
6
4
5.0
Gc – Conversion gain [dB]
VDD = 2.7V
VCTL1 = 0V
VCTL2 = 0V
VCTL3 = 0V
fRF = 850MHz
fLO = 740MHz
NF – Noise figure [dB]
Gc – Conversion gain [dB]
5.5
12
8
4.5
NF
8
–12.5
–10.0
–7.5
–5.0
–2.5
0
4.0
4
5.5
5.0
NF
0
–15.0
4.5
–12.5
–10.0
–7.5
–5.0
–2.5
0
PLO – LO input power [dBm]
CDMA IIP3 vs. PLO
GPS IIP3 vs. PLO
4.0
3.0
3.5
2.5
3.0
IIP3 – Input IP3 [dBm]
IIP3 – Input IP3 [dBm]
6.0
VDD = 2.7V
VCTL1 = 2.7V
VCTL2 = 0V
VCTL3 = 0V
fRF = 1575MHz
fLO = 732.5MHz
6
PLO – LO input power [dBm]
2.5
2.0
VDD = 2.7V
VCTL1 = 0V
VCTL2 = 0V
VCTL3 = 0V
fRF = 850MHz
fLO = 740MHz
1.5
1.0
0.5
0
–15.0
6.5
2
2
0
–15.0
GC
10
GC
10
7.0
–12.5
–10.0
–7.5
–5.0
–2.5
2.0
1.5
VDD = 2.7V
VCTL1 = 2.7V
VCTL2 = 0V
VCTL3 = 0V
fRF = 1575MHz
fLO = 732.5MHz
1.0
0.5
0
–15.0
0
PLO – LO input power [dBm]
–12.5
–10.0
–7.5
–5.0
–2.5
PLO – LO input power [dBm]
–8–
0
4.0
NF – Noise figure [dB]
6.0
16
CXG1115AER
Characteristics Example When the Optional Resistor R is Added (Ta = 25°C)
Low Noise Amplifier Block
∗ Measured with the choke inductor (L = 33nH) for decoupling inserted to Pin 9 (LNA OPT pin) in series.
CDMA IDDL vs. R
10
9
9
IDDL – Current consumption [mA]
IDDM – Current consumption [mA]
CDMA IDDM vs. R
10
8
7
6
5
VDD = 2.7V
VCTL1 = 0V
VCTL2 = 0V
VCTL3 = 2.7V
4
3
2
OPEN
120
47
15
27
8
VDD = 2.7V
VCTL1 = 0V
VCTL2 = 2.7V
VCTL3 = 0V
7
6
5
4
3
2
OPEN
10
120
R – Optional resistor [Ω]
47
15
27
10
R – Optional resistor [Ω]
CDMA GPM, NFM vs. R
CDMA GPL, NFL vs. R
8
10
15
3.0
GPM
8
NFM
5
OPEN
47
27
15
VDD = 2.7V
VCTL1 = 0V
VCTL2 = 2.7V
VCTL3 = 0V
fRF = 850MHz
PRF = –25dBm
13
11
OPEN
10
2.0
NFL
12
7
120
2.5
14
1.5
NFL – Noise figure [dB]
6
9
GPL – Power gain [dB]
VDD = 2.7V
VCTL1 = 0V
VCTL2 = 0V
VCTL3 = 2.7V
fRF = 850MHz
PRF = –20dBm
7
NFM – Noise figure [dB]
GPM – Power gain [dB]
GPL
1.0
120
R – Optional resistor [Ω]
47
15
27
10
R – Optional resistor [Ω]
CDMA IIP3M, ISOM vs. R
CDMA IIP3L, ISOL vs. R
10
30
20
5
IIP3M
28
27
7
47
IIP3L
VDD = 2.7V
VCTL1 = 0V
VCTL2 = 2.7V
VCTL3 = 0V
fRF1 = 850MHz
fRF2 = 850.9MHz
PRF = –25dBm
2
0
OPEN
26
120
18
3
1
ISOM
6
OPEN
19
ISOL
27
R – Optional resistor [Ω]
15
10
–9–
120
47
27
R – Optional resistor [Ω]
15
10
17
16
15
ISOL – Isolation [dB]
8
IIP3L – Input IP3 [dBm]
VDD = 2.7V
VCTL1 = 0V
VCTL2 = 0V
VCTL3 = 2.7V
fRF1 = 850MHz
fRF2 = 850.9MHz
PRF = –20dBm
ISOM – Isolation [dB]
IIP3M – Input IP3 [dBm]
4
29
9
CXG1115AER
Low Noise Amplifier Block
∗ Measured with the choke inductor (L = 33nH) for decoupling inserted to Pin 9 (LNA OPT pin) in series.
GPS IDD vs. R
10
9
9
IDD – Current consumption [mA]
IDDH – Current consumption [mA]
CDMA IDDH vs. R
10
8
7
6
5
4
VDD = 2.7V
VCTL1 = 0V
VCTL2 = 2.7V
VCTL3 = 2.7V
3
2
OPEN
120
47
27
15
8
7
6
5
4
VDD = 2.7V
VCTL1 = 2.7V
VCTL2 = 0V
VCTL3 = 0V
3
2
OPEN
10
120
R – Optional resistor [Ω]
47
27
15
10
R – Optional resistor [Ω]
CDMA GPH, NFH vs. R
GPS GP, NF vs. R
16
3.0
20
2.5
19
3.0
13
12
OPEN
2.0
1.5
NFH
120
47
27
15
10
18
NF
1.5
16
OPEN
1.0
120
CDMA IIP3H, ISOH vs. R
18
5
IIP3H
17
VDD = 2.7V
VCTL1 = 0V
VCTL2 = 2.7V
VCTL3 = 2.7V
fRF1 = 850MHz
fRF2 = 850.9MHz
PRF = –25dBm
27
R – Optional resistor [Ω]
15
10
16
IIP3 – Input IP3 [dBm]
19
ISOH – Isolation [dB]
IIP3H – Input IP3 [dBm]
ISOH
47
27
15
10
1.0
GPS IIP3, ISO vs. R
20
120
47
R – Optional resistor [Ω]
6
3
OPEN
2.0
17
R – Optional resistor [Ω]
4
2.5
VDD = 2.7V
VCTL1 = 2.7V
VCTL2 = 0V
VCTL3 = 0V
fRF = 1575MHz
PRF = –30dBm
–1
31
–2
30
ISO
–3
–4
IIP3
VDD = 2.7V
VCTL1 = 2.7V
VCTL2 = 0V
VCTL3 = 0V
fRF1 = 1574.5MHz
fRF2 = 1575.5MHz
PRF = –30dBm
–5
15
–6
OPEN
14
– 10 –
29
28
27
120
47
27
R – Optional resistor [Ω]
15
10
26
ISO – Isolation [dB]
14
GP
NF – Noise figure [dB]
VDD = 2.7V
VCTL1 = 0V
VCTL2 = 2.7V
VCTL3 = 2.7V
fRF = 850MHz
PRF = –25dBm
GP – Power gain [dB]
15
NFH – Noise figure [dB]
GPH – Power gain [dB]
GPH
CXG1115AER
Characteristics Example When the Optional Resistor R is Added (Ta = 25°C)
Mixer Block
GPS IDD (MIX) vs. R1
IDD (MIX) – Mixer block current consumption [mA]
9
8
7
VDD = 2.7V
VCTL1 = 0V
VCTL2 = 0V
VCTL3 = 0V
6
5
OPEN
100
47
27
10
8
7
6
5
3
OPEN
R1 – Optional resistor [Ω]
11.0
6.0
5.5
5.0
NF
10.5
10.0
OPEN
Gc – Conversion gain [dB]
11.5
4.5
100
47
27
8.0
7.0
8.5
8.0
7.5
NF
7.0
6.0
OPEN
4.0
10
4
IIP3 – Input IP3 [dBm]
IIP3 – Input IP3 [dBm]
5.5
5.0
100
47
27
10
GPS IIP3 vs. R1
4
3
VDD = 2.7V
VCTL1 = 0V
VCTL2 = 0V
VCTL3 = 0V
fRF = 850MHz
fLO = 740MHz
PLO = –25dBm
47
6.0
R1 – Optional resistor [Ω]
5
100
6.5
4.5
CDMA IIP3 vs. R1
0
OPEN
VDD = 2.7V
VCTL1 = 2.7V
VCTL2 = 0V
VCTL3 = 0V
fRF = 1575MHz
fLO = 732.5MHz
PLO = –25dBm
6.5
5
1
7.5
9.0
R1 – Optional resistor [Ω]
2
10
GC
9.5
NF – Noise figure [dB]
Gc – Conversion gain [dB]
VDD = 2.7V
VCTL1 = 0V
VCTL2 = 0V
VCTL3 = 0V
fRF = 850MHz
fLO = 740MHz
PLO = –25dBm
12.0
27
GPS Gc, NF vs. R1
6.5
GC
47
10.0
7.0
12.5
100
R1 – Optional resistor [Ω]
CDMA Gc, NF vs. R1
13.0
VDD = 2.7V
VCTL1 = 2.7V
VCTL2 = 0V
VCTL3 = 0V
4
27
R1 – Optional resistor [Ω]
3
VDD = 2.7V
VCTL1 = 2.7V
VCTL2 = 0V
VCTL3 = 0V
fRF = 1575MHz
fLO = 732.5MHz
PLO = –25dBm
2
1
0
OPEN
10
– 11 –
100
47
27
R1 – Optional resistor [Ω]
10
4.0
NF – Noise figure [dB]
IDD (MIX) – Mixer block current consumption [mA]
CDMA IDD (MIX) vs. R1
10
CXG1115AER
Recommended Evaluation Board
Front
50mm
VDD (LO AMP)
VCTL2 GND
VCTL3
VDD (LNA) VDD (Logic)
VDD (MIX)
VCTL1
GND
50mm
CDMA LNA RFIN
GPS LNA RFIN
CDMA LNA RFOUT
GPS LNA RFOUT
CDMA MIX RFIN
GPS MIX RFIN
LOIN
CDMA MIX IFOUT
GPS MIX IFOUT
Glass fabric-base 4-layer epoxy board (thickness: 0.2mm × 2)
GND for the whole 2nd and 3rd layers
Enlarged Diagram of Center Part
L16
C8
C7
L15
L17
L14
L13
C9
C6
L12
C10
L18 L19
L11
C11
C5
R1
L9
L20
L10
L21
C12
L8
L22
C1
L6 L5
L1
L3
L7
L4
L23
L2
C4
C3
C13
C2
C14
The IC mounted pattern on the back side is electrically in the open state.
– 12 –
CXG1115AER
Package Outline
Unit: mm
24PIN VQFN(PLASTIC)
0.9 ± 0.1
4.0
0.6 ± 0.1
2.0
A
19
S
4R
C
13
18
0.05
0.7
0.
3
3.6
12
B
9)
.3
(0
PIN 1 INDEX
24
˚
45
6
S
x4
.1
5)
1.0
0.1 S A-B C
(0
0.4
C
1
0.
6
7
x4
0.2 ± 0.01
0.03 ± 0.03(∗1)
(Stand Off)
0.05 M S A-B C
0.225 ± 0.03
0.1 S A-B C
Solder Plating
NOTE: 1) The dimensions of the terminal section apply to the
ranges of 0.1mm and 0.25mm from the end of a terminal.
2) The dimension of (∗1) is apply to DiePad and the lead.
0.13 ± 0.025
+ 0.09
0.14 – 0.03
TERMINAL SECTION
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
PACKAGE MASS
0.04g
VQFN-24P-04
SONY CODE
LEAD SPECIFICATIONS
ITEM
SPEC.
LEAD MATERIAL
COPPER ALLOY
SOLDER PLATING
Sn-Bi Bi:1-4wt%
LEAD TREATMENT THICKNESS
5-18µm
– 13 –
Sony Corporation