10BIT 75MSPS Quad-DAC GENERAL DESCRIPTION DAC1350X FEATURES This core is a CMOS quad-channel 10bit 75MSPS D/A converter for general & video applications. The dac1350x core is implemented in the Samsung 0.18um 3.3V CMOS process. Digital inputs are coded as straight binary. Each dac channel includes dependent power down control and the ability to sense output load. An external(optional) or internal 0.7V reference voltage (VREFOUT) and a single external resister define the full-scale output current together. It uses the two architecture of current-segment and binary-weighted. • • • • • • • • • • Maximum conversion rate is 75MSPS +3.3V CMOS monolithic construction ±1 LSB differential linearity (max) ±2 LSB integral linearity (max) External or internal voltage reference (Including Band Gap Reference Block) 10-Bit parallel digital input DAC auto-load detection circuitry Temperature : 0 ~ 70°C Each channel Power_Down Power Dump Mode TYPICAL APPLICATION •High Definition Television(HDTV) • High Resolution Color Graphics • Image Processing FUNCTIONAL BLOCK DIAGRAM IOUT0 IOUT1 IOUT2 IOUT3 binary LSBs DATA0[9:0] PDDAC[0] DACLP[0] binary LSBs digital decode DATA3[9:0] digital decode segmented MSBs segmented MSBs PDDAC[3] DACLP[3] AVDD33A DATA1[9:0] PDDAC[1] DACLP[1] binary LSBs binary LSBs segmented MSBs segmented MSBs digital decode AVSS33A DATA2[9:0] digital decode PDDAC[2] AVDD33D DACLP[2] AVSS33D AVDD18D CLK DTOUT DACPRE DLDSEL[1:0] BGPD Auto-load Detect CCOMP VREFOUT Band gap reference generator VBIAS IRSET Ver 1.5 (Apr. 2002) No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this data sheet is subject to change without any notice. SAMSUNG ELECTRONICS Co. LTD 1 / 15 DAC1350X 10BIT 75MSPS Quad DAC PIN CONFIGURATION NAME I/ O I/O PAD PIN DESCRIPTION INPUTS PDDAC[3:0] DI picc_abb Individual DAC power down control. When activated(high), the corresponding DAC is disabled. DACLP[3:0] DI picc_abb Low power current dumping mode control for each DAC. When selected (high enables low power mode) the corresponding DAC will run at reduced power with a slight loss in performance. CLK DI picc_abb DAC master clock. Input data is sampled with the rising edge of CLK. DI picc_abb Control strobe for the DAC auto-load detection comparator. When DACPRE transitions high-to-low, the auto-load detect circuit evaluates its selected input. Appropriate settling time must be allowed before the comparator output (DTOUT) is used. When not used, DACPRE should be left high. DI picc_abb 10-bit straight binary digital input for each DAC channel. BGPD DI picc_abb Power down control for Bandgap and all quad DACs. A high level disables all quad DACs plus the bandgap reference regardless of the states of PDDAC0,PDDAC1,PDDAC2,PDDAC3 DLDSEL[1:0] DI picc_abb Selection control for external DAC auto-load detection. Enable of load for IOUT0 is selected LDSEL[1:0]="00", IOUT2 is DLDSEL[1:0]="01", IOUT1 is DLDSEL[1:0]="10", IOUT3 is DLDSEL[1:0]="11" DACPRE DATA0[9:0] DATA1[9:0] DATA2[9:0] DATA3[9:0] OUTPUT DTOUT DO pot8_abb Comparator output for detection of resistive load at DAC output. A low at the detect output indicates that the output voltage of the selected channel is above 0.53V and therefore that no load is attached. IOUT0 IOUT1 IOUT2 IOUT3 AO phoa_abb Analog Current Output for each of the four DACs REFERENCES CCOMP AB phoa_abb Connect external 0.1uF cap to AVDD33A. IRSET AB phoa_abb External resistor from this node to AVSS33A defines the full scale output current for the DACs. VBIAS AB phoa_abb Connect external 0.1uF cap and 100ohm resistor to AVDD33A. VREFOUT AB phoa_abb internal / external voltage reference output SEC ASIC 2 / 15 ANALOG DAC1350X 10BIT 75MSPS Quad DAC NAME I/O I/O PAD PIN DESCRIPTION AVDD33A AP vdd3t_abb Analog Power (NEEDS 3 PIN) AVSS33A AG vss3t_abb Analog Ground (NEEDS 3 PIN) AVDD33D DP vdd3t_abb Digital Power AVSS33D DG vss3t_abb Digital Ground POWER I/O TYPE ABBR. •AI : Analog Input •DI : Digital Input •AO : Analog Output •DO : Digital Output •AB : Analog Bidirectional •DB : Digital Bidirectional •AP •AG •DP •DG SEC ASIC 3 / 15 : : : : Analog Power Analog Ground Digital Power Digital Ground ANALOG DAC1350X 10BIT 75MSPS Quad DAC AVSS33D AVDD33D AVSS33A AVSS33A AVSS33A AVDD33A AVDD33A AVDD33A AVDD33A AVDD18D CORE CONFIGURATION DATA0[9:0] DATA1[9:0] DATA2[9:0] DATA3[9:0] IOUT0 IOUT1 PDDAC[3:0] DAC1350X DACLP[3:0] IOUT2 IOUT3 SEC ASIC VBIAS VREFOUT IRSET CCOMP DTOUT CLK DACPRE BGPD DLDSEL[1:0] 4 / 15 ANALOG DAC1350X 10BIT 75MSPS Quad DAC ABSOLUTE MAXIMUM RATINGS CHARACTERISTIC SYMBOL VALUE UNIT AVDD33A - AVSS33A AVDD33D - AVSS33D -0.5 ~ 4.5 V Voltage on Any Digital Pin CLK AVSS33D-0.3 to AVDD33D+0.3 V Storage Temperature Range Tstg -45 ~ 125 ºC Supply Voltage NOTES 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to GND unless otherwise specified 3. Applied voltage must be limited to specified range. RECOMMENDED OPERATING CONDITIONS SYMBOL MIN TYP MAX UNIT Operating Supply Voltage AVDD33D,AVDD33A 3.1 3.3 3.5 V Digital Input Voltage High VIH 0.7*VDD 2.5 - V Digital Input Voltage Low VIL - 0.0 0.3*VDD V Topr 0 25 70 ºC RL - 37.5 - Ω Rset - 570 - Ω Vrefout 0.63 0.7 0.77 V Data Input Setup Time TS 4 - - ns Data Input Hold Time TH 1 - - ns Zero_level Voltage VOZ -5 0 +5 mV IRSET Current IREF 1.0 1.22 1.5 mA CHARACTERISTICS Operating Temperature Range Output Load(effective) Reference Load(effective) Resistor Internal Reference Voltage NOTES It is strongly recommended that all the supply pins (AVDD33A,AVDD33D) be powered from the same source and all the ground pins(AVSS33A,AVSS33D) avoid power latch-up. SEC ASIC 5 / 15 ANALOG DAC1350X 10BIT 75MSPS Quad DAC DC ELECTRICAL CHARACTERISTICS Characteristics Symbol Min Typ Max Unit - - - 10 Bits Ifs 33 34.8 36.5 mA Differential Linearity Error DLE -1.0 +0.4 +1.0 LSB Integral Linearity Error ILE -2.0 +1.5 ±2.0 LSB Resolution Full Scale Current per Channel Monotonicity - Guaranteed - Output Compliance VOC 0 - +1.4 V Power Dissipation PDISS - 50 100 uA NOTES 1. Converter Specifications (unless otherwise specified) : AVDD33A=AVDD33D=3.3V AVSS33A=AVSS33D=GND, 0°C< Temperature range < 70°C, Rset=570 [ohm], Rload1=Rload2=Rload3=Rload4 37.5 ohm resistor are connected to analog ground (AVSS33A). CCOMP=0.1uF capacitor is connected to analog power(AVDD33A). VBIAS = 0.1uF capacitor in series 100ohm resistor is connected to analog power(AVDD33A). AC ELECTRICAL CHARACTERISTICS Characteristics Symbol Min Typ Max Unit Minimum delay from SEL[1:0] transition to PRE transition low TselL 100 - - ns TDET_VAL 100 - - ns Minimum Pulse width low for PRE TSPWL 200 - - ns DAC to DAC Mismatch mm -2.5 - 2.5 % DAC to DAC Mismatch for any PD case. mm -2.5 - 2.5 % XTALK - -15 -10 dB PSRR -40 -45 - dB Conversion Rate FCON 75 30 - MHz Analog Output Delay Td - 10 - ns Analog Output Rise Time Tr - 1 - ns Analog Output Fall Time Tf - 1 - ns Analog Output Settling Time Tset - 33 - ns Clock & Data Feed-through FDTHR 25 30 - dB Signal-to-Noise Ratio SNDR 40 47 - dB THD 45 50 - dB Glitch Impulse Gl - ±100 ±200 pv*sec Pipeline Delay Top - 0.5 - CLK Supply Current Is - 150 200 mA Minimum delay from DACPRE transition low to valid DTOUT output 1 Cross Talk Power Supply Rejection Ratio Total Harmonic Distortion NOTE -The above parameters are not tested through the temperature range, but these are guaranteed over the full temperature range. -DAC to DAC Cross-talk is measured by holding one DAC high while the other three are making low to high and high to low transitions. SEC ASIC 6 / 15 ANALOG DAC1350X 10BIT 75MSPS Quad DAC FUNCTION DESCRIPTION This is quad 10bit 75MSPS digital to analog da t a c o nv e r te r a nd us e s c ur re n t- se gme nt arc hitec ture for 4-bits in MS B side s and binary-weighted architecture for 6-bits in LSB sides. It contains of 1'st latch block, decoder block , 2'nd latch block , OPA block , CM (c ur rent mirror ) block , BGR ( Band Ga p Reference) block, Auto-load detect block and analog switch block, etc. This core uses reference current which decide the 1LSB current by dividing the reference current by 32times. So the reference current must be constant and it can be constant by using OPA block with high DC gain. The most significant block of this core is analog switch block and it must maintain the uniformity at each switch, so layout designer must care of it. And more than 90% of supply current is dissipated at analog output side. And it uses samsung standard cell as all digital cell of latch, decoder and buffer, etc. And to adjust full current output range, you must decide the Rset value(connected to IRSET pin) and. Its voltage output ca n be obtaine d by c onne ct ing RL1(connected to IOUT0 pin) and RL2(connected to IOUT1 pin) ,RL3(connected to IOUT2 pin) and RL4(connected to IOUT3 pin) Its maximum output voltage limit is Compliance voltage. So you must decide the RL[4:1], VREFOUT and Rset carefully not to exceed the output voltage l i m i t . I t c o n t a i n s P DD AC [ 3 : 0 ] p i n s f o r power-save of each channel and BGPD for power-down mode of all blocks. Even though one or two out of 4 channels enter power-save mode, the reference block(OPA block,CM block, BGR block) is still alive, but if BGPD is activated(high), then all blocks of this core is disable regardless of PDDAC[3:0], so at this case supply current is almost just about the sum of leakage. You cant check the BGR's output vo lt a g e by c h e c ki ng t he VR EF OUT p in . SEC ASIC The user can detect the presence of an expected load on each DAC output by configuring the DAC digital inputs such that the detection comparator threshold(0.53V) is a useful threshold for presence of load resistance. Set DLDSEL[1:0] to select the appropriate DAC output. Transition PRE to low, wait for settling DTOUT value and return PRE back to high. The IRSET pin creates a +0.7[V] DC reference that can be forced with an external reference voltage pin VREFOUT. This voltage when combined with the external resistor attached to the IRSET pin sets the output current range for all quad DACs. The following example shows how to create a 1Vpk-pk output for a 100 IRE NTSC signal. Any other required variations can easily be calculated from the supplied equations. Please remember that these are ideal equations, the mismatch tolerances from the data sheet should be taken into account for any calculations. The <figure 1> diagram shows a typical relationship between DAC input and voltage output. 808 1V 10 DAC code Input An example 10-bit DAC relationship input code verse output level <figure 1> The <figure 2> diagram shows the basic bias-generator and analog current switch. From this diagram the number of DAC codes for a 1V delta output is : C100 = 808 - 10 = 798 7 / 15 ANALOG DAC1350X 10BIT 75MSPS Quad DAC DAC voltages assume the standard 140 IRE = 1V. Numbers shown are for NTSC type video with a pedestal. CCOMP Reference Generator IREF External resistor IR Current for 1 LSB <figure 2> If a standard doubly terminated 75 Ohm line is assumed : V100 1 I100 = -------- = --------- = 26.666mA RLOAD 37.5 The relationship between the IR reference current and DAC output current is shown below. IR = 32 LSB From the previous equation we have: IRSET 0.7V RSET = --------- = ------------- = 654Ω IR 1.069mA Summation of all equations gives : IRSET * C100 * RLOAD RSET = -----------------------------32 * V100 For most video applications an external resistor of 649Ω(+/− 1%) would be selected when driving doubly terminated loads (37.5Ω), and an external resistor of 1.3KΩ (+/− 1%) would be selected when driving loads of 75Ω, in order to have 798 DAC codes correspond to a 1V delta output voltage swing. Then the DAC output levels and the associated codes are as shown below. Table 1:Summary of DAC Voltage and Codes Signal Level CVBS/LUMA DAC Code IRE Value DAC Voltage 1.282V Max output 1023 137.2 100% White 810 100 1.015V Black 282 7.37 353mV Sync 12 -40 15mV White - Black 570 100 714mV delta White - Sync 798 140 1V delta Color burst 228 40 285mV delta SEC ASIC 8 / 15 ANALOG DAC1350X 10BIT 75MSPS Quad DAC TIMING DIAGRAM Analog output Delay Digital Input DI (2) D (1) DI (3) DI (4) DI (5) 1/2 CLK PIPELINE DELAY CLK td Analog Output AO (1) AO (2) AO (3) Load detection timing DAC0 DLDSEL[1:0] PRE TselL TSPWL DETECT DAC0's load detect Tdet_val Power Down timing DATA#[9:0] data#(1111111111) PDDAC# Tpn Vout(pp) IOUT(voltage measure) Tpf 0V NOTES 1. The Behavioral Modeling is provided by Verilog 2. Output delay(Td) measured from the 50% point of the rising edge of CLK to the full scale trasition 3. Settling time(Tset) measured from the 50% point of full scale transition to the output remaining within ±1LSB iteration. 4. Output rising(Tr)/falling(Tf) time measured between the 10% and 90% points of full scale transition. 5. Any power_down doesn't need clock signal. 6. PDDAC# makes the channel down respectively when it is high. 7. PDDAC# have absolutely no relations among them. 8. BGPD makes all of the blocks disable regardless of PDDAC#. 9. The minimum Pulse Width Low of BGPD should be longer than 500us. 10. The minimum Pulse Width Low of PDDAC# should be longer than 50us. 11. The minimum Pulse Width Low of BGPD and PDDAC# should be longer than 20ns. SEC ASIC 9 / 15 ANALOG DAC1350X 10BIT 75MSPS Quad DAC CORE EVALUATION GUIDE 3.3V 3.3V 3.3V L1 L1 L1 Cc + L2 Cc Cc + Ct 3.3V + Ct Cc + Ct Ct DTOUT AVSS33D AVDD33D AVSS33A AVSS33A AVDD33A AVDD33A AVSS33A AVDD33A 10 AVDD33A 10 10 10 10 DATA0[9:0] RL4 10 RL5 IOUT3 IOUT2 DATA0[9:0] HOST 10 DATA0[9:0] DSP dac1350x 10 DATA0[9:0] CORE IOUT1 DACLP[3:0] IOUT0 PDDAC[3:0] RL1 BGPD ( "0" normal operation) RL2 DACPRE DLDSEL[1:0] 10 SELECT CLK MUX CCOMP VBIAS IRSET VREFOUT Cc Cc 10 100Ω TEST PATH CLK(75MHz) RSET AVDD33A 0.7V AVDD33A * You must use more than two 3PADs for AVDD33A bcause it's current is more than about 150mA. LOCATION DESCRIPTION Cc 0.1µF Ct 10µF RSET 570Ω RL1/RL2/RL3/RL4 37.5Ω SEC ASIC 10 / 15 ANALOG DAC1350X 10BIT 75MSPS Quad DAC 1. ABOUT TESTABILITY If you want to test it over full specifications via all channel in main chip(that is, when it is used as a block of main chip) you must add many pins(for 60pins of digital inputs, 6pins of analog outputs, etc) at the main chip to test this DAC block. But usually it is nearly impossible 'cause the total number of pins at main chip is limited. So more efficient method for testing this DAC block is needed. We offer two ways of testing efficiently here as a reference. But remember this is not the best thing. You can test it by your own testing method. 2. FIRST METHOD OF TESTABILITY The first way is adding only extra 10PADs for 10bit parallel digital inputs and 3PADs for channel selecting and path selecting. You can check quad channels one by one, that is you can test only one channel at one time. Therefore you can test all three channels by turn but cannot check all channel at one time. And this method needs extra MUX and switch blocks for testing. Furthermore we can assure all channels by testing only one channel because all the quad channels have same architecture and share the same analog reference block(OPAMP, CM, BGR). This characteristic makes it simple to test this DAC block(when it is embedded in main chip) by adding another 10PADs for parallel digital inputs and 3PADs for selecting one channel analog switch block of DAC out of three channels. 3. SECOND METHOD OF TESTABILITY If above extra 13PADs are burden on you, then you can test it by this second method to reduce the extra PADs for testing. What is different from above method is that this way needs only 2 extra PADs(one for 1bit serial digital input and the other for clock signal), but you must insert extra serial to parallel converter block for converting 1bit 10times high speed digital input to 10bit parallel digital inputs. And this block may need considerable area. And this method also needs extra 3PADs for channel selecting and path selecting. 4 ANALYSIS The voltage applied to VREFOUT is measured at IRSET node . And the voltage value is proportioned to the reference current value of resistor which is connected to IRSET node. So you can estimate the full scale current value by measuring the voltage, and check the DC characteristics of the OPAMP. For reference, as VBIAS voltage applied to VREFOUT pin is given at IRSET node, the current flowing through RSET resistor(connected to IRSET pin) is given as VREF/RSET. If the voltage applied to VREFOUT pin is not same with IRSET node, you can say "This DAC chip does not work properly", because the internal OPAMP block makes the two node voltage(IRSET pin, VREFOUT pin) equal. And you have to check the CCOMP node to see the desired voltage on it. If the desired voltage is not measured, you can check the DAC output by appling a desired voltage to the CCOMP pin instead of compensation capacitor directly. If you use internal reference voltage(BGR's output voltage) instead of external Vbias by setting the BGRSW low, you can check the BGR's output by checking the VBIAS pin voltage. SEC ASIC 11 / 15 ANALOG DAC1350X 10BIT 75MSPS Quad DAC PHANTOM CELL INFORMATION - Pins of the core can be assigned externally (Package pins) or internally (internal ports) depending on design methods. The term "External" implies that the pins should be assigned externally like power pins. The term "External/internal" implies that the applications of these pins depend on the user. DATA0[9] DATA0[1] BGPD PDDAC[0] DACLP[0] DACLP[1] PDDAC[1] DATA1[0] DACPRE DATA1[9] AVDD33D AVSS33D AVSS33A Pin Name Pin Usage Pin Layout Guide AVDD33A External - Maintain the large width of lines AVSS33A External AVSS33D External as far as the pads. - place the port positions to minimize the length of power lines. - Do not merge the analog powers IRSET AVDD33D External with another power from other blocks. VBIAS dac1350x - Use good power and ground source on board. VREFOUT 10bit 75MSPS Quad-DAC CCOMP IRSET External VREFOUT External VBIAS External IOUT0 IOUT1 AVDD33A AVSS33A AVDD33A IOUT2 CCOMP External IOUT0 External IOUT3 External IOUT2 External IOUT1 External DTOUT External/Internal DLDSEL IOUT3 [1:0] AVSS33A - Maintain the larger width and the shorter length as far as the pads. - Separate from all other digital lines. External/Internal DATA3[9] DATA3[0] PDDAC[3] DACLP[3] DACLP[2] PDDAC[2] DATA2[0] DATA2[9] DLDSEL[1] DLDSEL[0] CLK DTOUT AVDD18D BGPD External/Internal CLK External/Internal DACPRE External/Internal DACLP[3:0] External/Internal PDDAC[3:0] External/Internal - Separated from the analog clean signals if possible. - Do not exceed the length by 1,000um. DATA3[9:0] External/Internal DATA2[9:0] External/Internal DATA1[9:0] External/Internal DATA0[9:0] External/Internal SEC ASIC 12 / 15 ANALOG DAC1350X 10BIT 75MSPS Quad DAC PC BOARD LAYOUT CONSIDERATIONS ♦ PC Board Considerations To minimize noise on the power lines and the ground lines, the digital inputs need to be shielded and de-coupled. This trace length between groups of vdd (AVDD33A,AVDD33A) pins short as possible so as to minimize inductive ringing. ♦ Supply De-coupling and Planes For the de-coupling capacitor between the power line and the ground line, 0.1µF ceramic capacitor is used in parallel with a 10µF tantalum capacitor. The digital power plane(AVDD33A) and analog power plane(AVDD33A) are connected through a ferrite bead, and also the digital ground plane(AVSS33A) and the analog ground plane(AVSS33A). This ferrite bead should be located within 3inches of the dac1350x The analog power plane supplies power to the dac1350x of the analog output pin and related devices. ♦Analog Signal Interconnect To minimized noise pickup and reflections due to impedance mismatch, the dac1350x should be located as close as possible to the output connector. The line between DAC output and monitor input should also be regarded as a transmission line. Due to the fact, it can cause problems in transmission line mismatch. As a solution to these problems, the double-termination methods used. By using this, both ends of the termination lines are matched, providing an ideal, non-reflective system. CORE LAYOUT GUIDE (OPTIONAL) Layout DAC core replacement • It is recommended that you use thick analog power metal. when connecting to PAD, the path should be kept as short as possible, and use branch metal to connect to the center of analog switch block. • It is recommended that you use thick analog output metal(at least more than 25µm) when connecting to PAD, and also the path length should be kept as short as possible. • Digital power and analog power are separately used. • When it is connected to other blocks, it must be double shielded using N-well and P+ active to remove the substrate and coupling noise. In that case, the power metal should be connected to PAD directly. • Bulk power is used to reduce the influence of substrate noise. • You must use more than two pins for AVDD33A because it require much current dissipation(about 93mA) • It is recommended that analog metal line(including IRSET,VREFOUT,IOUT0,IOUT1,IOUT2,IOUT3) and analog power metal line should be layout alone and should not mixed with other noisy digital metal lines. • If this core is used as a function block in larger main chip, you can join digital power metal of this core with the main digital power instead of using new digital power pad for this core. But you must use new analog power pad for the analog power of this core. SEC ASIC 13 / 15 ANALOG DAC1350X 10BIT 75MSPS Quad DAC FEEDBACK REQUEST We appreciate your interest in out products. If you have further questions, please specify in the attached form. Thank you very much. DC / AC ELECTRICAL CHARACTERISTIC Characteristics Min Typ Max Unit Supply Voltage V Power dissipation mW Resolution Bits Analog Output Voltage V Operating Temperature °C Output Load Capacitor µF Output Load Resistor Ω Integral Non-Linearity Error LSB Differential Non-Linearity Error LSB Maximum Conversion Rate MHz Remarks VOLTAGE OUTPUT DAC Reference Voltage TOP V BOTTOM Analog Output Voltage Range Digital Input Format V Binary Code or 2's Complement Code CURRENT OUTPUT DAC - Analog Output Maximum Current mA Analog Output Maximum Signal Frequency MHz Reference Voltage V External Resistor for Current Setting(RSET) Ω Pipeline Delay sec Do you want to Interal Reference Voltage(BGR)? Which do you want to Serial Input TYPE or parallel Input TYPE? Do you need 3.3v and 5v power supply in your system? How many channels do you need ? SEC ASIC 14 / 15 ANALOG DAC1350X 10BIT 75MSPS Quad DAC HISTORY CARD Version Modified Items Date Ver 1.0 Newly registered by circuit designer Kwang-Hee Lee Ver 1.1 '01.08.05 pin map , absolute maximum power , operating power range. Ver 1.2 '01.08.28 Typo correction. Ver 1.3 '01.10.20 - IOUT1,IOUT2,IOUT3,IOUT4 --> IOUT0,IOUT1,IOUT2,IOUT3 DACLP0,1,2,3 --> DACLP[3:0] PDDAC0,1,2,3 --> PDDAC[3:0] remove AVBB pin Connect 0.1uF cap between VBIAS and AVDD33A in CORE APPLICATION GUIDE - Power port AVDD33A(3EA) --> 4EA '02.03.01 -Load detect selection sequence DLDSEL(00) ⇒ IOUT0 DLDSEL(01) ⇒ IOUT2 DLDSEL(10) ⇒ IOUT1 DLDSEL(11) ⇒ IOUT3 Ver 1.5 '02.04.19 - Add New item - DAC to DAC Cross talk - DAC to DAC mismatching ( ±2.5% ) - DAC to DAC mismatch for any power down signal( ±2.5%) - Recommend connect resistor(100ohm) to VBIAS pin to AVDD33A in series capacitor(0.1uF) - Recommend resistor ( Rset=570ohm) for IFS = 34.8mA - PSRR = -40dB(min) - voltage reference variance 0.7V ±10% Ver1.6 '02.04.30 - Add New Item SNDR THD Ver 1.4 Comments SEC ASIC 15 / 15 page2 ANALOG