ESDALC6V1P6 ® QUAD LOW CAPACITANCE TRANSIL™ ARRAY FOR ESD PROTECTION Application Specific Discretes A.S.D. MAIN APPLICATIONS Where transient overvoltage protection in ESD sensitive equipment is required, such as : Computers Printers Communication systems and cellular phones Video equipment This device is particularly adapted to the protection of symmetrical signals. ■ ■ ■ ■ SOT666 FEATURES 4 UNIDIRECTIONAL TRANSIL™ FUNCTIONS. BREAKDOWN VOLTAGE VBR = 6.1V MIN. LOW DIODE CAPACITANCE (12pF @ 0V) LOW LEAKAGE CURRENT < 500 nA VERY SMALL PCB AREA < 2.6 mm2 ■ ■ ■ ■ ■ FUNCTIONAL DIAGRAM DESCRIPTION The ESDALC6V1P6 is a monolithic array designed to protect up to 4 lines against ESD transients. This device is ideal for applications where both reduced line capacitance and board space saving are required. BENEFITS High ESD protection level. High integration. Suitable for high density boards. I/O1 I/O4 GND GND I/O2 I/O3 ■ ■ ■ COMPLIES WITH THE FOLLOWING STANDARDS : ■ ■ IEC61000-4-2 level 4: 15 kV (air discharge) 8 kV (contact discharge) MIL STD 883E-Method 3015-7: class 3 25kV HBM (Human Body Model) March 2003 - Ed: 2A 1/9 ESDALC6V1P6 ABSOLUTE RATINGS (Tamb = 25°C) Symbol Parameter Test conditions VPP ESD discharge - IEC61000-4-2 air discharge IEC61000-4-2 contact discharge PPP Peak pulse power (8/20 µs) (see note 1) Tj Value Unit ± 15 ±8 kV 30 W 125 °C - 55 to + 150 °C 260 °C - 40 to + 125 °C Tj initial = Tamb Junction temperature Tstg Storage temperature range TL Maximum lead temperature for soldering during 10s at N/A Top Operating temperature range Note 1: for a surge greater than the maximum values, the diode will fail in short-circuit. THERMAL RESISTANCES Symbol Parameter Value Unit Rth(j-a) Junction to ambient on printed circuit on recommended pad layout 220 °C/W ELECTRICAL CHARACTERISTICS (Tamb = 25°C) Symbol Parameter VRM Stand-off voltage VBR Breakdown voltage VCL Clamping voltage IRM Leakage current IPP Peak pulse current αT Voltage tempature coefficient VF Forward voltage drop C Capacitance per line Rd Dynamic resistance VBR min. I IF VF VCL VBR VRM V IRM Slope: 1/Rd @ IR max. IRM @ VRM max. IPP Rd αT C typ. max. typ. Types @ 0V ESDALC6V1P6 V V mA µA V Ω 10-4/°C pF 6.1 7.2 1 0.5 3 1.5 4.5 12 Note 1 : Square pulse Ipp = 15A, tp=2.5µs. Note 2 : ∆ VBR = αT* (Tamb -25°C) * VBR (25°C) 2/9 ESDALC6V1P6 Fig. 1: Relative variation of peak pulse power versus initial junction temperature. Fig. 2: Peak pulse power versus exponential pulse duration. PPP[Tj initial] / PPP[Tj initial=25°C) PPP(W) 1.1 1000 Tj initial=25°C 1.0 0.9 0.8 0.7 0.6 100 0.5 0.4 0.3 0.2 0.1 Tp(µs) Tj(°C) 0.0 10 0 25 50 75 100 125 150 Fig. 3: Clamping voltage versus peak pulse current (typical values, rectangular waveform). 1 10 100 Fig. 4: Forward voltage drop versus peak forward current (typical values). IFM(A) IPP(A) 1.E+00 100.0 tp=2.5µs Tj initial=25°C Tj=125°C 10.0 1.E-01 1.0 1.E-02 Tj=25°C VCL(V) VFM(V) 1.E-03 0.1 0 10 20 30 40 50 60 0.0 70 Fig. 5: Junction capacitance versus reverse voltage applied (typical values). 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Fig. 6: Relative variation of leakage current versus junction temperature (typical values). C(pF) IR[Tj] / IR[Tj=25°C] 13 1000 F=1MHz VOSC=30mVRMS Tj=25°C 12 11 VR=3V 10 9 100 8 7 6 5 10 4 3 2 1 VR(V) Tj(°C) 1 0 0 1 2 3 4 5 6 25 50 75 100 125 3/9 ESDALC6V1P6 TECHNICAL INFORMATION Fig. A1: Application example. I/O2 Connector 1. ESD protection by ESDALC6V1P6 With the focus of lowering the operation levels, the problem of malfunction caused by the environment is critical. Electrostatic discharge (ESD) is a major cause of failure in electronic systems. As a transient voltage suppressor, the ESDALC6V1P6 is an ideal choice for ESD protection by suppressing ESD events. It is capable of clamping the incoming transient to a low enough level such that any damage is prevented on the device to be protected by ESDALC6V1P6. ESDALC6V1P6 serves as a parallel protection element, connected between signal line and ground. As the transient rises above the operating voltage of the device, the ESDALC6V1P6 becomes a low impedance path diverting the transient current to ground. I/O1 I/O4 I/O3 IC to be protected The clamping voltage is given by the following formula: VCL = VBR + Rd.IPP As shown in figure A2, the ESD strikes are clamped by the transient voltage suppressor. Fig. A2: ESD clamping behavior. RG IPP Rd VG RLOAD V(i/o) VBR ESD surge Device to be protected ESDALC6V1P6 I VCL = VBR +Rd x IPP slope = 1 Rd IPP V VBR VCL To have a good approximation of the remaining voltages at both Vi/o side, we provide the typical dynamical resistance value Rd. By taking into account the following hypothesis: RG > Rd and Rload > Rd we have: V V (i / o ) = V BR + Rd × g Rg The results of the calculation done for VG = 8kV, RG = 330Ω (IEC61000-4-2 standard), VBR = 6.4V (typ.) and Rd = 1.5Ω (typ.) give: V (i / o ) = 42.8Volts This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be a few tenths of volts during a few ns at the Vi/o side. 4/9 ESDALC6V1P6 Fig. A3: ESD test board. Fig. A4: ESD test configuration. ± 15kV ESD Air discharge V(i/o) I/O1, I/O2, I/O3 or I/O4 ± 15kV ESD Air discharge V(i/o) GND ESDALC6V1P6 The measurements done here after show very clearly (figure A5) the high efficiency of the ESD protection: the clamping voltage V(i/o) becomes very close to VBR (positive way, figure A5a) and -VF (negative way, figure A5b). Fig. A5: Remaining voltage during ESD surge. a: Response in the positive way b: Response in the negative way One can note that the ESDALC6V1P6 is not only acting for positive ESD surges but, also, for negative ones. For this kind of disturbances, it clamps close to ground voltage as shown in figure A5b. 5/9 ESDALC6V1P6 2. Crosstalk behavior Fig. A6: Crosstalk phenomenon. RG1 Line 1 VG1 α1VG1 + β12VG2 RL1 RG2 Line 2 VG2 α2VG2 + β21VG1 RL2 DRIVERS RECEIVERS The crosstalk phenomena are due to the coupling between 2 lines. Coupling factors ( β12 or β21 ) increase when the gap across lines decreases, particularly in silicon dice. In the example above, the expected signal on load RL2 is α2VG2, in fact the real voltage at this point has got an extra value β21VG2. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few kΩ). Fig. A7: Analog crosstalk test configuration. Fig. A8: Typical analog crosstalk response. 0.00 dB 50Ω I/O1 -10.00 unloaded -20.00 VG -30.00 Port 1 -40.00 GND -50.00 -60.00 50Ω I/O4 -70.00 -80.00 Port 2 -90.00 -100.00 100.0k 1.0M 10.0M 100.0M 1.0G f/Hz Figure A7 gives the measurement circuit for the analog crosstalk application. In figure 8, the curve shows the effect of the cell I/O1 on the cell I/O4. In usual frequency range of analog signals (up to 100 MHz) the effect on disturbed line is less than -55dB. 6/9 ESDALC6V1P6 Fig. A9: Digital crosstalk test configuration. I/O1 Fig. A10: Typical digital crosstalk response. unloaded VG1 VG1 0 - 5V pulse generator F= 100kHz tR = 20ns GND β21VG1 β21VG1 unloaded I/O4 Figure A9 shows the measurement circuit used to quantify the crosstalk effect in a classical digital application. Figure A10 shows that in such a condition, ie signal from 0 to 5V and rise time of a few ns, the impact on the disturbed line is less than 5 mV peak to peak. No data disturbance was noted on the concerned line. The measurements performed with falling edges give an impact within the same range. 3. PCB layout recommendations As ESD is a fast event, the di/dt caused by this surge is about 30A/ns (risetime=1ns, Ipeak=30A), that means each nH causes an overvoltage of 30V. Thus, the circuit board layout is a critical design step in the suppression of ESD induced transients by reducing parasitic inductances. To ensure that, the following guidelines are recommended : The ESDALC6V1P6 should be placed as close as possible to the input terminals or connectors. The path length between the ESD suppressor and the protected line should be minimized. All conductive loops, including power and ground loops should be minimized. The ESD transient return path to ground should be kept as short as possible. The connections from the ground pins to the ground plane should be the shortest possible. ■ ■ ■ ■ ■ 4. Comparison with varistors Varistors TRANSIL™ Leakage current -- +++ Protection efficiency -- ++ Ageing -- ++ Low leakage current for Transil™ device Improve the autonomy of portable equipments as mobile Better efficiency in terms of ESD protection by using Transil™ device Varistors are bidirectional devices and so are not suitable to protect sensitive ICs, because they will be submitted to high voltages in the negative way. Ratio VCL/VBR lower for Transil™ device Less dispersion in terms of VBR No ageing phenomena regarding ESD events with Transil™ device Higher efficiency in terms of ESD protection ■ ■ ■ ■ ■ 7/9 ESDALC6V1P6 ORDER CODE ESDA LC 6V1 P6 ESD ARRAY PACKAGE: SOT666 VBR min LOW CAPACITANCE Ordering type Marking Package Weight Base qty Delivery mode ESDALC6V1P6 D SOT666 2.9 mg. 3000 Tape & reel 8/9 ESDALC6V1P6 PACKAGE MECHANICAL DATA SOT-666 DIMENSIONS REF. bp D Millimeters Inches Min. Max. Min. Max. A 0.50 0.60 0.020 0.024 bp 0.17 0.27 0.007 0.011 c 0.08 0.18 0.003 0.007 D 1.50 1.70 0.060 0.067 E 1.10 1.30 0.043 0.051 E A Lp He e1 U e 1.00 0.040 e1 0.50 0.020 He 1.50 1.70 0.059 0.067 Lp 0.10 0.30 0.004 0.012 e FOOT PRINT (in millimeters) 0.36 0.30 0.62 2.30 0.84 0.20 0.20 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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