GF3443 P-Channel Logic Level Enhancement-Mode MOSFET VDS –20V RDS(ON) 65mΩ ID –4.4A SOT-23-6L 0.122 (3.10) 0.114 (2.90) ® Pin Configuration (Top View) Top View 0.118 (3.00) 0.106 (2.70) 0.067 (1.70) 0.059 (1.50) 0.020 (0.50) 0.010 (0.25) 0.037 (0.95) H C EN ET R T ENF G oduct r P New 6 5 4 1 2 3 Mounting Pad Layout Dimensions in inches and (millimeters) 0.028 (0.7) 0.075 (1.90) 0.039 (1.07) 0.004 (0.10) 0.0005 (0.013) 0.008 (0.20) 0.004 (0.10) 0.039 (1.00) 0.036 (0.90) 0.094 (2.4) 10° Typical 0.037 (0.95) Ref. 0.074 (1.9) Ref. Mechanical Data Features Case: SOT-23-6L package Terminals: Leads solderable per MIL-STD-750, Method 2026 Marking Code: 43 • Advanced trench process technology • High density cell design for ultra low on-resistance • Popular SOT-23-6L package with copper lead-frame for superior thermal and electrical capabilities • Compact and low profile • –2.5V rated Maximum Ratings and Thermal Characteristics (T Parameter Symbol Drain-Source Voltage Gate-Source Voltage TA = 25°C TA = 70°C Continuous Drain Current TJ = 150°C Pulsed Drain Current TA = 25°C TA = 70°C Maximum Power Dissipation Operating Junction and Storage Temperature Range (1) Maximum Junction-to-Ambient A = 25°C unless otherwise noted) Limit Unit VDS –20 VGS ± 12 ID – 4.4 – 3.5 IDM – 20 PD 2.0 1.3 W TJ, Tstg –55 to 150 °C RθJA 62.5 °C/W V A A Note: (1) Surface Mounted on FR4 Board, t ≤ 5 sec. 5/4/01 GF3443 P-Channel Logic Level Enhancement-Mode MOSFET Electrical Characteristics (T J Parameter = 25°C unless otherwise noted) Symbol Test Condition Min Typ Max Unit Drain-Source Breakdown Voltage BVDSS VGS = 0V, ID = –250µA –20 — — V Gate Threshold Voltage VGS(th) VDS = VGS, ID = –250µA –0.6 — — V Gate-Body Leakage IGSS VDS = 0V, VGS = ± 12V — — ± 100 nA Zero Gate Voltage Drain Current IDSS TJ = 25°C — — –1.0 TJ = 70°C — — –5.0 µA VDS ≥ –5V, VGS = –4.5V –15 — — VGS = –4.5V, ID = –4.4A — 50 65 VGS = –2.7V, ID = –3.7A — 65 90 VGS = –2.5V, ID = –3.5A — 68 100 VDS = –10V, ID = –4.4A — 12 — — 9.6 15 — 1.4 — — 2.8 — — 10 50 — 25 60 — 65 100 — 68 80 — 770 — — 210 — — 140 — Static On-State Drain Current(1) VDS = –20V VGS = 0V ID(on) (1) Drain-Source On-State Resistance RDS(on) (1) Forward Transconductance gfs A mΩ S Dynamic Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) Rise Time tr Turn-Off Delay Time td(off) Fall Time VDS = –10V, VGS = –4.5V ID = –4.4A VDD = –10V, RL = 10Ω ID ≈ –1A, VGEN = –4.5V RG = 6Ω tf Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss VDS = –10V, VGS = 0V f = 1.0MHZ nC ns pF Source-Drain Diode Maximum Diode Forward Current Diode Forward Voltage Note: (1) Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2% Switching Test Circuit IS — — — –1.7 A VSD IS = –1.7A, VGS = 0V — –0.75 –1.2 V VDD ton RD VIN VOUT D Switching Waveforms td(on) RG tr td(off) tf 90 % 90% Output, VOUT VGEN toff 10% 10% INVERTED DUT G 90% 50% S Input, VIN 50% 10% PULSE WIDTH GF3443 Ratings and Characteristic Curves (T P-Channel Logic Level Enhancement-Mode MOSFET A = 25°C unless otherwise noted) Fig. 2 – Transfer Characteristics Fig. 1 – Output Characteristics 20 VGS = -- 4.5V -- 4.0V 16 VDS = -- 10V -- 2.5V -- 3.5V 16 --ID -- Drain Current (A) --ID -- Drain-to-Source Current (A) 20 -- 3.0V 12 -- 2.0V 8 4 8 4 0 0 1 2 3 4 5 0 0.5 1 1.5 2 2.5 --VDS -- Drain-to-Source Voltage (V) --VGS -- Gate-to-Source Voltage (V) Fig. 3 – Threshold Voltage vs. Temperature Fig. 4 – On-Resistance vs. Drain Current 1.0 3 0.3 ID = --250µA RDS(ON) -- On-Resistance (Ω) --VGS(th) -- Gate-to-Source Threshold Voltage (V) TJ = 125°C 12 -- 1.5V 0 0.9 0.8 0.7 0.6 0.5 0.2 --2.5V 0.1 --2.7V VGS = --4.5V 0.4 --50 0 --25 0 25 50 75 100 125 150 Fig. 5 – On-Resistance vs. Junction Temperature 1.4 VGS = --4.5V ID = --4.4A 1.2 1 0.8 0.6 --50 --25 0 25 50 75 100 TJ -- Junction Temperature (°C) 0 5 10 -- ID -- Drain Current (A) TJ -- Junction Temperature (°C) RDS(ON) -- On-Resistance (Normalized) 25°C --55°C 125 150 15 20 GF3443 Ratings and Characteristic Curves (T P-Channel Logic Level Enhancement-Mode MOSFET A = 25°C unless otherwise noted) Fig. 6 – On-Resistance vs. Gate-to-Source Voltage Fig. 7 – Gate Charge 4.5 --VGS -- Gate-to-Source Voltage (V) 0.2 RDS(ON) -- On-Resistance (Ω) ID = --4.4A 0.15 0.1 TJ = 125°C 0.05 25°C 0 VDS = --10V ID = --4.4A 3 1.5 0 1 2 3 4 5 0 6 4 8 10 --VGS -- Gate-to-Source Voltage (V) Qg -- Gate Charge (nC) Fig. 8 – Capacitance Fig. 9 – Source-Drain Diode Forward Voltage 1200 100 VGS = 0V --IS -- Source Current (A) f = 1MHZ VGS = 0V C -- Capacitance (pF) 2 900 Ciss 600 Coss 300 10 TJ = 125°C 1 25°C 0.1 --55°C Crss 0 0 5 10 15 --VDS -- Drain-to-Source Voltage (V) 20 0.01 0 0.2 0.4 0.6 0.8 1 --VSD -- Source-to-Drain Voltage (V) 1.2 GF3443 Ratings and Characteristic Curves (T P-Channel Logic Level Enhancement-Mode MOSFET A = 25°C unless otherwise noted) Fig. 10 – Breakdown Voltage vs. Junction Temperature Fig. 11 – Thermal Impedance 1 27 D = 0.5 RΘJA (norm) -- Normalized Thermal Impedance --BVDSS -- Drain-to-Source Breakdown Voltage (V) ID = --250µA 26 25 24 --50 --25 0 25 50 75 100 125 0.2 0.1 0.1 PDM 0.05 0.02 t1 0.01 Single Pulse 0.001 0.0001 0.001 150 0.01 TJ -- Junction Temperature (°C) Fig. 12 – Power vs. Pulse Duration 0.1 1 10 100 Fig. 13 – Maximum Safe Operating Area 100 Single Pulse RθJA = 78°C/W TA = 25°C 10 --ID -- Drain Current (A) 60 50 Power (W) 1. Duty Cycle, D = t1/t2 2. RθJA (t) = RθJA(norm) *RθJA 3. RθJA = 78°C/W 4. TJ - TA = PDM * RθJA (t) Pulse Duration (sec.) 70 40 30 20 0µ s 1m 10 10 ms 10 0m 1s s 1 s RDS(ON) Limit 10s 0.1 DC VGS = --4.5V Single Pulse RθJA = 78°C/W TA = 25°C 10 0 0.001 t2 0.01 0.01 0.01 0.1 1 Pulse Duration (sec.) 10 100 0.1 1 10 --VDS -- Drain-Source Voltage (V) 100