GS71024T/U 64K x 24 1.5Mb Asynchronous SRAM TQFP, FPBGA Commercial Temp Industrial Temp Features 8, 10, 12, 15 ns 3.3 V VDD Fine Pitch BGA Bump Configuration • Fast access time: 8, 10, 12, 15 ns • CMOS low power operation: 190/160/130/110 mA at minimum cycle time. • Single 3.3 V ± 0.3 V power supply • All inputs and outputs are TTL-compatible • Fully static operation • Industrial Temperature Option: –40 to 85°C • Package T: 100-pin TQFP package U: 6 mm x 8 mm Fine Pitch Ball Grid Array Description The GS71024 is a high speed CMOS static RAM organized as 65,536 words by 24 bits. Static design eliminates the need for external clocks or timing strobes. The GS71024 operates on a single 3.3 V power supply, and all inputs and outputs are TTLcompatible. The GS71024 is available in a 6 mm x 8 mm Fine Pitch BGA package, as well as in a 100-pin TQFP package. 1 2 3 4 5 6 A DQ A3 A2 A1 A0 DQ B DQ DQ CE2 WE DQ DQ C DQ DQ CE1 OE DQ DQ D VSS DQ A5 A4 DQ VDD E VDD DQ A7 A6 DQ VSS F DQ DQ A9 A8 DQ DQ G DQ DQ A11 A10 DQ DQ H DQ A15 A14 A13 A12 DQ 6 mm x 8 mm, 0.75 mm Bump Pitch Top View Pin Descriptions Symbol Description Symbol Description A0 to A15 Address input DQ1 to DQ24 Data input/output X/Y Vector Input V/S Address Multiplexer Control WE Write enable input OE Output enable input CE1, CE2 Chip enable input — — VDD +3.3 V power supply VSS Ground Block Diagram A0 Row Decoder Memory Array 1024 x 1536 Address Input A14 A15 X/Y V/S CE1 CE2 WE 0 1 Column Decoder Q I/O Buffer Control OE DQ1 Rev: 1.03 11/2000 DQ24 1/13 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71024T/U NC A13 A12 A11 A10 A9 A8 NC NC VSS DQ19 DQ20 VDD VSS DQ21 DQ22 DQ23 DQ24 NC NC NC NC NC Rev: 1.03 11/2000 NC NC NC NC NC DQ12 DQ11 DQ10 DQ9 VSS VDD DQ8 DQ7 VSS NC VDD NC DQ6 DQ5 VDD VSS DQ4 DQ3 DQ2 DQ1 NC NC NC NC NC NC NC A7 A6 A5 A4 A3 A2 NC NC VSS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 Top View 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDD NC NC NC NC NC DQ13 DQ14 DQ15 DQ16 VSS VDD DQ17 DQ18 NC VDD VDD VSS NC WE NC OE NC NC NC A0 A1 A14 A15 CE1 CE2 NC NC NC X/Y V/S 100-Pin TQFP Pinout 2/13 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71024T/U Truth Table CE1 CE2 OE WE V/S Mode DQ0 to DQ23 H X X X X Not selected High Z X L X X X Not selected High Z L H L H H Read using X/Y Data Out L H L H L Read using A15 Data Out L H X L H Write using X/Y Data In L H X L L Write using A15 Data In L H H H X Output disable High Z VDD Current ISB1, ISB2 IDD X: “H” or “L” Absolute Maximum Ratings Parameter Symbol Rating Unit Supply Voltage VDD –0.5 to +4.6 V Input Voltage VIN –0.5 to VDD + 0.5 (≤ 4.6 V max.) V Output Voltage VOUT –0.5 to VDD + 0.5 (≤ 4.6 V max.) V Allowable TQFP power dissipation PD 1 W Allowable FPBGA power dissipation PD 1 W Storage temperature TSTG –55 to 150 o C Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. Rev: 1.03 11/2000 3/13 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71024T/U Recommended Operating Conditions Parameter Symbol Minimum Typical Maximum Unit Supply Voltage for -10/12/15 VDD 3.0 3.3 3.6 V Supply Voltage for -8 VDD 3.135 3.3 3.6 V Input High Voltage VIH 2.0 — VDD + 0.3 V Input Low Voltage VIL –0.3 — 0.8 V Ambient Temperature, Commercial Range TAc 0 — 70 o Ambient Temperature, Industrial Range TAi –40 — 85 o C C Notes: 1. Input overshoot voltage should be less than VDD + 2 V and not exceed 20 ns. 2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns. Capacitance Parameter Symbol Test Condition Maximum Unit Input Capacitance CIN VIN = 0 V 5 pF I/O Capacitance COUT VOUT = 0 V 7 pF Notes: 1. Tested at TA = 25°C, f = 1 MHz 2. These parameters are sampled and are not 100% tested DC I/O Pin Characteristics Parameter Symbol Test Conditions Minimum Maximum Input Leakage Current IIL VIN = 0 to VDD –1uA 1uA Output Leakage Current IOL Output High Z, VOUT = 0 to VDD –1uA 1uA Output High Voltage VOH IOH = –4mA 2.4 — Output Low Voltage VOL IOL = +4mA — 0.4 V Rev: 1.03 11/2000 4/13 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71024T/U AC Test Conditions Output Load 1 Parameter Conditions Input high level VIH = 2.4 V Input low level VIL = 0.4 V Input rise time tr = 1 V/ns Input fall time tf = 1 V/ns Input reference level 1.4 V Output Load 2 Output reference level 1.4 V 3.3 V Output load Fig. 1& 2 DQ 50Ω 30pF1 VT = 1.4 V 589Ω DQ Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted 3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ. 5pF1 434Ω Power Supply Currents Parameter Operating Supply Current Standby Current Standby Current Rev: 1.03 11/2000 Symbol Test Conditions 0 to 70°C -40 to 85°C 8 ns 10 ns 12 ns 15 ns 10 ns 12 ns 15 ns IDD CE ≤ VIL All other inputs ≥ VIH or ≤ VIL Min. cycle time IOUT = 0 mA 190 mA 160 mA 130 mA 110 mA 165 mA 135 mA 115 mA ISB1 CE ≥ VIH All other inputs ≥ VIH or ≤VIL Min. cycle time 45 mA 40 mA 35 mA 30 mA 45 mA 40 mA 35 mA ISB2 CE ≥ VDD – 0.2 V All other inputs ≥ VDD – 0.2 V or ≤ 0.2 V 10 mA 5/13 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 15 mA © 1999, Giga Semiconductor, Inc. GS71024T/U AC Characteristics Read Cycle Parameter Symbol -8 -10 -12 -15 Min Max Min Max Min Max Min Max Unit Read cycle time tRC 8 — 10 — 12 — 15 — ns Address access time tAA — 8 — 10 — 12 — 15 ns Chip enable access time (CE1, CE2) tAC — 8 — 10 — 12 — 15 ns MUX control to output valid (V/S) tAV — 8 — 10 — 12 — 15 ns Output enable to output valid (OE) tOE — 4 — 5 — 6 — 7 ns Output hold from address change tOH 3 — 3 — 3 — 3 — ns Output hold from MUX controls change tOH1 3 — 3 — 3 — 3 — ns Chip enable to output in low Z (CE1, CE2) tLZ* 3 — 3 — 3 — 3 — ns Output enable to output in low Z (OE) tOLZ* 0 — 0 — 0 — 0 — ns Chip disable to output in High Z (CE1, CE2) tHZ* — 4 — 5 — 6 — 7 ns Output disable to output in High Z (OE) tOHZ* — 4 — 5 — 6 — 7 ns * These parameters are sampled and are not 100% tested Rev: 1.03 11/2000 6/13 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71024T/U Read Cycle 1: CE = OE = VIL, WE = VIH tRC Address tAA V/S tOH Data Out Previous Data Data valid tOH1 tAV Read Cycle 2: WE = VIH tRC Address tAA CE1(*1) tAC tHZ tLZ tAV V/S OE Data Out tOLZ High impedance tOE tOHZ Data valid *1 CE1 represents both CE1 low and CE2 high. Rev: 1.03 11/2000 7/13 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71024T/U Write Cycle Parameter Symbol -8 -10 -12 -15 Min Max Min Max Min Max Min Max Unit Write cycle time tWC 8 — 10 — 12 — 15 — ns Address valid to end of write tAW 5.5 — 7 — 8 — 10 — ns Chip enable to end of write (CE1, CE2) tCW 5.5 — 7 — 8 — 10 — ns MUX control to end of write (V/S) tVW 5.5 — 7 — 8 — 10 — ns Data set up time tDW 4 — 5 — 6 — 7 — ns Data hold time tDH 0 — 0 — 0 — 0 — ns Write pulse width tWP 5.5 — 7 — 8 — 10 — ns Address set up time tAS 0 — 0 — 0 — 0 — ns MUX control set up time tVS 0 — 0 — 0 — 0 — ns Write recovery time (WE) tWR 0 — 0 — 0 — 0 — ns Write recovery time (V/S, CE1, CE2 ) tWR1 0 — 0 — 0 — 0 — ns Output Low Z from end of write tWLZ* 2 — 3 — 3 — 3 — ns Write to output in High Z tWHZ* — 4 — 5 — 6 — 7 ns * These parameters are sampled and are not 100% tested Rev: 1.03 11/2000 8/13 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71024T/U Write Cycle 1: WE control tWC Address tAW tWR OE tCW CE1(*1) tVW tVS V/S tAS tWP WE (*2) tDW Data In tDH Data valid tWHZ tWLZ Data Out High impedance (*3) (*3) *1 CE1 represents both CE1 low and CE2 high. *2 Write is executed when both CE1 and WE are at low simultaneously. *3 Do not apply the data input voltage to the output while DQ pin is in output condition. Write Cycle 2: CE control tWC Address tAW tWR1 OE tAS CE1 tCW (*1) tVW V/S tWP WE tDW Data In tDH Data valid Data Out High impedance *1 CE1 represents both CE1 low and CE2 high. Rev: 1.03 11/2000 9/13 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71024T/U 6 mm x 8 mm Fine Pitch BGA 0.36(typ) D H G F E D C B A 0.22 ± 0.05 1 Ball Dia. 0.35 Pitch 0.75 0.75(typ). 5.25 10/13 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 3.75 2 3 4 6 5 Bottom View pin A1 index 1.20(max) pin A1 index units: mm Top View 6.00 ± 0.10 8.00 ± 0.10 Rev: 1.03 11/2000 0.10 © 1999, Giga Semiconductor, Inc. GS71024T/U TQFP Package Drawing Description Min. Nom. Max A1 Standoff 0.05 0.10 0.15 A2 Body Thickness 1.35 1.40 1.45 b Lead Width 0.20 0.30 0.40 c Lead Thickness 0.09 D Terminal Dimension 21.9 22.0 22.1 D1 Package Body 19.9 20.0 20.1 E Terminal Dimension 15.9 16.0 16.1 E1 Package Body 13.9 14.0 14.1 e Lead Pitch L Foot Length L1 Lead Length Y Coplanarity θ Lead Angle c 0.20 0.60 D D1 0.65 0.45 L1 θ Pin 1 Symbol L e b 0.75 1.00 0.10 0° 7° A1 A2 Y Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion E1 E BPR 1999.05.18 Rev: 1.03 11/2000 11/13 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71024T/U Ordering Information Part Number Package Access Time Temp. Range GS71024T-8 100-Pin TQFP 8 ns Commercial GS71024T-10 100-Pin TQFP 10 ns Commercial GS71024T-12 100-Pin TQFP 12 ns Commercial GS71024T-15 100-Pin TQFP 15 ns Commercial GS71024T-8I 100-Pin TQFP 8 ns Industrial GS71024T-10I 100-Pin TQFP 10 ns Industrial GS71024T-12I 100-Pin TQFP 12 ns Industrial GS71024T-15I 100-Pin TQFP 15 ns Industrial GS71024U-8 6 mm x 8 mm Fine Pitch BGA 8 ns Commercial GS71024U-10 6 mm x 8 mm Fine Pitch BGA 10 ns Commercial GS71024U-12 6 mm x 8 mm Fine Pitch BGA 12 ns Commercial GS71024U-15 6 mm x 8 mm Fine Pitch BGA 15 ns Commercial GS71024U-8I 6 mm x 8 mm Fine Pitch BGA 8 ns Industrial GS71024U-10I 6 mm x 8 mm Fine Pitch BGA 10 ns Industrial GS71024U-12I 6 mm x 8 mm Fine Pitch BGA 12 ns Industrial GS71024U-15I 6 mm x 8 mm Fine Pitch BGA 15 ns Industrial Status Not Available Not Available * Customers requiring Tape and Reel should add the character “T” to the end of the part number. For example: GS71024T/U-12T. Rev: 1.03 11/2000 12/13 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71024T/U Revision History Rev. Code: Old; New Types of Changes Format or Content Format/Typos GS71024Rev 2:17pm, 4/8/ 1999; 1.00a5/1999 Page/Revisions/Reason • Document Changed subscripts to small caps. • 1/Features: Changed TP to T. • Document/Replaced “micro” with “fine pitch”. Content • Ordering Information/Added Tape and Reel Note/ Enhancement • Pin Description/Changed A0 - A14 to A0 - A15/Correction • Page 1/Took out “Byte Control” from Features/Correction • 3/Changed pin 97 from NC to CE2/Correction • GS710241.00a5/1999; 1.01 8/1999B Content 1. 2. 3. 4. GS710241.01 8/1999C; 1.02 9/1999C Content • Package Diagram/Changed Dimension “D Max” from 20.1 to 22.1/Correction GS71024Rev1.01 8/ 1999C;Rev1.02 2/2000D Format Rev1.02 2/2000D; 71024_r1_03 Rev: 1.03 11/2000 Pin out/Changed Pin 89 from CK to NC/Correction Pin out/Changed Pin 92 from NC to V/S/Correction Pin out/Changed Pin 93 from V/S to X/Y/Correction Pin out/Changed Pin 94 from X/Y to NC/Correction • GSI Logo • Updated format to comply with Technical Publications standards • Changed all VSSQ to VSS and all VDDQ to VDD in pinout on Format and Content page 2 • Updated Revision History (revision notes for 8/1999 incorrect) 13/13 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc.