Revised December 2000 GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver with High Drive GTLP and Individual Byte Controls General Description Features The GTLP16T1655 is a 16-bit universal bus transceiver that provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD8-3. ■ Bidirectional interface between GTLP and LVTTL logic levels Fairchild’s GTLP has internal edge-rate control and is process, voltage, and temperature (PVT) compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V. ■ Variable edge rate control pin to select desired edge rate on the GTLP backplane (VERC) ■ VREF pin provides external supply reference voltage for receiver threshold adjustibility ■ Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature ■ TTL compatible driver and control inputs ■ Designed using Fairchild advanced BiCMOS technology ■ Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs ■ Power up/down and power off high impedance for live insertion ■ Open drain on GTLP to support wired-or connection ■ Flow through pinout optimizes PCB layout ■ D-type flip-flop, latch and transparent data paths ■ A Port source/sink −24mA/+24mA ■ B Port sink +100mA ■ Partitioned as two 8-bit transceivers with individual latch timing and output control but with a common clock ■ External pin to pre-condition I/O capacitance to high state (VCCBIAS) Ordering Code: Order Number Package Number Package Description GTLP16T1655MTD MTD64 64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2000 Fairchild Semiconductor Corporation DS500172 www.fairchildsemi.com GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver with High Drive GTLP and Individual Byte Controls August 1998 GTLP16T1655 Connection Diagram Pin Descriptions Pin Names Description 1OEAB A-to-B Output Enable (Active LOW) 2OEAB Byte 1 and Byte 2 1OEBA B-to-A Output Enable (Active LOW) 2OEBA Byte 1 and Byte 2 OE Disables all I/O ports simultaneously 1LEAB A-to-B Latch Enable (Transparent HIGH) 2LEAB Byte 1 and Byte 2 1LEBA B-to-A Latch Enable (Transparent HIGH) 2LEBA Byte 1 and Byte 2 VREF GTLP Reference Voltage CLK A-to-B and B-to-A Clock 1A1-1A8 A Port I/O Byte 1 and Byte 2 2A1-2A8 1B1-1B8 B Port I/O Byte 1 and Byte 2 2B1-2B8 Truth Tables (Note 1) Inputs Output Mode OEAB LEAB CLK A B H X X X Z L H X L L Transparent L H X H H Transparent L L ↑ L L Registered L L ↑ H H Registered L L H X B0 (Note 2) Previous State L L L X B0 (Note 3) Previous State Inputs OE OEAB (Note 4) L L Outputs High Impedance Inputs Output Edge VERC B Port OEBA (Note 4) A Port B Port L L Active Active VCC Slow L H Z Active GND Fast L H L Active Z L H H Z Z H X X Z Z Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLK. Note 2: Output level before the indicated steady state input conditions were established, provided CLK was HIGH prior to LEAB going LOW. Note 3: Output level before the indicated steady state input conditions were established. Note 4: OEAB and OEBA are byte-wide enables. Each is proceeded by a number indicating the byte controlled. www.fairchildsemi.com 2 The GTLP16T1655 is a high drive (100 mA) 16-bit universal bus transceiver containing D-type flip-flop, latch and transparent modes of operation for the data path. The device is uniquely partitioned as two 8-bit transceivers with individual latch timing and output control signals but with a common clock pin (CLK) for both transceiver words. Data flow for each word is determined by the respective latch enables (xLEAB and xLEBA), output enables (xOEAB and xOEBA) and clock (CLK). The output enables (1OEAB, 1OEBA, and 2OEAB and 2OEBA) control Byte1 and Byte2 data for the A to B and B to A directions respectively. For A-to-B data flow, the devices operate in the transparent mode when LEAB is HIGH. When LEAB transitions LOW, the A data is latched independent of CLK HIGH or LOW. If LEAB is LOW the A data is registered on the CLK LOW-to-HIGH transition. When OEAB is LOW the outputs are active. With OEAB HIGH the outputs are HIGH impedance. Data flow for the B-to-A direction is identical but uses OEBA, LEBA and CLK. Note that CLK is common to both directions and both 8-bit words. OE is also common and is used to disable all I/O ports simultaneously. Logic Diagrams 3 www.fairchildsemi.com GTLP16T1655 Functional Description GTLP16T1655 Absolute Maximum Ratings(Note 5) Supply Voltage (VCC) −0.5V to +4.6V DC Input Voltage (VI) −0.5V to +4.6V Recommended Operating Conditions Outputs 3-STATE −0.5V to +4.6V Outputs Active (Note 6) −0.5V to + 4.6V 3.0V to 3.6V Supply Voltage VCC DC Output Voltage (VO) Bus Termination Voltage (VTT) DC Output Sink Current into GTLP 1.35V to 1.65V GTL 1.14V to 1.26V VREF A Port IOL 48 mA GTLP DC Output Source Current from 0.87V to 1.1V GTL −48 mA A Port IOH 0.74V to 0.87V Input Voltage (VI) DC Output Sink Current on A Port and Control Pins into B Port in the LOW State, 200 mA 0.0V to VCC on B Port IOL (Note 7) 0.0V to Vtt HIGH Level Output Current (IOH) DC Input Diode Current (IIK) −50 mA LOW Level Output Current (IOL) DC Output Diode Current (IOK) VO < 0V −50 mA VO > VCC +50 mA ESD Rating >2000V Storage Temperature (TSTG) −24 mA A Port VI < 0V A Port +24mA B Port +100 mA −40°C to +85°C Operating Temperature (TA) Note 5: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. −65°C to +150°C Note 6: IO Absolute Maximum Rating must be observed. Note 7: VTT and Rterm can be adjusted to accommodate backplane impedances other than 50Ω, within the boundaries of not exceeding the DC Absolute IOL ratings (200 mA). Similarly VREF can be adjusted to compensate for changes in VTT. DC Electrical Characteristics Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted). Symbol VIH VIL Min Test Conditions Typ B Port VREF +0.05 Others 2.0 B Port 0.0 VREF VOH GTLP VOL A Port A Port B Port II IOFF 0.74 VCC = 3.0V II = −18 mA VCC = Min to Max (Note 9) IOH = −100 µA VCC −0.2 VCC = 3.0V IOH = −12 mA 2.4 IOH = −24 mA 2.2 VTT V 1.0 VREF −0.05 V 0.8 V 1.1 V −1.2 V V VCC = Min to Max (Note 9) IOL = 100 µA 0.20 VCC = 3.0V IOL = 12 mA 0.40 IOL = 24 mA 0.50 IOL = 40 mA 0.20 VCC = 3.0V V IOL = 80 mA 0.40 IOL = 100 mA 0.50 VCC = 3.6V VI = VCC or 0V ±10 µA Control Pins VCC = 3.6V VI = VCC or 0V ±10 µA µA A Port B Port VCC = 3.6V VI = VTT or GND ±10 Except VCC = 0 VI or VO = 0 to 100 VERC II(hold) Units V Others VIK Max (Note 8) A Port VCC VCC = 3.0V VCC = 3.6V www.fairchildsemi.com VI = 0.8V 75 VI = 2.0V −75 VI = 0 to VCC 4 V µA µA ±500 Symbol IOZH A Port (Continued) VCC = 3.6V B Port A Port IOZL VCC = 3.6V B Port A Port IOZPU VCC = 0 to 1.5V A Port Max Units VO = V CC 10 VO = 1.5V 10 µA VO = 0V −10 VO = 0.4V −10 VO = 0.5 to 3V ±50 µA VO = 0.5 to 3V ±50 µA µA VCC = 1.5 to 0V OE = 0 or VCC (Note 10) A or B Ports VCC = 3.6 ICC Typ (Note 8) OE = 0 or VCC (Note 10) IOZPD Min Test Conditions (vcc) Outputs HIGH 55 IO = 0 Outputs LOW 55 VI = V CC or GND Outputs Disabled 55 VCC = 3.6V One Input at ∆ICC A Port and (Note 11) Control Pins A or Control 0 mA 1 VCC–0.6 mA Inputs at VCC or GND Ci Control Pins VI = VCC or 0 5.8 7.0 A Port VI = VCC or 0 8.0 9.5 B Port VI = VCC or 0 8.3 9.9 pF Note 8: All typical values are at VCC = 3.3V, and TA = 25°C. Note 9: For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. Note 10: This is specified by characterization but not tested. Note 11: This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. Live Insertion Characteristics Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted). Parameter ICC B Port (VCCBIAS) Test Conditions Min Typ Max Units VCC = 0 to 3V VO = 0 to 1.2V 5 mA VCC = 3.0 to 3.6V VI (VCCBIAS) = 3 to 3.6V 10 µA VO B Port VCC = 0 VI (VCCBIAS) = 3.3v IO B Port VCC = 0 VI (VCCBIAS) = 3 to 3.6V 1.1 VO = 0.4 V −1 VCC = 0 to 3.6V OE = 3.3V 100 VCC = 0 to 1.5V OE = 0 to 3.3V 100 µA AC Operating Requirements (GTLP) Over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5V and Vref = 1.0V (unless otherwise noted). Parameter fMAX Maximum Clock Frequency tWIDTH Pulse Duration tSU tHOLD Min 160 LE HIGH 3.0 CLK HIGH or LOW 3.0 Max Unit MHz ns Setup Time Hold Time Data before CLK↑ 2.5 Data before LE↓ (CLK = X) 2.5 Data after CLK↑ 0.5 Data after LE↓ (CLK = X) 0.5 5 ns ns www.fairchildsemi.com GTLP16T1655 DC Electrical Characteristics GTLP16T1655 B to A AC Electrical Characteristics (GTLP) Over recommended range of supply voltage and operating free-air temperature, VREF = 1.0V, VTT = 1.5V, VERC = VCC or GND (unless otherwise noted). CL = 30 pF for B Port and CL = 50 pF for A Port. From To (Input) (Output) B A Min Typ Max Unit Parameter fMAX tPLH 160 LEAB A CLK A OE A OEBA A 1.2 4.0 1.2 3.8 1.2 4.0 1.2 4.0 1.4 4.5 1.0 4.0 1.2 4.9 1.0 4.0 ns tPZH/ZL Note 12: All typical values are at VCC = 3.3V, and TA = 25°C. www.fairchildsemi.com 4.8 ns tPZH/ZL tPLZ/HZ 1.5 ns tPHL tPLZ/HZ 4.7 ns tPHL tPLH MHz 1.0 ns tPHL tPLH (Note 12) 6 AC Electrical Characteristics (GTLP) Over recommended range of supply voltage and operating free air temperature, V = 1.0V, VTT = 1.5V (unless otherwise noted). CL = 30 pF for B Port and CL = 50 pF for A Port. From To (Input) (Output) tPLH A B tPHL VERC = VCC Min Type Max Units Symbol (Note 13) fMAX 160 tPLH A tPHL VERC = GND tPLH LEAB tPHL VERC = VCC tPLH LEAB tPHL VERC = GND tPLH CLK tPHL VERC = VCC tPLH CLK tPHL VERC = GND tPLH OE tPHL VERC = VCC tPLH OE tPHL VERC = GND tPLH OEAB tPHL VERC = VCC tPLH OEAB tPHL VERC = GND tFALL/RISE VERC = V CC tFALL/RISE VERC = GND MHz 2.6 5.7 0.8 4.5 2.0 4.9 0.7 4.0 2.6 5.7 0.8 4.0 2.2 4.9 0.7 4.0 2.8 5.7 1.0 4.0 2.3 5.0 0.8 4.0 ns B ns B ns B ns B ns B ns B 2.7 5.8 0.6 4.0 2.1 4.9 1.0 4.0 ns B ns B 2.6 5.8 0.6 4.0 2.0 4.9 0.6 3.5 ns B ns Transition Time, B outputs (0.6V to 1.3V) 0.7/0.7 2.0/2.5 ns Transition Time, B outputs (0.6V to 1.3V) 0.7/0.7 1.5/2.0 ns Note 13: All Typical values are at VCC = 3.3V and TA = 25°C 7 www.fairchildsemi.com GTLP16T1655 A to B GTLP16T1655 Extended Electrical Characteristics (GTLP) Over recommended ranges of supply voltage and operating free-air temperature VREF = 1.0V (unless otherwise noted). CL = 30 pF for B Port and CL = 50 pF for A Port. Symbol tOSLH (Note 15) From To (Input) (Output) Min (Note 14) A B tOSHL (Note 15) tPV(HL) (Note 16) (Note 17) tOSLH (Note 15) tOSLH (Note 15) tPV (Note 16) tOSLH(Note 15) Unit 0.4 1.0 ns 0.4 1.0 ns B CLKAB B CLKAB B B A 0.3 0.3 1.0 ns B A 0.6 1.5 ns B A 1.6 ns CLKAB A 0.3 0.3 tOSHL (Note 15) tOST (Note 15) Max A tOSHL (Note 15) tPV(HL) (Note 16)(Note 17) Typ tOSHL (Note 15) tOST(Note 15) CLKAB A tPV (Note 16) CLKAB A 1.5 ns 0.9 ns 0.6 ns 1.2 ns 1.0 ns 0.3 0.6 ns 0.3 0.6 ns 0.5 1.0 ns 1.1 ns Note 14: All typical values are at VCC = 3.3V, and TA = 25°C. Note 15: tOSHL/tOSLH and tOST—Output to output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs within the same packaged device. The specifications are given for specific worst case VCC and temperature and apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH) or in opposite directions both HL and LH (tOST). This parameter is guaranteed by design and statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device. Note 16: tPV—Part to part skew is defined as the absolute value of the difference between the actual propagation delay for all outputs from device to device. The parameter is specified for a specific worst case VCC and temperature. This parameter is guaranteed by design and statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device. Note 17: Due to the open drain structure on GTLP outputs, tOST and tPV(LH) in the A-to-B direction are not specified. Skew on these paths is dependent on the VTT and RT values on the backplane. www.fairchildsemi.com 8 Over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.2V and Vref = 0.8V (unless otherwise noted). Parameter fMAX Maximum Clock Frequency tWIDTH Pulse Duration tSU Setup Time tHOLD B to A Hold Time Min Max 160 Units MHz LE HIGH 3.0 ns CLK HIGH or LOW 3.0 ns Data before CLK↑ 2.5 Data before LE↓ (CLK = X) 2.5 Data after CLK↑ 0.5 Data after LE↓ (CLK =X) 0.5 ns ns AC Electrical Characteristics (GTL) Over recommended range of supply voltage and operating free air temperature, Vref = 0.8V, VTT = 1.2V, VERC = VCC or GND (unless otherwise noted). CL = 30pF for B Port and CL = 50 pF for A Port. From To (Input) (Output) Min Typ Max B A 1.0 4.7 1.2 4.8 LEBA A 1.0 4.4 1.1 4.0 1.0 4.2 1.1 4.1 1.5 4.6 1.2 4.2 1.2 4.9 1.0 4.0 Units Parameter (Note 18) 160 fMAX tPLH tPHL tPLH tPHL tPLH CLK A OE A OEBA A tPHL tPLZ/HZ tPZH/ZL tPLZ/HZ tPZH/ZL MHz ns ns ns ns ns Note 18: All Typical values are at VCC = 3.3V and TA = 25°C. 9 www.fairchildsemi.com GTLP16T1655 AC Operating Requirements (GTL) GTLP16T1655 A to B AC Electrical Characteristics (GTL) Over recommended range of supply voltage and operating free air temperature, VREF = 0.8V, VTT = 1.2V (unless otherwise noted). CL = 30 pF for B Port and CL = 50 pF for A Port. From To (Input) (Output) Min tPLH A B tPHL VERC = VCC tPLH A tPHL VERC = GND Typ Max Units Symbol 160 fMAX tPLH LEAB tPHL VERC = VCC tPLH LEAB tPHL VERC = GND tPLH CLK tPHL VERC = VCC tPLH CLK tPHL VERC = GND tPLH OE tPHL VERC = VCC tPLH OE tPHL VERC = GND tPLH OEAB tPHL VERC = VCC tPLH OEAB tPHL VERC = GND tFALL/RISE VERC = VCC tFALL/RISE VERC = VCC MHz 2.2 5.7 1.0 4.7 1.5 4.8 0.9 4.0 ns B ns B 2.2 5.7 1.0 4.1 1.7 5.0 0.9 4.4 ns B ns B 2.8 5.8 1.0 4.3 2.3 5.0 1.0 4.3 2.5 5.8 0.8 4.3 1.7 4.9 0.9 4.3 2.2 5.8 0.8 4.3 1.7 4.9 0.9 3.8 ns B ns B ns B ns B ns B ns Transition Time, B outputs (0.6V to 1.3V) 0.7/0.7 2.0/2.5 ns Transition Time, B outputs (0.6V to 1.3V) 0.7/0.7 1.5/2.0 ns Note 19: All Typical values are at VCC = 3.3V and TA = 25°C. www.fairchildsemi.com (Note 19) 10 Over recommended ranges of supply voltage and operating free-air temperature VREF = 0.8V (unless otherwise noted). CL = 30 pF for B Port and CL = 50 pF for A Port. Symbol tOSLH (Note 21) From To (Input) (Output) A B tOSHL (Note 21) tPV(HL) (Note 22) (Note 23) tOSLH (Note 21) A B CLKAB B tOSHL (Note 21) tPV(HL) (Note 22)(Note 23) tOSLH (Note 21) CLKAB B B A tOSHL (Note 21) tOST (Note 21) B A tPV (Note 22) B A CLKAB A tOSLH(Note 21) tOST(Note 21) CLKAB A CLKAB A Typ Max Unit (Note 20) 0.4 1.0 ns 0.4 1.0 ns 1.5 ns 0.3 0.9 ns 0.3 0.6 ns 1.2 ns 0.3 1.0 ns 0.3 1.0 ns 0.6 tOSHL (Note 21) tPV (Note 22) Min 1.5 ns 1.6 ns 0.3 0.6 ns 0.3 0.6 ns 0.5 1.0 ns 1.1 ns Note 20: All typical values are at VCC = 3.3V, and TA = 25°C. Note 21: tOSHL/tOSLH and tOST—Output to output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs within the same packaged device. The specifications are given for specific worst case VCC and temperature and apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH) or in opposite directions both HL and LH (tOST). This parameter is guaranteed by design and statistical process distribution. Actual skew values between the GTL outputs could vary on the backplane due to the loading and impedance seen by the device. Note 22: tPV—Part to part skew is defined as the absolute value of the difference between the actual propagation delay for all outputs from device to device. The parameter is specified for a specific worst case VCC and temperature. This parameter is guaranteed by design and statistical process distribution. Actual skew values between the GTL outputs could vary on the backplane due to the loading and impedance seen by the device. Note 23: Due to the open drain structure on GTL outputs, tOST and tPV(LH) in the A-to-B direction are not specified. Skew on these paths is dependent on the VTT and RT values on the backplane. 11 www.fairchildsemi.com GTLP16T1655 Extended Electrical Characteristics (GTL) GTLP16T1655 Test Circuits and Timing Waveforms Test Circuit for A Outputs Test S tPLH/tPHL Open tPLZ/tPZL 6V tPHZ/tPZH GND Test Circuit for B Outputs Note A: C L includes probes and Jig capacitance. Note B: For B Port, C L = 30 pF is used fort worst case. Voltage Waveform - Propagation Delay Times Voltage Waveform - Setup and Hold Times Voltage Waveform - Pulse Width Voltage Waveform - Enable and Disable Times Output Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the control output Output Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the control output Input and Measure Conditions A or LVTTL Pins B or GTLP Pins VinHIGH 3.0 1.5 VinLOW 0.0 0.0 VM 1.5 1.0 VX VOL + 0.3V N/A VY VOH − 0.3V N/A All input pulses have the following characteristics: Frequency = 10MHz, tRISE = t FALL = 2 ns, ZO = 50Ω The outputs are measured one at a time with one transition per measurement www.fairchildsemi.com 12 64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD64 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 13 www.fairchildsemi.com GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver with High Drive GTLP and Individual Byte Controls Physical Dimensions inches (millimeters) unless otherwise noted