ETC HD74SSTL16857

HD74SSTL16857
a
14-bit SSTL_2 Registered Buffer
ADE-205-223C (Z)
4th. Edition
May 1999
Description
The HD74SSTL16857 is a 14-bit registered buffer designed for 2.3 V to 3.6 V Vcc operation and LVCMOS
reset (RESET) input / SSTL_2 data (D) inputs and CLK input.
Data flow from D to Q is controlled by differential clock pins (CLK, CLK) and the RESET. Data is triggered
on the positive edge of the positive clock (CLK), and the negative clock (CLK) must be used to maintain noise
margins. When RESET is low, all registers are reset and all outputs are low.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
Features
•
•
•
•
Supports LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input
Differential SSTL_2 (Stub series terminated logic) CLK signal
Flow through architecture optimizes PCB layout
Meets SSTL_2 Class I and Class II specifications
Function Table
Inputs
Output Q
CLK
RESET
CLK
D
L
X
X
X
L
H
↓
↑
H
H
H
↓
↑
L
L
H
L or H
H or L
X
Q0 *1
H:
High level
L:
Low level
X:
Immaterial
↑:
Low to high transition
↓:
High to low transition
Note:
1.Output level before the indicated steady state input conditions were established.
HD74SSTL16857
Pin Arrangement
Q1 1
48 D1
Q2 2
47 D2
GND 3
46 GND
V DDQ 4
45 V CC
Q3 5
44 D3
Q4 6
43 D4
Q5 7
42 D5
GND 8
41 D6
V DDQ 9
40 D7
Q6 10
39 CLK
Q7 11
38 CLK
V DDQ 12
37 V CC
GND 13
36 GND
Q8 14
35 V REF
Q9 15
34 RESET
V DDQ 16
33 D8
GND 17
32 D9
Q10 18
31 D10
Q11 19
30 D11
Q12 20
29 D12
V DDQ 21
28 V CC
GND 22
27 GND
Q13 23
26 D13
Q14 24
25 D14
(Top view)
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Supply voltage
VCC or VDDQ
–0.5 to 4.6
V
Input voltage *1
VI
–0.5 to VDDQ+0.5
V
Output voltage
*1, 2
Conditions
VO
–0.5 to VDDQ+0.5
V
Input clamp current
IIK
–50
mA
Output clamp current
IOK
–50
mA
VO < 0
Continuous output current
IO
±50
mA
VO = 0 to VDDQ
2
VI < 0
HD74SSTL16857
Item
Symbol
Ratings
Unit
VCC, VDDQ or GND current / pin
ICC, IDDQ or
IGND
±100
mA
Maximum power dissipation
at Ta = 55°C (in still air)
PT
115
°C / W
Storage temperature
Tstg
–65 to +150
°C
Notes:
Conditions
TSSOP
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device at these or any
other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
1.The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2.This current will flow only when the output is in the high state and VO > VDDQ.
Recommended Operating Conditions
Item
Symbol
Min
Typ
Max
Unit Conditions
Supply voltage
VCC
VDDQ
—
3.6
V
Output supply voltage
VDDQ
2.3
—
2.7
V
Reference voltage
VREF
1.15
1.25
1.35
V
VREF = 0.5 ×
VDDQ
Termination voltage
VTT
VREF–40 mV VREF
VREF+40 mV V
Input voltage
VI
0
—
VCC
V
AC high level input voltage
VIH
VREF+350
mV
—
—
V
CLK, CLK, D
AC low level input voltage
V IL
—
—
VREF–350
mV
V
CLK, CLK, D
DC high level input voltage
VIH
VREF+180
mV
—
—
V
CLK, CLK, D
DC low level input voltage
VIL
—
—
VREF–180
mV
V
CLK, CLK, D
High level input voltage
VIH
1.7
—
VDDQ+0.3
V
RESET
Low level input voltage
VIL
–0.3
—
0.7
V
RESET
High level output current
IOH
—
—
–20
mA
Low level output current
IOL
—
—
20
mA
Operating temperature
Ta
0
—
70
°C
3
HD74SSTL16857
Logic Diagram
*1
RESET
34
CLK
CLK
38
39
D1
48
1D
C1
R
To thirteen other channels
Note:
4
1.RESET input gate is conected to VDDQ.
1
Q1
HD74SSTL16857
Electrical Characteristics
Item
Input diode voltage
Symbol VCC (V)
VIK
2.3
Output voltage
VOH
VOL
Differential input voltage
Input current
RESET
—
–1.2
V
IIN = –18 mA
—
—
V
IOH = –100 µA
2.3
1.95
—
—
IOH = –8 mA
2.3
1.70
—
—
IOH = –16 mA
2.3 to 2.7 —
—
0.2
IOL = 100 µA
2.3
—
—
0.35
IOL = 8 mA
—
—
0.55
—
0.97
—
1.53
V
VPP
—
360
—
—
m Minimum peak to peak
V input
µ VIN = 2.7 V or 0
A V = 2.7 V or 0
IN
IIN
ICC
Notes:
Common mode range
2.7
—
—
±5
—
—
±5
2.7
—
—
±5
VIN = 1.7 V or 0.8 V
VREF = 1.15 V or 1.35 V
2.7
—
—
±5
VIN = 2.7 V or 0
VREF = 1.15 V or 1.35 V
3.6
—
—
±5
VIN = 1.7 V or 0.8 V
VREF = 1.15 V or 1.35 V
3.6
—
—
±5
VIN = 2.7 V or 0
VREF = 1.15 V or 1.35 V
VREF = 1.15 V or 1.35 V
2.7
—
—
±5
3.6
—
—
±5
2.7
—
—
25
m VIN = 1.7 V or 0.8 V, IO = 0
A
2.7
—
—
25
VIN = 2.7 V or 0, IO = 0
3.6
—
—
50
VIN = 1.7 V or 0.8 V, IO = 0
VIN = 2.7 V or 0, IO = 0
—
—
50
—
3.5
—
Data inputs
2.5 *1
—
3.7
—
Control
inputs
3.3 *2
—
3.5
—
Data inputs
3.3 *2
—
3.7
—
CIN
IOL = 16 mA
3.6
*1
Control
inputs
U
nit Test Conditions
2.3 to 2.7 VCC–
0.2
3.6
capacitance
Max
2.3
VREF
Input
—
Typ
VCMR
CLK, CLK,
Data inputs,
Quiescent
supply current
Min
2.5
pF VIN = 1.7 V or 0.8 V
1.All typical values are at VCC = 2.5 V, Ta = 25°C.
2.All typical values are at VCC = 3.3 V, Ta = 25°C.
5
HD74SSTL16857
Switching Characteristics
Item
Symbol
Clock frequency
fclock
Setup time
tsu
VCC = 2.5 ± 0.2 V VCC = 3.3 ± 0.3 V Unit Test Condition
Min
Max
Min
Max
200
—
200
—
MHz
ns
1.25
—
1.25
—
1.25
—
1.25
—
Data before CLK↑, CLK↓
RESET high before CLK↑,
CLK↓
Hold time
th
0.75
—
0.75
—
ns
Data after CLK↑, CLK↓
Pulse width
tw
2.0
—
2.0
—
ns
CLK, CLK “H” or “L”
(CL = 10 pF, Class I, VREF = VTT = VDDQ × 0.5)
Item
Symbol
Maximum clock frequency fmax
Propagation delay time
VCC = 3.3 ± 0.3
V
Unit
VCC = 2.5 ± 0.2 V
Min
Typ
Max
Min
Max
From
To
(Input)
(Output)
200
—
—
200
—
MHz
tPLH,
tPHL
1.5
2.5
3.5
1.5
3.0
ns
CLK, CLK
Q
tPHL
—
2.6
5.0
1.0
5.0
ns
RESET
Q
(CL = 30 pF, Class II, VREF = VTT = VDDQ × 0.5)
Item
Symbol
VCC = 3.3 ± 0.3
V
Unit
From
(Input)
Min
Typ
Max
Min
Max
To
(Output)
200
—
—
200
—
MHz
tPLH,
tPHL
1.5
2.5
3.5
1.5
3.0
ns
CLK, CLK
Q
tPHL
—
2.6
5.0
1.0
5.0
ns
RESET
Q
Maximum clock frequency fmax
Propagation delay time
VCC = 2.5 ± 0.2 V
(CL = 50 pF, RL = 500 W, VREF = VTT = VDDQ × 0.5)
Item
Symbol
Maximum clock frequency fmax
Propagation delay time
tPLH,
tPHL
tPHL
6
VCC = 2.5 ± 0.2 V
VCC = 3.3 ± 0.3
V
Unit
From
(Input)
To
(Output)
Min
Typ
Max
Min
Max
150
—
—
150
—
MHz
1.5
3.8
5.0
1.5
4.5
ns
CLK, CLK
Q
—
4.0
7.0
1.0
6.5
ns
RESET
Q
HD74SSTL16857
Test Circuit
• Class I, II
VTT
Test point
25 Ω
*2
25 Ω = SSTL_2 Class II
50 Ω = SSTL_2 Class I
*1
C L = 10 pF or 30 pF
• C L= 50 pF, R L = 500 Ω
Test point
*1
C L = 50 pF
Notes:
R L = 500 Ω
1.CL includes probe and jig capacitance.
2.VTT = VREF = VDDQ × 0.5
7
HD74SSTL16857
Waveforms – 1
VIH
CLK input
VREF
VREF
t PLH
VIL
t PHL
VOH
Output
VREF
VREF
VOL
0.5 × VDDQ
VREF
VIH
VREF +350 mV (AC voltage levels)
VIL
VREF –350 mV (AC voltage levels)
Waveforms – 2
VIH
Timing input
VREF
tsu
VIL
th
VIH
Data input
VREF
VREF
VIL
tw
VIH
Input
VREF
VREF
VIL
VREF
Notes:
8
VREF +350 mV (AC voltage levels)
VIL
VREF –350 mV (AC voltage levels)
1.Input waveform : PRR ≤ 10 MHz, Zo = 50 W, tr ≤ 1.25 ns/V, tf ≤ 1.25 ns/V.
2.The output are measured one at a time with one transition per measurement.
3.tPLH and tPHL are the same as propagation delay time.
Package Dimensions
Unit : mm
0.5 × VDDQ
VIH
HD74SSTL16857
+0.3
12.50 –0.1
25
6.10 +0.3
–0.1
48
0.20 +0.1
–0.05
0.50
24
0.15 ± 0.05
1
0.08 M
0.05 Min
0.10
1.20 max
0.65 Max
8.10 ± 0.3
10° Max
0.50 ± 0.1
Hitachi code
EIAJ code
JEDEC code
TTP-48DC
—
—
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi
bears no responsibility for problems that may arise with third party’s rights, including intellectual property
rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality
and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily
injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety
equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions
and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due
to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.
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HD74SSTL16857
Hitachi, Ltd.
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Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
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For further information write to:
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Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
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