200 MBd Low-Cost SBCON Multimode Fiber Transceiver Technical Data HFBR-5320 Features Description • Compliant with IBM♦ Enterprise Systems Connection (ESCON)♦ Architecture • Compliant to SBCON Draft Specification (dpANS X3.xxx-199x rev 2.2) • Low Radiated Emissions and High Immunity to Conducted Noise • Multi-Sourced 4 x 7 Package Style with ESCON♦ Duplex Connector Interface • Wave Solder and Aqueous Wash Process Compatible • Manufactured in an ISO 9001 Certified Facility • 1300 nm LED-Based Transceiver The HFBR-5320 SBCON transceiver from Agilent provides system designers with a product to implement a range of solutions compliant with the IBM♦ Enterprise System Connection (ESCON)♦ architecture. Applications • Interconnection with IBM♦ Compatible Processors, Directors, and Channel Attachment Units – Disk and Tape Drives – Communication – Controllers • Data Communication Equipment – Local Area Networks – Point-to-Point – Communication Note: IBM, Enterprise System Connection Architecture, ESCON, are registered trademarks of International Business Machines Corporation. Transmitter Section The transmitter section of the HFBR-5320 utilizes 1300 nm Surface Emitting InGaAsP LED. The LED is packaged in an optical sub-assembly within the transmitter section. The LED is driven by a custom silicon IC which converts differential PECL logic signals [ECL referenced (shifted) to a +5 Volt supply] into an analog LED drive current. Receiver Section The receiver section of the HFBR-5320 utilizes an InGaAs PIN photodiode coupled to a custom silicon transimpedance preamplifier IC. This PIN/ preamplifier combination is coupled to a custom quantizer IC which provides the final pulse shaping for the logic Data Output and Status Flag function. The Data and Status Flag Outputs are differential PECL compatible [ECL referenced (shifted) to a +5 Volt power supply] logic outputs. Package The overall package concept for the Agilent transceiver consists of the following basic elements: two optical sub-assemblies, an electrical sub-assembly and the housing with an integral duplex SBCON connector receptacle. This illustrated in Figure 1. The package outline and pin-out are shown in Figures 2 and 3. The package includes internal shields for the electrical and optical sub-assemblies to ensure low EMI emissions and high immunity to EMI fields. 2 The optical sub-assemblies utilize a high-volume assembly process together with low-cost lens technical understanding associated with this transceiver. You can contact them through DUPLEX RECEPTACLE ELECTRICAL SUBASSEMBLY DIFFERENTIAL DATA OUT DIFFERENTIAL SIGNAL DETECT OUT PIN PHOTODIODE QUANTIZER IC PREAMP IC DIFFERENTIAL DATA IN OPTICAL SUBASSEMBLIES LED DRIVER IC Figure 1. Block Diagram. TOP VIEW elements which result in a costeffective building block. your local Agilent sales representative. The electrical subassembly consists of a high-volume multilayer printed circuit board on which the IC circuits and various surface-mount passive circuit elements are attached. Agilent LED technology has produced 1300 nm LED devices with lower aging characteristics than normally associated with these technologies in the industry. The industry convention is 1.5 dB aging for 1300 nm LEDs. The Agilent LED will normally experience less than half this amount of aging over normal, commercial equipment mission-life periods. Contact your local Agilent sales representatives for additional details. The outer housing, including the SBCON-compliant duplex connector receptacle, is molded of filled, non-conductive UL 94V0 flame retardant Ultem♦ plastic (U.L. File E121562) to provide mechanical strength and electrical isolation. The transceiver is attached to a printed circuit board with 28 signal pins (4 rows of 7 pins) and with the four slots on the flanges which are located on the package sides. These four slots on the flanges provide the primary mechanical strength to withstand the loads imposed by the duplex connectored fiber cables. Applications Information The Applications Engineering group in the Agilent Optical Communications Division is available to assist you with the Recommended Handling Precautions It is advised that normal, antistatic precautions be taken in the handling and assembly of these transceivers to prevent damage which may be induced by electrostatic discharge (ESD). The HFBR-5320 transceiver meets Mil-Std-883C Method 3015.4 Class 2. Care should be used to avoid shorting the receiver Data or Status Flag Outputs directly to ground without proper current limiting impedance. Solder and Wash Process Compatibility The transceiver is delivered with a protective process plug inserted into the duplex SBCON connector receptacle. This process plug protects the optical subassemblies during wave solder and aqueous wash processing and acts as a dust cover during shipping. These transceivers are compatible with either industry standard wave or hand soldering processes. The process plug part number is HFBR-5002. Shipping Container The transceiver is packaged in a shipping container designed to protect it from mechanical and ESD damage during shipment or storage. Board Layout Decoupling Circuit and Ground Planes It is important to take care in the layout of your circuit board to achieve optimum performance from the transceiver. Figure 3 provides a good example of a schematic for a power supply decoupling circuit that works well with this part. It is further recommended that a contiguous ground plane be provided in the circuit board directly under the transceiver to provide a low inductive ground for signal return current. This recommendation is in keeping with good highfrequency board layout practices. Note: Ultem is a registered trademark of General Electric Corporation. 3 Regulatory Compliance This transceiver product is intended to enable commercial system designers to develop equipment that complies with the various international regulations governing certification of Information Technology Equipment. See the Regulatory Compliance Table for details. Additional information is benches, and floor mats in ESD controlled areas. the IBM♦ ESCON♦ / SBCON architecture. The second case to consider is static discharges to the exterior of the equipment chassis containing the transceiver parts. To the extent that the SBCONcompatible duplex connector receptacle is exposed to the outside of the equipment chassis, Immunity Equipment utilizing this transceiver will be subject to radiofrequency electromagnetic fields in some environments. This transceiver has a high immunity to such fields. Regulatory Compliance Table Feature Electrostatic Discharge (ESD) to the Electrical Pins Electrostatic Discharge (ESD) to the Duplex SBCON Receptacle Test Method MIL-STD-883C Method 3015.4 Variation of IEC 801-2 Electromagnetic Interference (EMI) FCC Class B CENELEC EN55022 Class B (CISPR 22B) VCCI Class 2 Variation of IEC 801-3 Immunity available from your local Agilent sales representative. Electrostatic Discharge (ESD) There are two design cases in which immunity to ESD damage is important. The first case is during handling of the transceiver prior to mounting it on the circuit board. It is important to use normal ESD handling precautions for ESD sensitive devices. These precautions include using grounded wrist straps, work Performance Meets Class 2 (2000 to 3999 Volts) Withstands up to 2200 V applied between electrical pins. Typically withstand at least 25kV without damage when the Duplex SBCON Connector Receptacle is contacted by a Human Body Model probe. Typically provide a 20 dB margin to the noted standard limits when tested at a certified test range with the transceiver mounted to a circuit card without a chassis enclosure. Typically show no measurable effect from a 10V/m field swept from 10 to 450 MHz applied to the transceiver when mounted to a circuit card without a chassis enclosure. it may be subject to whatever ESD system level test criteria that the equipment is intended to meet. Electromagnetic Interference (EMI) Ordering Information The HFBR-5320 1300 nm SBCONcompatible transceiver is available for production orders through the Agilent Component Field Sales Offices and Authorized Distributors worldwide. Most equipment designs utilizing this high-speed transceiver from Agilent will be required to meet the requirements of FCC in the United States, CENELEC EN55022 (CISPR 22) in Europe and VCCI in Japan. This device is suitable for a variety of applications utilizing All HFBR-5320 LED transmitters are classified as IEC-825-1 Accessible Emission Limit (AEL) Class 1 based upon the current proposed draft scheduled to go into effect on January 1, 1997. AEL Class 1 LED devices are considered eye safe. 4 Absolute Maximum Ratings Parameter Storage Temperature Lead Soldering Temperature Lead Soldering Time Supply Voltage Data Input Voltage Differential Input Voltage Output Current Symbol TS TSOLD tSOLD VCC VI VD IO Min. –40 Typ. –0.5 –0.5 Max. 100 260 10 7.0 VCC 1.4 50 Unit °C °C sec. V V V mA Reference Max. 70 5.25 –1.475 –0.810 Unit °C V V V Ω Reference Reference Note 3 Reference Note 4 Note 5 Note 6 Note 6 Note 7 Note 7 Note 6 Note 6 Note 7 Note 7 Note 1 Recommended Operating Conditions Parameter Ambient Operating Temperature Supply Voltage Data Input Voltage - Low Data Input Voltage - High Data and Status Flag Output Load Symbol TA VCC VIL - V CC VIH - V CC RL Min. 0 4.75 –1.890 –1.165 Typ. 50 Note 2 Transmitter Electrical Characteristics (TA = 0°C to 70°C, V CC = 4.75 V to 5.25 V) Parameter Supply Current Power Dissipation Data Input Current - Low Data Input Current - High Threshold Voltage Symbol ICC PDISS IIL IIH VBB - V CC Min. Typ. 145 0.76 Max. 185 0.97 –1.42 –1.3 350 –1.24 Unit mA W µA µA V Min. Typ. 100 0.3 Max. 125 0.5 –1.620 –0.810 1.3 1.3 –1.620 –0.810 2.2 2.2 Unit mA W V V ns ns V V ns ns –350 Note 21 Receiver Electrical Characteristics (TA = 0°C to 70°C, V CC = 4.75 V to 5.25 V) Parameter Supply Current Power Dissipation Data Output Voltage - Low Data Output Voltage - High Data Output Rise Time Data Output Fall Time Status Flag Output Voltage - Low Status Flag Output Voltage - High Status Flag Output Rise Time Status Flag Output Fall Time Symbol ICC PDISS VOL - VCC VOH - V CC tr tf VOL - VCC VOH - V CC tr tf –1.890 –1.060 0.35 0.35 –1.890 –1.060 0.35 0.35 5 Transmitter Optical Characteristics (TA = 0°C to 70°C, V CC = 4.75 V to 5.25 V) Parameter Output Optical Power 62.5 / 125 µm, NA = 0.275 Fiber Optical Extinction Ratio Center Wavelength Spectral Width - FWHM Optical Rise Time Optical Fall Time Output Optical Systematic Jitter Symbol PO BOL PO EOL λC ∆λ Tr tf tSJ Min. –20.5 –21.5 8 1280 Max. –15.0 1380 175 1.7 1.7 0.8 Unit dBm avg. dB nm nm ns ns ns p-p Reference Note 9 Note 22 Note 11 Note 10, 12 Note 10, 12 Note 13 Receiver Optical and Electrical Characteristics (TA = 0°C to 70°C, V CC = 4.75 V to 5.25 V) Parameter Input Optical Power Minimum at Window Edge Input Optical Power Minimum at Eye Center Input Optical Power Maximum Operating Wavelength Systematic Jitter Eyewidth Status Flag - Asserted Status Flag - Deasserted Status Flag - Hysteresis Status Flag Assert Time (off-to-on) Signal Detect Deassert Time (off-to-on) Symbol PIN Min. (W) PIN Min. (C) PIN Max. λ SJ tew PA PD PA - PD tA tD Min. –14.0 1280 1.4 –44.5 –45 0.5 3 3 Max. PIN Min. (C) + 1.0 dB –29.0 Unit dBm avg. Reference Note 14 dBm avg. Note 15 Note 14 500 dBm avg. nm ns p-p ns dBm avg. dBm avg. dB µs 500 µs Note 20 1380 1.0 –35.5 –36 Note 16 Note 8 Note 17 Note 17 Note 18 Note 19 6 Notes: 1. This is the maximum voltage that can be applied across the Differential Transmitter Data Inputs to prevent damage to the input ESD protection circuit. 2. The outputs are terminated with 50 Ω connected to VCC –2 V. 3. The power supply current needed to operate the transmitter is provided to differential ECL circuitry. This circuitry maintains a nearly constant current flow from the power supply. Constant current operation helps to prevent unwanted electrical noise from being generated and conducted or emitted to neighboring circuitry. 4. This value is measured with the outputs terminated into 50 Ω connected to VCC –2 V and an Input Optical Power Level of – 14.5 dBm average. 5. The power dissipation value is the power dissipated in the receiver itself. Power dissipation is calculated as the sum of the products of supply voltage and currents, minus the sum of the products of the output voltages and currents. 6. This value is measured with respect to VCC with the output terminated into 50 Ω connected to VCC –2 V. 7. The output rise time and fall times are measured between 20% and 80% levels with the output connected to VCC – 2 V through 50 Ω. 8. Eye-width specified defines the minimum clock time-position range, centered around the center of the 5 ns baud interval, at which the BER must be 10 –12 or better. Test data pattern is PRBS 27 – 1. The maximum change in input optical power to open the eye to 1.4 nsec from a closed eye is 1.0 dB. 9. These optical power values are measured with the following conditions: • The Beginning of Life (BOL) to the End of Life (EOL) optical power degradation is assumed to be 1.5 dB per the industry convention for long wavelength LEDs. The actual degradation observed in normal commercial environments will be <1.0 dB with Agilent’s 1300 nm LED products. • Over the specified operating voltage and temperature ranges. • Input Signal: 27 –1 data pattern PseudoRandom Bit-Stream, 200 Mbit/sec NRZ code. 10. Input conditions: 100 MHz, square wave signal, input voltages are in the range specified for VIL and VIH. 11. From an assumed Gaussian-shaped wavelength distribution, the relationship between FWHM and RMS values for Spectral Width is 2.35 x RMS = FWHM. 12. Measured with electrical input signal rise and fall time of 0.35 to 1.3 ns (20-80%) at the transmitter input pins. Optical output rise and fall times are measured between 10% and 90% levels. 13. Transmitter Systematic Jitter is equal to the sum of Duty Cycle Distortion (DCD) and Data Dependent Jitter (DDJ). DCD is equivalent to PulseWidth Distortion (PWD). Systematic Jitter is measured at the 50% signal level with 200 MBd, PRBS 2 7 – 1 electrical input data pattern. 14. This specification is intended to indicate the performance of the receiver section of the transceiver when Input Optical Power signal characteristics are present per the following conditions. The Input Optical Power dynamic range from the minimum level (with a window time-width) to the maximum level is the range over which the receiver is guaranteed to provide output data with a Bit Error Ratio (BER) better than or equal to 10 –15. • At the Beginning of Life (BOL). • Over the specified operating temperature and voltage ranges. • Receiver data window time-width is 1.4 ns or greater and centered at mid-symbol. • Input signal is 200 MBd, PseudoRandom-Bit-Stream 27 – 1 data pattern. • Transmitter cross-talk effects have been included in Receiver sensitivity. Transmitter should be running at 50% duty cycle (nominal) between 8 - 200 Mbps, while Receiver sensitivity is measured. 15. All conditions of note 14 apply except that the measurement is made at the center of the symbol with no window time-width. 16. The receiver systematic jitter specification applies to optical powers between – 14.5 dBm avg. to – 27.0 dBm avg. at the receiver. Receiver Systematic Jitter is equal to the sum of Duty Cycle Distortion (DCD) and Data Dependent Jitter 17. 18. 19. 20. 21. 22. (DDJ). DCD is equivalent to PulseWidth Distortion (PWD). Systematic Jitter is measured at the 50% signal level with 200 MBd, PRBS 27 – 1 electrical output data pattern. Status Flag switching thresholds: Direction of decreasing optical power If Power >–36.0 dBm avg., then SF = 1 (high) If Power <–45.0 dBm avg., then SF = 0 (low) Direction of increasing optical power: If Power <–45.5 dBm avg., then SF = 0 (low) If Power >–35.5 dBm avg., then SF = 1 (high) Status Flag Hysteresis is the difference in low-to-high and high-tolow switching thresholds. Thresholds must lie within optical power limits specified. The Hysteresis is desired to avoid Status Flag chatter when the optical input is near the threshold. The Status Flag output shall be asserted with 500 µs after a step increase of the Input Optical Power. The step will be from a low Input Optical Power <– 45.5 dBm avg., to >–35.5 dBm avg. Status Flag output shall be deasserted within 500 µs after a step decrease in the Input Optical Power. The Step will be from a high Input Optical Power >– 36.0 dBm avg. to <–45.0 dBm avg. This value is measured with an output load of RL = 10 kΩ. The Extinction Ratio is a measure of the modulation depth of the optical signal. The data “0” output optical power is compared to the data “1” peak output optical and expressed in decibels. With the transmitter driven by a HALT Line State (12.5 Mhz square-wave) signal, the average optical power is measured. The data “1” peak power is then calculated by adding 3 dB to the measured average optical power. The data “0” output optical power is found by measuring the optical power when the transmitter is driven by a logic “0” input. The Extinction Ratio is the ratio of the optical power at the “0” level compared to the optical power at the “1” level expressed in decibels. 7 17.78 8.89 3.8 ± 0.1 (2X) ∅ 2.50 45° PROCESS PLUG 11.57 MAX. 45.75 20.15 4.05 ± 0.1 0.40 CARD MOUNT SURFACE (4X) 19.00 (2X) 15.88 76.26 MAX. 17.78 7 (28X) ∅ 0.48 1 GND GND GND 14 27 VCC VCC3 GND NC GND GND VCC GND GND GND GND VCC1 GND GND GND GND DATA GND GND DATA SF VBB DATA 20 21 DATA SF A HFBR-5XXX DATE CODE (YYWW) SINGAPORE A 34 (7X) 2.54 40 (2X) 3.81 (2X) 10.16 TOP VIEW 3.60 ± 0.25 35.20 BOTTOM VIEW Figure 2. Package Outline Drawing. NOTES: 1. ALL DIMENSIONS ARE MILLIMETERS. 2. ALL DIMENSIONS ARE NOMINAL UNLESS OTHERWISE SPECIFIED. 3. THE LEADS ARE TIN-LEAD (90/10) PLATED PHOSPHOR BRONZE. 4. LABEL INFORMATION REFER TO –05. +5 V 0.1 µF 1 µH 0.1 µF 82 Ω 0.1 µF 82 Ω RD RD 1 µH +5 V 10 µF 0.1 µF 130 Ω 130 Ω +5 V +5 V 20 1 0.1 µF 82 Ω 82 Ω VBB DATA 21 DATA SF GND DATA DATA SF GND GND GND GND GND GND VCC GND GND VCC GND GND GND VCC NC GND GND GND VCC GND 40 0.1 µF 82 Ω 82 Ω TD 4 X 7 PINS REQUIRED TD 130 Ω 130 Ω 7 SF SF 130 Ω 14 27 130 Ω 34 NC = NO INTERNAL CONNECTION HFBR-5320 (TOP VIEW) Figure 3. Notes: 1. Resistance is in Ohms. Capacitance is in microfarads. Inductance is in microhenries. 2. Terminal transmitter input Data and Data-bar at the transmitter input pins. Terminate the receiver Output Data, Data-bar, Status Flag, and Status Flag-bar at the follow-on device input pins. For lower power dissipation in the Status Flag termination circuitry with small compromise to the signal quality, each Status Flag output can be loaded with 510 Ohms to ground instead of the two resistor, split -load PECL termination shown in the Figure 3 schematic. 3. Make differential signal paths short and same length with equal termination impedance. 4. Signal traces should be 50 Ohms microstrip or stripline transmission lines. Use multilayer, ground-plane printed circuit board for best high-frequency performance. 5. Use high-frequency, monolithic ceramic bypass capacitors and low series dc resistance inductors. Recommend use of surfacemount coil inductors and capacitors. In low noise power supply systems, ferrite bead inductors can be substituted for coil inductors. Locate power supply filter components close to their respective power supply pins. 6. Device ground pin should be directly and individually connected to ground. 7. Caution: Do not directly connect the fiber-optic module PECL outputs (Data, Data-bar, Status flag, Status Flag-bar, V BB) to ground without proper current limiting impedance. www.semiconductor.agilent.com Data subject to change. Copyright © 1999 Agilent Technologies, Inc. 5965-5256E (11/99)