ETC HM66AEB36102BP-50

To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
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these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
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HM66AEB36102/HM66AEB18202
HM66AEB9402
36-Mbit DDR II SRAM
2-word Burst
ADE-203-1365 (Z)
Preliminary
Rev. 0.0
Dec. 18, 2002
Description
The HM66AEB36102 is a 1,048,576-word by 36-bit, the HM66AEB18202 is a 2,097,152-word by 18-bit,
and the HM66AEB9402 is a 4,194,304-word by 9-bit synchronous double data rate static RAM fabricated
with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique
synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair
(K and K) and are latched on the positive edge of K and K. These products are suitable for applications
which require synchronous operation, high speed, low voltage, high density and wide bit configuration.
These products are packaged in 165-pin plastic FBGA package.
Preliminary: The specifications of this device are subject to change without notice. Please contact
your nearest Hitachi’s Sales Dept. regarding specifications.
HM66AEB36102/18202/9402
Features
• 1.8 V ± 0.1 V power supply for core (VDD)
• 1.4 V to VDD power supply for I/O (VDDQ)
• DLL circuitry for wide output data valid window and future frequency scaling
• Pipelined double data rate operation
• Common data input/output bus
• Two-tick burst for low DDR transaction size
• Two input clocks (K and K) for precise DDR timing at clock rising edges only
• Two output clocks (C and C) for precise flight time and clock skew matching-clock and data delivered
together to receiving device
• Internally self-timed write control
• Clock-stop capability with µs restart
• User programmable impedance output
• Fast clock cycle time: 3.0 ns (333 MHz)/3.3 ns (300 MHz)/4.0 ns (250 MHz)/
5.0 ns (200 MHz)/6.0 ns (167 MHz)
• Simple control logic for easy depth expansion
• JTAG boundary scan
Ordering Information
Type No.
Organization
Cycle time
Clock frequency
Package
HM66AEB36102BP-30
HM66AEB36102BP-33
HM66AEB36102BP-40
HM66AEB36102BP-50
HM66AEB36102BP-60
1-M word
× 36-bit
3.0 ns
3.3 ns
4.0 ns
5.0 ns
6.0 ns
333 MHz
300 MHz
250 MHz
200 MHz
167 MHz
Plastic FBGA 165-pin
(BP-165A)
HM66AEB18202BP-30
HM66AEB18202BP-33
HM66AEB18202BP-40
HM66AEB18202BP-50
HM66AEB18202BP-60
2-M word
× 18-bit
3.0 ns
3.3 ns
4.0 ns
5.0 ns
6.0 ns
333 MHz
300 MHz
250 MHz
200 MHz
167 MHz
HM66AEB9402BP-30
HM66AEB9402BP-33
HM66AEB9402BP-40
HM66AEB9402BP-50
HM66AEB9402BP-60
4-M word
× 9-bit
3.0 ns
3.3 ns
4.0 ns
5.0 ns
6.0 ns
333 MHz
300 MHz
250 MHz
200 MHz
167 MHz
Rev.0.0, Dec. 2002, page 2 of 30
HM66AEB36102/18202/9402
Pin Arrangement (HM66AEB36102) 165PIN-BGA
1
2
3
4
5
6
7
8
9
10
11
A
CQ
VSS
SA
R/W
BW2
K
BW1
LD
SA
NC
CQ
B
NC
DQ27
DQ18
SA
BW3
K
BW0
SA
NC
NC
DQ8
C
NC
NC
DQ28
VSS
SA
SA0
SA
VSS
NC
DQ17
DQ7
D
NC
DQ29
DQ19
VSS
VSS
VSS
VSS
VSS
NC
NC
DQ16
E
NC
NC
DQ20
VDDQ
VSS
VSS
VSS
VDDQ
NC
DQ15
DQ6
F
NC
DQ30
DQ21
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ5
G
NC
DQ31
DQ22
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ14
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
DQ32
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ13
DQ4
K
NC
NC
DQ23
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ12
DQ3
L
NC
DQ33
DQ24
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
M
NC
NC
DQ34
VSS
VSS
VSS
VSS
VSS
NC
DQ11
DQ1
N
NC
DQ35
DQ25
VSS
SA
SA
SA
VSS
NC
NC
DQ10
P
NC
NC
DQ26
SA
SA
C
SA
SA
NC
DQ9
DQ0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
7
8
9
10
11
(Top view)
Pin Arrangement (HM66AEB18202) 165PIN-BGA
1
2
3
4
5
6
A
CQ
VSS
SA
R/W
BW1
K
NC
LD
SA
SA
CQ
B
NC
DQ9
NC
SA
NC
K
BW0
SA
NC
NC
DQ8
C
NC
NC
NC
VSS
SA
SA0
SA
VSS
NC
DQ7
NC
D
NC
NC
DQ10
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
DQ11
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ6
F
NC
DQ12
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ5
G
NC
NC
DQ13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ4
NC
K
NC
NC
DQ14
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ3
L
NC
DQ15
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
DQ1
NC
N
NC
NC
DQ16
VSS
SA
SA
SA
VSS
NC
NC
NC
P
NC
NC
DQ17
SA
SA
C
SA
SA
NC
NC
DQ0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
(Top view)
Rev.0.0, Dec. 2002, page 3 of 30
HM66AEB36102/18202/9402
Pin Arrangement (HM66AEB9402) 165PIN-BGA
1
2
3
4
5
6
A
CQ
B
NC
C
D
7
8
9
10
11
VSS
SA
R/W
NC
K
NC
LD
SA
SA
CQ
NC
NC
SA
NC
K
BW
SA
NC
NC
DQ3
NC
NC
NC
VSS
SA
SA
SA
VSS
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
DQ4
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
NC
DQ5
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ1
NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
DQ6
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ0
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
N
NC
NC
NC
VSS
SA
SA
SA
VSS
NC
NC
NC
P
NC
NC
DQ7
SA
SA
C
SA
SA
NC
NC
DQ8
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
(Top view)
Note: Note that 6C is not SA0. The ×9 product does not permit random start address on the least
significant address bit. SA0 = 0 at the start of each address.
Rev.0.0, Dec. 2002, page 4 of 30
HM66AEB36102/18202/9402
Pin Descriptions
Name
I/O type Descriptions
SA0
SAn
Input
Synchronous address inputs: These inputs are registered and must meet the setup and
hold times around the rising edge of K. Ball 2A is reserved for the next higher-order
address input on future devices. All transactions operate on a burst-of-two words (one
clock period of bus activity). SA0 is used as the lowest address bit for burst READ and
burst WRITE operations permitting a random burst start address on ×18 and ×36
devices. These inputs are ignored when device is deselected.
LD
Input
Synchronous load: This input is brought low when a bus cycle sequence is to be
defined. This definition includes address and READ / WRITE direction. All transactions
operate on a burst-of-two data (one clock period of bus activity).
R/W
Input
Synchronous read / write input: When LD is low, this input designates the access type
(READ when R/W is high, WRITE when R/W is low) for the loaded address. R/W must
meet the setup and hold times around the rising edge of K.
BW
BWn
Input
Synchronous byte writes: When low, these inputs cause their respective byte to be
registered and written during WRITE cycles. These signals must meet setup and hold
times around the rising edges of K and K for each of the two rising edges comprising the
WRITE cycle. See Byte Write Truth Table for signal to data relationship.
K, K
Input
Input clock: This input clock pair registers address and control inputs on the rising edge
of K, and registers data on the rising edge of K and the rising edge of K. K is ideally 180
degrees out of phase with K. All synchronous inputs must meet setup and hold times
around the clock rising edges.
C, C
Input
Output clock: This clock pair provides a user-controlled means of tuning device output
data. The rising edge of C is used as the output timing reference for second output data.
The rising edge of C is used as the output reference for first output data. Ideally, C is
180 degrees out of phase with C. C and C may be tied high to force the use of K and K
as the output reference clocks instead of having to provide C and C clocks. If tied high,
C and C must remain high and not to be toggled during device operation.
DOFF
Input
DLL disable: When low, this input causes the DLL to be bypassed for stable, lowfrequency operation.
ZQ
Input
Output impedance matching input: This input is used to tune the device outputs to the
system data bus impedance. DQ and CQ output impedance are set to 0.2 × RQ, where
RQ is a resistor from this ball to ground. Alternately, this ball can be connected directly
to VDDQ, which enables the minimum impedance mode. This ball cannot be connected
directly to VSS or left unconnected.
TMS
TDI
Input
IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left not connected if the
JTAG function is not used in the circuit.
TCK
Input
IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to VSS if the JTAG
function is not used in the circuit.
Rev.0.0, Dec. 2002, page 5 of 30
HM66AEB36102/18202/9402
Name
I/O type Descriptions
DQ0 to
DQn
Input/
output
CQ, CQ
Output Synchronous echo clock outputs: The edges of these outputs are tightly matched to the
synchronous data outputs and can be used as a data valid indication. These signals run
freely and do not stop when DQ tri-states.
TDO
Output IEEE 1149.1 test output: 1.8 V I/O level.
VDD
Supply Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for
range.
VDDQ
Supply Power supply: Isolated output buffer supply. Nominally 1.5 V. 1.8 V is also permissible.
See DC Characteristics and Operating Conditions for range.
VSS
Supply Power supply: Ground
VREF

HSTL input reference voltage: Nominally VDDQ/2. Provides a reference voltage for the
input buffers.
NC

No connect: These signals are internally connected and appear in the JTAG scan chain
as the logic level applied to the ball sites. These signals may be connected to ground to
improve package heat dissipation.
Note:
Synchronous data I/Os: Input data must meet setup and hold times around the rising
edges of K and K. Output data is synchronized to the respective C and C data clocks, or
to the respective K and K if C and C are tied to high.
The ×9 device uses DQ0 to DQ8. Remaining signals are NC.
The ×18 device uses DQ0 to DQ17. Remaining signals are NC.
The ×36 device uses DQ0 to DQ35.
NC signals are read in the JTAG scan chain as the logic level applied to the ball site.
1. All power supply and ground balls must be connected for proper operation of the device.
Rev.0.0, Dec. 2002, page 6 of 30
HM66AEB36102/18202/9402
Block Diagram (HM66AEB36102)
SA0
SA
Burst
Logic
20
Address
Registry
& Logic
LD
R/W
SA0'
SA0'' Output SA0'''
Control
Logic
20
K
K
36
MUX
72
C
72
Output Buffer
Output Select
K
Memory
Array
Output Register
K
72
Sense Amps
Data
Registry
& Logic
WRITE Driver
LD
BW0
BW1
BW2
BW3
WRITE Register
R/W
2
CQ, CQ
36
DQ0-35
C, C
or
K, K
Block Diagram (HM66AEB18202)
SA0
SA
Burst
Logic
21
Address
Registry
& Logic
LD
R/W
SA0'
SA0'' Output SA0'''
Control
Logic
21
K
K
18
MUX
36
C
36
Output Buffer
Output Select
K
Memory
Array
Output Register
K
36
Sense Amps
Data
Registry
& Logic
WRITE Driver
LD
BW0
BW1
WRITE Register
R/W
2
CQ, CQ
18
DQ0-17
C, C
or
K, K
Rev.0.0, Dec. 2002, page 7 of 30
HM66AEB36102/18202/9402
Block Diagram (HM66AEB9402)
SA
21
Address
Registry 21
& Logic
LD
R/W
K
K
9
Rev.0.0, Dec. 2002, page 8 of 30
MUX
18
C
C, C
or
K, K
18
Output Buffer
Output Select
K
Memory
Array
Output Register
K
18
Sense Amps
Data
Registry
& Logic
WRITE Driver
LD
BW
WRITE Register
R/W
2
CQ, CQ
9
DQ0-8
HM66AEB36102/18202/9402
Burst Sequence
Linear Burst Sequence Table
(HM66AEB36102/18202)
SA0
SA0
External address
0
1
1st internal burst address
1
0
Truth Table
Operation
K
LD
R/W
W
DQ
WRITE cycle
L→H
L
L
Data in
Load address, input write data on
consecutive K and K rising edges
READ cycle
L→H
L
H
Load address, read data on
consecutive C and C rising edges
Input
data
DA(A1)
DA(A2)
Input
clock
K(t+1)↑
K(t+1)↑
Output
data
QA(A1)
QA(A2)
Output
clock
C(t+1)↑
C(t+2)↑
Data out
NOP (No operation)
L→H
H
×
High-Z
STANDBY (Clock stopped)
Stopped
×
×
Previous state
Notes: 1. H: high level, L: low level, ×: don’t care, ↑: rising edge.
2. Data inputs are registered at K and K rising edges. Data outputs are delivered at C and C rising
edges, except if C and C are high, then data outputs are delivered at K and K rising edges.
3. All control inputs in the truth table must meet setup/hold times around the rising edges (low to
high) of K and are registered at the rising edge of K.
4. This device contains circuitry that will ensure the outputs will be in high-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that (K) = /(K) = (C) = /(C) when clock is stopped. This is not essential, but
permits most rapid restart by overcoming transmission line charging symmetrically.
7. A1 refers to the address input during a WRITE or READ cycle. A2 refers to the next internal
burst address in accordance with the linear burst sequence.
Rev.0.0, Dec. 2002, page 9 of 30
HM66AEB36102/18202/9402
Byte Write Truth Table
(HM66AEB36102)
Operation
K
K
BW0
BW1
BW2
BW3
Write D0 to D35
L→H

0
0
0
0

L→H
0
0
0
0
L→H

0
1
1
1

L→H
0
1
1
1
Write D0 to D8
Write D9 to D17
Write D18 to D26
Write D27 to D35
Write nothing
L→H

1
0
1
1

L→H
1
0
1
1
L→H

1
1
0
1

L→H
1
1
0
1
L→H

1
1
1
0

L→H
1
1
1
0
L→H

1
1
1
1

L→H
1
1
1
1
Notes: 1. H: high level, L: low level, →: rising edge.
2. Assumes a WRITE cycle was initiated. BW0 to BW3 can be altered for any portion of the burst
WRITE operation provided that the setup and hold requirements are satisfied.
(HM66AEB18202)
Operation
K
K
BW0
BW1
Write D0 to D17
L→H

0
0

L→H
0
0
L→H

0
1

L→H
0
1
L→H

1
0

L→H
1
0
L→H

1
1

L→H
1
1
Write D0 to D8
Write D9 to D17
Write nothing
Notes: 1. H: high level, L: low level, →: rising edge.
2. Assumes a WRITE cycle was initiated. BW0 and BW1 can be altered for any portion of the burst
WRITE operation provided that the setup and hold requirements are satisfied.
Rev.0.0, Dec. 2002, page 10 of 30
HM66AEB36102/18202/9402
(HM66AEB9402)
Operation
K
K
BW
Write D0 to D8
L→H

0

L→H
0
L→H

1

L→H
1
Write nothing
Notes: 1. H: high level, L: low level, →: rising edge.
2. Assumes a WRITE cycle was initiated. BW can be altered for any portion of the burst WRITE
operation provided that the setup and hold requirements are satisfied.
Bus Cycle State Diagram
LD = L
LD = H,
Count = 2
LD = L,
Count = 2
WRITE DOUBLE
Count = Count + 2
R/W = L
LD = H
LOAD NEW
ADDRESS
Count = 0
NOP
R/W = H
LD = L,
Count = 2
READ DOUBLE
Count = Count + 2
Supply voltage provided
LD = H,
Count = 2
POWER UP
Notes: 1. SA0 is internally advanced in accordance with the burst order table. Bus cycle is terminated after
burst count = 2.
2. State machine control timing sequence is controlled by K.
Rev.0.0, Dec. 2002, page 11 of 30
HM66AEB36102/18202/9402
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Notes
Input voltage on any ball
VIN
−0.5 to VDD + 0.5
(2.9 V max.)
V
1, 4
Input/output voltage
VI/O
−0.5 to VDDQ + 0.5
(2.9 V max.)
V
1, 4
Core supply voltage
VDD
−0.5 to 2.9
V
1, 4
Output supply voltage
VDDQ
−0.5 to VDD
V
1, 4
Junction temperature
Tj
+125 (max)
°C
Storage temperature
TSTG
−55 to +125
°C
Notes: 1. All voltage is referenced to VSS.
2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional
operation should be restricted the Operation Conditions. Exposure to higher than recommended
voltages for extended periods of time could affect device reliability.
3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown
in the tables after thermal equilibrium has been established.
4. The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF then VIN.
Remember, according to the Absolute Maximum Ratings table, VDDQ is not to exceed 2.9V,
whatever the instantaneous value of VDDQ.
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Power supply voltage -- core
VDD
1.7
1.8
1.9
V
Power supply voltage -- I/O
VDDQ
1.4
1.5
VDD
V
Input reference voltage -- I/O
VREF
0.68
0.75
0.95
V
Input high voltage
VIH (DC)
VREF + 0.1

VDDQ + 0.3
V
2, 3
Input low voltage
VIL (DC)
−0.3

VREF − 0.1
V
2, 3
1
Notes: 1. Peak to peak AC component superimposed on VREF may not exceed 5% of VREF.
2. VREF = 0.75 V (typ).
3. Overshoot: VIH (AC) ≤ VDD + 0.7 V for t ≤ tKHKH/2
Undershoot: VIL (AC) ≥ −0.5 V for t ≤ tKHKH/2
Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms
During normal operation, VDDQ must not exceed VDD.
Control input signals may not have pulse widths less than tKHKL (min) or operate at cycle rates less
than tKHKH (min).
Rev.0.0, Dec. 2002, page 12 of 30
HM66AEB36102/18202/9402
DC Characteristics (Ta = 0 to +70°C, VDD = 1.8 V ± 0.1 V)
HM66AEB36102/HM66AEB18202
HM66AEB9402
-30
Parameter
Symbol Typ
Operating supply current
(READ / WRITE)
Standby supply current
(NOP)
Notes 1.
2.
3.
4.
5.
-33
-40
-50
-60
Max
Unit
(×9 / ×18)
IDD
TBD 525
475
400
330
280
mA
(×36)
IDD
TBD 710
640
545
445
380
mA
(×9 / ×18)
ISB1
TBD 255
235
200
170
150
mA
(×36)
ISB1
TBD 265
240
210
180
160
mA
Notes
All inputs (except ZQ, VREF) are held at either VIH or VIL.
IOUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min.
Typical values are measured at VDD = 1.8 V, VDDQ = 1.5 V, Ta = +25°C, and tKHKH = 6 ns.
Operating supply currents are measured at 100% bus utilization.
NOP currents are valid when entering NOP after all pending READ and WRITE cycles are
completed.
Parameter
Symbol Min
Input leakage current
Max
Unit Test conditions Notes
ILI
−2
2
µA
8
Output leakage current ILO
−2
2
µA
9
Output high voltage
VOH
(Low)
VDDQ − 0.2
VDDQ
V
|IOH| ≤ 0.1 mA
3, 4
VOH
VDDQ/2 − 0.08
VDDQ/2 + 0.08
V
Notes1
3, 4
VOL
(Low)
VSS
0.2
V
IOL ≤ 0.1 mA
3, 4
VOL
VDDQ/2 − 0.08
VDDQ/2 + 0.08
V
Notes2
3, 4
Output “High” current
IOH
(VDDQ/2)/(RQ/5 + 10%) (VDDQ/2)/(RQ/5 − 10%) mA
5, 7
Output “Low” current
IOL
(VDDQ/2)/(RQ/5 − 10%) (VDDQ/2)/(RQ/5 + 10%) mA
6, 7
Output low voltage
Rev.0.0, Dec. 2002, page 13 of 30
HM66AEB36102/18202/9402
Outputs are impedance-controlled. |IOH| = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.
Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.
AC load current is higher than the shown DC values. AC I/O curves are available upon request.
HSTL outputs meet JEDEC HSTL Class I and Class II standards.
Measured at VOH= VDDQ/2
Measured at VOL= VDDQ/2
Output buffer impedance can be programmed by terminating the ZQ ball to VSS through a
precision resistor (RQ). The value of RQ is five times the output impedance desired. The
allowable range of RQ to guarantee impedance matching with a tolerance of 10% is 250 Ω
typical. The total external capacitance of ZQ ball must be less than 7.5 pF.
8. 0 ≤ VIN ≤ VDDQ for all input balls (except VREF, ZQ, TCK, TMS, TDI ball)
9. 0 ≤ VOUT ≤ VDDQ (except TDO ball), output disabled.
10. VDDQ = 1.5 V ± 0.1 V
Notes: 1.
2.
3.
4.
5.
6.
7.
Capacitance (Ta = +25°C, f = 1.0 MHz, VDD = 1.8 V)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Input capacitance
CIN

4
5
pF
VIN = 0 V
Clock input capacitance
CCLK

5
6
pF
VCLK = 0 V
Input/output capacitance (DQ)
CI/O

6
7
pF
VI/O = 0 V
Notes: 1. These parameters are sampled and not 100% tested.
2. Parameters tested with RQ = 250 Ω and VDDQ = 1.5 V.
Rev.0.0, Dec. 2002, page 14 of 30
HM66AEB36102/18202/9402
AC Characteristics (Ta = 0 to +70°C, VDD = 1.8 V ± 0.1 V)
Test Conditions
Input waveform (Rise/fall time ≤ 0.3 ns)
1.25 V
0.75 V
Test points
0.75 V
0.25 V
Output waveform
VDDQ/2
Test points
VDDQ/2
Output load condition
0.75 V
VREF
16.7 Ω
50 Ω
Zo = 50 Ω
0.75 V
16.7 Ω
SRAM
DQ
16.7 Ω
50 Ω
Zo = 50 Ω
0.75 V
250 Ω
ZQ
0.75 V
Rev.0.0, Dec. 2002, page 15 of 30
HM66AEB36102/18202/9402
Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Input high voltage
VIH (AC)
VREF + 0.2


V
1, 2, 3
Input low voltage
VIL (AC)


VREF − 0.2
V
1, 2, 3
Notes: 1.
2.
3.
All voltages referenced to VSS (GND).
Overshoot: VIH (AC) ≤ VDD + 0.7 V for t ≤ tKHKH/2
Undershoot: VIL (AC) ≥ −0.5 V for t ≤ tKHKH/2
Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms
During normal operation, VDDQ must not exceed VDD. Control input signals may not have pulse
widths less than tKHKL (min) or operate at cycle rates less than tKHKH (min).
To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through the target AC level, VIL (AC) or
VIH (AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at least the target DC level, VIL (DC)
or VIH (DC).
Rev.0.0, Dec. 2002, page 16 of 30
HM66AEB36102/18202/9402
HM66AEB36102/HM66AEB18202
HM66AEB9402
-30
Parameter
Symbol Min
-33
-40
-50
-60
Max
Min
Max
Min
Max
Min
Max Min
Max
Unit Notes
Average clock tKHKH
cycle time
(K, K, C, C)
3.00
3.47
3.30
4.20
4.00
5.25
5.00
6.30 6.00
7.88
ns
Clock phase
jitter
(K, K, C, C)

0.20

0.20

0.20

0.20 
0.20
ns
Clock high time tKHKL
(K, K, C, C)
1.20

1.32

1.60

2.00

2.40

ns
Clock low time tKLKH
(K, K, C, C)
1.20

1.32

1.60

2.00

2.40

ns
Clock to clock tKH/KH
(K to K, C to C)
1.35

1.49

1.80

2.20

2.70

ns
Clock to clock t/KHKH
(K to K, C to C)
1.35

1.49

1.80

2.20

2.70

ns
Clock to data tKHCH
clock
(K to C, K to C)
0
1.30
0
1.45
0
1.80
0
2.30 0
2.80
ns
DLL lock time
(K, C)
tKC var
tKC lock 1,024 
1,024 
1,024 
1,024 
1,024 
K static to DLL tKC reset 30
reset

30

30

30

C, C high to
output valid
tCHQV

0.45

0.45

0.45

0.45 
C, C high to
output hold
tCHQX
−0.45 
−0.45 
−0.45 
−0.45 
C, C high to
echo clock
valid
tCHCQV




0.45
0.45
0.45
−0.45 
−0.45 
−0.45 
−0.45 
CQ, CQ high to tCQHQV
output valid




CQ, CQ high to tCQHQX
output hold
−0.25 
−0.27 
−0.30 
−0.35 
C high to
output high-Z
tCHQZ




C high to
output low-Z
tCHQX1
−0.45 
0.45
0.27
0.45
−0.45 
0.30
0.45
−0.45 
−0.50
0.45 
C, C high to
tCHCQX
echo clock hold
0.25
30
−0.50
0.35 
−0.40
0.45 
−0.45 
−0.50
3
Cycle 2

ns
0.50
ns

ns
0.50
ns

ns
0.40
ns
4

ns
4
0.50
ns
5

ns
5
Rev.0.0, Dec. 2002, page 17 of 30
HM66AEB36102/18202/9402
HM66AEB36102/HM66AEB18202
HM66AEB9402
-30
Parameter
Symbol Min
-33
-40
-50
-60
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit Notes
Address valid tAVKH
to K rising edge
0.40

0.40

0.50

0.60

0.70

ns
1
Control inputs tIVKH
valid to K rising
edge
0.40

0.40

0.50

0.60

0.70

ns
1
Data-in valid to tDVKH
K, K rising
edge
0.28

0.30

0.35

0.40

0.50

ns
1
K rising edge to tKHAX
address hold
0.40

0.40

0.50

0.60

0.70

ns
1
K rising edge to tKHIX
control inputs
hold
0.40

0.40

0.50

0.60

0.70

ns
1
tKHDX
K, K rising
edge to data-in
hold
0.28

0.30

0.35

0.40

0.50

ns
1
Notes: 1. This is a synchronous device. All addresses, data and control lines must meet the specified
setup and hold times for all latching clock edges.
2. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins
once VDD and input clock are stable.
It is recommended that the device is kept inactive during these cycles.
3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ±0.1 ns
variation from echo clock to data. The datasheet parameters reflect tester guardbands and test
setup variations.
5. Transitions are measured ±100 mV from steady-state voltage.
6. At any given voltage and temperature tCHQZ is less than tCHQX1 and tCHQZ less than tCHQV.
Remarks: 1. This parameter is sampled.
2. Test conditions as specified with the output loading as shown in AC Test Conditions unless
otherwise noted.
3. Control input signals may not be operated with pulse widths less than tKHKL (min).
4. If C, C are tied high, K, K become the references for C, C timing parameters.
5. VDDQ is +1.5 V DC.
Rev.0.0, Dec. 2002, page 18 of 30
HM66AEB36102/18202/9402
Timing Waveforms
Read and Write Timing
NOP
READ
READ NOP
(burst of 2) (burst of 2)
1
2
3
tKHKH
NOP
4
5
WRITE
WRITE
READ
(burst of 2) (burst of 2) (burst of 2)
6
7
8
A2
A3
A4
9
10
K
tKHKL tKLKH
tKH/KH
t/KHKH
K
LD
tKHIX
tIVKH
R/W
tAVKH tKHAX
A0
Address
A1
tKHDX
tDVKH
DQ
Qx2
Q01 Q02
tCHQX1
tKHCH
CQ
CQ
tKHCH
tCHQV
D21 D22 D31 D32
Q11 Q12
tCHQX
tCHQV
tKHDX
tDVKH
Q41
Q42
tCQHQX
tCHQZ
tCQHQV
tCHQX
tCHCQX
tCHCQV
tCHCQX
tCHCQV
C
C
tKHKL tKLKH tKHKH tKH/KH t/KHKH
Notes: 1. Q01 refers to output from address A0. Q02 refers to output from the next internal burst address
following A0, etc.
2. Outputs are disable (high-Z) one clock cycle after a NOP.
3. In this example, if address A4 = A3, then data Q41 = D31, Q42 = D32. Write data is forwarded
immediately as read results.
4. The second NOP cycle is not necessary for correct device operation; however, at high clock
frequencies it may be required to prevent bus contention.
Rev.0.0, Dec. 2002, page 19 of 30
HM66AEB36102/18202/9402
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering
with normal operation of the device, TCK must be tied to VSS to preclude mid level inputs.
TDI and TMS are designed so an undriven input will produce a response identical to the application of a
logic 1, and may be left unconnected. But they may also be tied to VDD through a 1k resistor.
TDO should be left unconnected.
Test Access Port (TAP) Pins
Symbol I/O
Pin assignments
Description
TCK
2R
Test clock input. All inputs are captured on the rising edge of
TCK and all outputs propagate from the falling edge of TCK.
TMS
10R
Test mode select. This is the command input for the TAP
controller state machine.
TDI
11R
Test data input. This is the input side of the serial registers
placed between TDI and TDO. The register placed between
TDI and TDO is determined by the state of the TAP controller
state machine and the instruction that is currently loaded in
the TAP instruction.
TDO
1R
Test data output. Output changes in response to the falling
edge of TCK. This is the output side of the serial registers
placed between TDI and TDO.
Note: The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP controller state is also reset on SRAM POWER-UP.
Rev.0.0, Dec. 2002, page 20 of 30
HM66AEB36102/18202/9402
TAP DC Operating Characteristics (Ta = 0 to +70°C, VDD = 1.8 V ± 0.1 V)
Parameter
Symbol
Min
Max
Unit
Input high voltage
VIH
1.3
VDD + 0.3
V
Input low voltage
VIL
−0.3
+0.5
V
Input leakage current
ILI
−5.0
+5.0
µA
0 V ≤ VIN ≤ VDD
Output leakage current
ILO
−5.0
+5.0
µA
0 V ≤ VIN ≤ VDD,
output disabled
Output low voltage
VOL1

0.2
V
IOLC = 100 µA
VOL2

0.4
V
IOLT = 2 mA
VOH1
1.6

V
|IOHC| = 100 µA
VOH2
1.4

V
|IOHT| = 2 mA
Output high voltage
Conditions
Notes: 1. All voltages referenced to VSS (GND).
2. Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ +1.7 V and VDDQ ≤ +1.4 V for t ≤ 200 ms
3. In “EXTEST” mode and “SAMPLE” mode, VDDQ is nominally 1.5 V.
Rev.0.0, Dec. 2002, page 21 of 30
HM66AEB36102/18202/9402
TAP AC Test Condition
• Temperature
0°C ≤ Ta ≤ +70°C
• Input timing measurement reference levels
0.9 V
• Input pulse levels
0 V to 1.8 V
• Input rise/fall time
≤ 1.0 ns
• Output timing measurement reference levels
0.9 V
• Test load termination supply voltage (VTT)
0.9 V
• Output load
See figures
Input waveform
1.8 V
0.9 V
Test points
0.9 V
0V
Output waveform
0.9 V
Test points
0.9 V
Output load
VTT = 0.9 V
50 Ω
Zo = 50 Ω
TDO
20 pF
External load at test
Rev.0.0, Dec. 2002, page 22 of 30
HM66AEB36102/18202/9402
TAP AC Operating Characteristics (Ta = 0 to +70°C, VDD = 1.8 V ± 0.1 V)
Parameter
Symbol
Min
Max
Unit
Test clock cycle time
tTHTH
100

ns
Test clock high pulse width
tTHTL
40

ns
Test clock low pulse width
tTLTH
40

ns
Test mode select setup
tMVTH
10

ns
Test mode select hold
tTHMX
10

ns
Capture setup
tCS
10

ns
1
Capture hold
tCH
10

ns
1
TDI valid to TCK high
tDVTH
10

ns
TCK high to TDI invalid
tTHDX
10

ns
TCK low to TDO unknown
tTLQX
0

ns
TCK low to TDO valid
tTLQV

20
ns
Note:
Note
1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture.
TAP Controller Timing Diagram
tTHTH
TCK
tMVTH
tTHTL
tTLTH
TMS
tTHMX
tDVTH
TDI
tTLQV
tTHDX
TDO
tCS
tTLQX
tCH
RAM
ADDRESS
Test Access Port Registers
Register name
Length
Symbol
Instruction register
3 bits
IR [2:0]
Bypass register
1 bit
BP
ID register
32 bits
ID [31:0]
Boundary scan register
109 bits
BS [109:1]
Rev.0.0, Dec. 2002, page 23 of 30
HM66AEB36102/18202/9402
TAP Controller Instruction Set
IR2
IR1
IR0
Instruction
Description
0
0
0
EXTEST
The EXTEST instruction allows circuitry external to the
component package to be tested. Boundary scan register cells
at output balls are used to apply test vectors, while those at
input balls capture test results. Typically, the first test vector to
be applied using the EXTEST instruction will be shifted into the
boundary scan register using the PRELOAD instruction. Thus,
during the Update-IR state of EXTEST, the output drive is
turned on and the PRELOAD data is driven onto the output
balls.
0
0
1
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into
the ID register when the controller is in capture-DR mode and
places the ID register between the TDI and TDO balls in shiftDR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in
the Test-Logic-Reset state.
0
1
0
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register,
all RAM outputs are forced to an inactive drive state (high-Z,
except CQ, CQ ball) and the boundary register is connected
between TDI and TDO when the TAP controller is moved to the
shift-DR state.
0
1
1
RESERVED
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
1
0
0
SAMPLE
(-PRELOAD)
When the SAMPLE instruction is loaded in the instruction
register, moving the TAP controller into the capture-DR state
loads the data in the RAMs input and I/O buffers into the
boundary scan register. Because the RAM clock(s) are
independent from the TAP clock (TCK) it is possible for the
TAP to attempt to capture the I/O ring contents while the input
buffers are in transition (i.e., in a metastable state). Although
allowing the TAP to SAMPLE metastable input will not harm the
device, repeatable results cannot be expected. RAM input
signals must be stabilized for long enough to meet the TAPs
input data capture setup plus hold time (tCS plus tCH). The RAMs
clock inputs need not be paused for any other TAP operation
except capturing the I/O ring contents into the boundary scan
register. Moving the controller to shift-DR state then places the
boundary scan register between the TDI and TDO balls.
1
0
1
RESERVED
1
1
0
RESERVED
1
1
1
BYPASS
Notes
1, 2
The BYPASS instruction is loaded in the instruction register
when the bypass register is placed between TDI and TDO.
This occurs when the TAP controller is moved to the shift-DR
state. This allows the board level scan path to be shortened to
facilitate testing of other devices in the scan path.
Notes: 1. Data in output register is not guaranteed if EXTEST instruction is loaded.
2. After performing EXTEST, power-up conditions are required in order to return part to normal
operation.
Rev.0.0, Dec. 2002, page 24 of 30
HM66AEB36102/18202/9402
ID Register
Part
Revision number
(31:29)
Type number (28:12)
Vendor JEDEC code
(11:1)
Start
bit (0)
HM66AEB36102
000
00010011010000000
00000000111
1
HM66AEB18202
000
00010010010000000
00000000111
1
HM66AEB9402
000
00010000010000000
00000000111
1
Rev.0.0, Dec. 2002, page 25 of 30
HM66AEB36102/18202/9402
Boundary Scan Order
Signal names
Signal names
Bit #
Ball ID
×9
×18
×36
Bit #
Ball ID
×9
×18
1
6R
C
C
C
36
10E
NC
NC
×36
DQ15
2
6P
C
C
C
37
10D
NC
NC
NC
3
6N
SA
SA
SA
38
9E
NC
NC
NC
4
7P
SA
SA
SA
39
10C
NC
DQ7
DQ17
5
7N
SA
SA
SA
40
11D
NC
NC
DQ16
6
7R
SA
SA
SA
41
9C
NC
NC
NC
7
8R
SA
SA
SA
42
9D
NC
NC
NC
8
8P
SA
SA
SA
43
11B
DQ3
DQ8
DQ8
9
9R
SA
SA
SA
44
11C
NC
NC
DQ7
10
11P
DQ8
DQ0
DQ0
45
9B
NC
NC
NC
11
10P
NC
NC
DQ9
46
10B
NC
NC
NC
12
10N
NC
NC
NC
47
11A
CQ
CQ
CQ
13
9P
NC
NC
NC
48
10A
SA
SA
NC
14
10M
NC
DQ1
DQ11
49
9A
SA
SA
SA
15
11N
NC
NC
DQ10
50
8B
SA
SA
SA
16
9M
NC
NC
NC
51
7C
SA
SA
SA
17
9N
NC
NC
NC
52
6C
SA
SA0
SA0
18
11L
DQ0
DQ2
DQ2
53
8A
LD
LD
LD
19
11M
NC
NC
DQ1
54
7A
NC
NC
BW1
20
9L
NC
NC
NC
55
7B
BW
BW0
BW0
21
10L
NC
NC
NC
56
6B
K
K
K
22
11K
NC
DQ3
DQ3
57
6A
K
K
K
23
10K
NC
NC
DQ12
58
5B
NC
NC
BW3
24
9J
NC
NC
NC
59
5A
NC
BW1
BW2
25
9K
NC
NC
NC
60
4A
R/W
R/W
R/W
26
10J
DQ1
DQ4
DQ13
61
5C
SA
SA
SA
27
11J
NC
NC
DQ4
62
4B
SA
SA
SA
28
11H
ZQ
ZQ
ZQ
63
3A
SA
SA
SA
29
10G
NC
NC
NC
64
2A
VSS
VSS
VSS
30
9G
NC
NC
NC
65
1A
CQ
CQ
CQ
31
11F
NC
DQ5
DQ5
66
2B
NC
DQ9
DQ27
32
11G
NC
NC
DQ14
67
3B
NC
NC
DQ18
33
9F
NC
NC
NC
68
1C
NC
NC
NC
34
10F
NC
NC
NC
69
1B
NC
NC
NC
35
11E
DQ2
DQ6
DQ6
70
3D
NC
DQ10
DQ19
Rev.0.0, Dec. 2002, page 26 of 30
HM66AEB36102/18202/9402
Signal names
Signal names
Bit #
Ball ID
×9
×18
×36
Bit #
Ball ID
×9
×18
71
3C
NC
NC
DQ28
91
2L
DQ6
DQ15
×36
DQ33
72
1D
NC
NC
NC
92
3L
NC
NC
DQ24
73
2C
NC
NC
NC
93
1M
NC
NC
NC
74
3E
DQ4
DQ11
DQ20
94
1L
NC
NC
NC
75
2D
NC
NC
DQ29
95
3N
NC
DQ16
DQ25
76
2E
NC
NC
NC
96
3M
NC
NC
DQ34
77
1E
NC
NC
NC
97
1N
NC
NC
NC
78
2F
NC
DQ12
DQ30
98
2M
NC
NC
NC
79
3F
NC
NC
DQ21
99
3P
DQ7
DQ17
DQ26
80
1G
NC
NC
NC
100
2N
NC
NC
DQ35
81
1F
NC
NC
NC
101
2P
NC
NC
NC
82
3G
DQ5
DQ13
DQ22
102
1P
NC
NC
NC
83
2G
NC
NC
DQ31
103
3R
SA
SA
SA
84
1H
DOFF
DOFF
DOFF
104
4R
SA
SA
SA
85
1J
NC
NC
NC
105
4P
SA
SA
SA
86
2J
NC
NC
NC
106
5P
SA
SA
SA
87
3K
NC
DQ14
DQ23
107
5N
SA
SA
SA
88
3J
NC
NC
DQ32
108
5R
SA
SA
SA
89
2K
NC
NC
NC
109

INTERNAL
INTERNAL
INTERNAL
90
1K
NC
NC
NC
Note: In boundary scan mode,
1. Clock balls (K / K, C / C) are referenced to each other and must be at opposite logic levels for
reliable operation.
2. CQ and CQ data are synchronized to the respective C and C.
3. If C and C tied high, CQ is generated with respect to K and CQ is generated with respect to K.
Rev.0.0, Dec. 2002, page 27 of 30
HM66AEB36102/18202/9402
TAP Controller State Diagram
1
Test-LogicReset
0
0
Run-Test/
Idle
1
1
SelectDR-Scan
0
1
0
1
Capture-DR
Capture-IR
0
0
Shift-DR
Shift-IR
0
1
1
1
Exit1-IR
0
0
0
Pause-DR
0
Pause-IR
1
1
0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
0
1
Exit1-DR
0
1
SelectIR-Scan
Update-IR
0
1
0
Notes: The value adjacent to each state transition in this figure represents the signal present
at TMS at the time of a rising edge at TCK.
No matter what the original state of the controller, it will enter Test-Logic-Reset when
TMS is held high for at least five rising edges of TCK.
Rev.0.0, Dec. 2002, page 28 of 30
HM66AEB36102/18202/9402
Package Dimensions
HM66AEB36102/18202/9402BP (BP-165A)
14 × 1.00
Unit: mm
15.00 ± 0.20
165 × φ0.50 ± 0.05
11 10 9 8 7 6 5 4 3 2 1
17.00 ± 0.20
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
10 × 1.00
C
0.40 ± 0.06
0.10 C
1.44 ± 0.10
0.25 C
Hitachi Code
JEDEC
JEITA
Mass (reference value)
BP-165A
–
–
–
Rev.0.0, Dec. 2002, page 29 of 30
HM66AEB36102/18202/9402
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Colophon 7.0
Rev.0.0, Dec. 2002, page 30 of 30