ETC HY51V65164ASLTC50

HY51V64164A,HY51V65164A
4Mx16, Extended Data Out mode
2nd Generation
DESCRIPTION
This family is a 64M bit dynamic RAM organized 4,194,304 x 16-bit configuration with Extended Data Out mode CMOS
DRAMs. Extended data out mode is a kind of page mode which is useful for the read operation. The circuit and process
design allow this device to achieve high performance and low power dissipation. Optional features are access time(50 or
60ns) and refresh cycle(8K ref. or 4K ref.) and power consumption (Normal or Low power with self refresh). Hyundai’s
advanced circuit design and process technology allow this device to achieve high bandwidth, low power consumption and
high reliability.
FEATURES
Ÿ Extended data out operation
Ÿ Read-modify-write capability
Ÿ Multi-bit parallel test capability
Ÿ LVTTL(3.3V) compatible inputs and outputs
Ÿ /CAS-before-/RAS, /RAS-only, Hidden and
Self refresh capability
Ÿ JEDEC standard pinout
50-pin plastic TSOP-II (400mil)
Ÿ Single power supply of 3.3 ± 0.3V
Ÿ Early write or output enable controlled write
Ÿ Max. Active power dissipation
Ÿ Fast access time and cycle time
Speed
8K refresh
4K refresh
Speed
tRAC
tCAC
tHPC
50
396mW
504mW
50
50ns
13ns
20ns
60
324mW
432mW
60
60ns
15ns
25ns
Ÿ Refresh cycles
Part number
Refresh
HY51V64164A1)
8K
HY51V65164A2)
4K
Normal
L-part
64ms
128ms
1) Normal read / write, /RAS only refresh : 8K cycles / 64ms
/CAS-before-/RAS, Hidden refresh
: 4K cycles / 64ms
2) Normal read / write, /RAS only refresh : 4K cycles / 64ms
/CAS-before-/RAS, Hidden refresh
: 4K cycles / 64ms
ORDERING INFORMATION
Part Name
Refresh
Power
Package
HY51V64164ATC
8K
50Pin TSOP-II
HY51V64164ALTC
8K
L-part
50Pin TSOP-II
HY51V64164ASLTC
8K
*SL-part
50Pin TSOP-II
HY51V65164ATC
4K
HY51V65164ALTC
4K
L-part
50Pin TSOP-II
HY51V65164ASLTC
4K
*SL-part
50Pin TSOP-II
50Pin TSOP-II
*SL : Self refresh with low power.
This document is a general product description and is subject to change without notice. Hyundai electronics does not assume any responsibility for use of
circuits described. No patent licences are implied
Hyundai Semiconductor
Rev.12/Sep.98
1
HY51V64164A,HY51V65164A
FUNCTIONAL BLOCK DIAGRAM
DQ0 ~ DQ15
8
8
8
Data Input Buffer
8
Data Output Buffer
OE
DQ0~7
DQ8~15
DQ0~7
DQ8~15
8
8
8
8
WE
LCAS
UCAS
CAS Clock
Generator
RAS
Address Buffer
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
*(A12)
(9/10)*
Cloumn
Predecoder
Column Decoder
Sense Amp
I/O Gate
Refresh Controller
Refresh Counter
Row
Decoder
Row Predecoder
(13/12)*
Memory Array
4,194,304x16
(13/12)*
RAS Clock
Generator
Substrate Bias
Generator
X32 Parallel
Test
*(A12) for 8K refresh part
(8K Refresh / 4K Refresh)*
4Mx16,EDO DRAM
Rev.12/Sep.98
2
VCC
VSS
HY51V64164A,HY51V65164A
PIN CONFIGURATION (Marking Side)
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
N.C
VCC
WE
RAS
N.C
N.C
N.C
N.C
A0
A1
A2
A3
A4
A5
VCC
•
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
N.C
VSS
LCAS
UCAS
OE
N.C
N.C
A12(N.C)*
A11
A10
A9
A8
A7
A6
VSS
50Pin Plastic TSOP- II (400mil)
A12(N.C)* : For 4K refresh product
PIN DESCRIPTION
Pin Name
Parameter
/RAS
Row Address Strobe
/CAS
Column Address Strobe
/WE
Write Enable
/OE
Output Enable
A0~A12
Address Input (8K Refresh Product)
A0~A11
Address Input (4K Refresh Product)
DQ0~DQ15
Data In/Out
Vcc
Power (3.3V)
Vss
Ground
NC
No Connection
4Mx16,EDO DRAM
Rev.12/Sep.98
3
HY51V64164A,HY51V65164A
ABSOLUTE MAXIMUM RATING
Symbol
Parameter
Rating
Unit
TA
Ambient Temperature
0 to 70
°C
TSTG
Storage Temperature
-55 to 150
°C
VIN, VOUT
Voltage on Any Pin relative to VSS
-0.5 to 6.0
V
VCC
Voltage on VCC relative to VSS
-0.5 to 4.6
V
IOS
Short Circuit Output Current
50
mA
PD
Power Dissipation
1
W
TSOLDER
Soldering Temperature Ÿ Time
260 Ÿ 10
°C Ÿ sec
Note : Operation at or above Absolute Maximum Ratings could adversely affect device reliability and cause permanent
damage.
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0°C to 70°C )
Symbol
Parameter
Min
Typ
Max
UNIT
VCC
Power Supply Voltage
3.0
3.3
3.6
V
VIH
Input High Voltage
2.0
-
VCC+0.31)
V
VIL
Input Low Voltage
-0.32)
-
0.8
V
Note : All voltages are referenced to VSS.
1) 6.0V at pulse width 10ns which is measured at VCC.
2) -1.0V at pulse width 10ns which is measured at VSS.
DC AND OPERATING CHARACTERISTICS
Symbol
Parameter
Test condition
Min
Max
Unit
ILI
Input Leakage Current
(Any input)
VSS ≤ VIN ≤ VCC + 0.3
All other pins not under test = VSS
-5
5
µA
ILO
Output Leakage Current
(Any input)
VSS ≤ VOUT ≤ VCC
/RAS&/CAS at VIH
-5
5
µA
VOL
Output Low Voltage
IOL = 2.0mA
-
0.4
V
VOH
Output High Voltage
IOL = -2.0mA
2.4
-
V
4Mx16,EDO DRAM
Rev.12/Sep.98
4
HY51V64164A,HY51V65164A
DC CHARACTERISTICS
(TA = 0°C to 70°C , VCC = 3.3 ± 0.3V , VSS = 0V, unless otherwise noted.)
Symbol
Parameter
Test condition
Max. Current
Speed
4K refresh
110
90
140
120
mA
1
1
mA
ICC1
Operating Current
/RAS, /CAS Cycling
tRC = tRC(min.)
ICC2
LVTTL Standby
Current
/RAS, /CAS ≥ VIH
Other inputs ≥ VSS
ICC3
/RAS-only Refresh
Current
/RAS Cycling,/CAS = VIH
tRC = tRC(min.)
50
60
110
90
140
120
mA
ICC4
EDO mode Current
/CAS Cycling, /RAS = VIL
tHPC = tHPC(min.)
50
60
120
100
130
110
mA
ICC5
CMOS Standby
Current
/RAS = /CAS ≥ VCC - 0.2V
L-part
500
300
500
300
µA
ICC6
/CAS-before-/RAS
Refresh Current
tRC = tRC(min.)
50
60
140
120
140
120
mA
ICC7
Battery Back-up
Current (L-part)
VIH = VCC - 0.2V, VIL = 0.2V
/CAS = CBR cycling or 0.2V
/OE&/WE = VIH = VCC - 0.2V
Address = Don’t care
DQ0~DQ15 = Open, tRAS ≤ 300ns
tRC=31.25uS
550
550
µA
/RAS&/CAS = 0.2V
Other pins are same as ICC7
450
450
µA
ICC8
Self Refresh Current
(L-part)
50
60
Unit
8K refresh
Note
1. ICC1, ICC3, ICC4 and ICC6 depend on output loading and cycle rates(tRC and tHPC).
2. Specified values are obtained with output unloaded.
3. ICC is specified as an average current. In ICC1, ICC3, ICC6, address can be changed only once while /RAS=VIL. In ICC4,
address can be changed maximum once while /CAS=VIH withen one EDO mode cycle time tHPC.
4Mx16,EDO DRAM
Rev.12/Sep.98
5
HY51V64164A,HY51V65164A
AC CHARACTERISTICS
(TA = 0 °C to 70 °C, VCC = 3.3 ± 0.3V , VSS = 0V, unless otherwise noted.)
50ns
# Symbol
60ns
Parameter
Unit
Min
Max
Min
Max
Note
1
tRC
Random read or write cycle time
84
-
104
-
ns
2
tRWC
Read-modify-write cycle time
120
-
140
-
ns
3
tHPC
EDO mode cycle time
20
-
25
-
ns
4
tHPRWC
EDO mode read-modify-write cycle time
57
-
65
-
ns
5
tRAC
Access time from /RAS
-
50
-
60
ns
4,5,10,11
6
tCAC
Access time from /CAS
-
13
-
15
ns
4,5,10
7
tAA
Access time from column address
-
25
-
30
ns
4,5,11
8
tCPA
Access time from /CAS precharge
-
30
-
35
ns
4
9
tCLZ
/CAS to output low impedance
0
-
0
-
ns
3
10 tCEZ
Output buffer turn-off delay from /CAS
0
10
0
15
ns
11 tOLZ
/OE to output in low impedance
0
-
0
-
ns
12 tT
Transition time(rise and fall)
2
50
2
50
ns
13 tRP
/RAS precharge time
30
-
40
-
ns
14 tRAS
/RAS pulse width
50
10K
60
10K
ns
15 tRASP
/RAS pulse width(EDO mode)
50
100K
60
100K
ns
16 tRSH
/RAS hold time
13
-
15
-
ns
17 tCSH
/CAS hold time
40
-
45
-
ns
18 tCAS
/CAS pulse width
8
10K
10
10K
ns
19 tRCD
/RAS to /CAS delay time
15
37
20
45
ns
10
20 tRAD
/RAS to column address delay time
13
25
15
30
ns
11
21 tCRP
/CAS to /RAS precharge time
5
-
5
-
ns
22 tCP
/CAS precharge time
8
-
10
-
ns
23 tASR
Row address set-up time
0
-
0
-
ns
24 tRAH
Row address hold time
8
-
10
-
ns
25 tASC
Column address set-up time
0
-
0
-
ns
14
26 tCAH
Column address hold time
8
-
10
-
ns
14
27 tRAL
Column address to /RAS lead time
25
-
30
-
ns
28 tRCS
Read command set-up time
0
-
0
-
ns
29 tRCH
Read command hold time referenced to /CAS
0
-
0
-
ns
7
30 tRRH
Read command hold time referenced to /RAS
0
-
0
-
ns
7
31 tWCH
Write command hold time
10
-
10
-
ns
4Mx16,EDO DRAM
Rev.12/Sep.98
6
4
15
HY51V64164A,HY51V65164A
AC CHARACTERISTICS
Continued
50ns
# Symbol
60ns
Parameter
Unit
Min
Max
Min
Max
Note
32 tWP
Write command pulse width
8
-
10
-
ns
33 tRWL
Write command to /RAS lead time
15
-
15
-
ns
34 tCWL
Write command to /CAS lead time
8
-
10
-
ns
17
35 tDS
Data-in set-up time
0
-
0
-
ns
8,20
36 tDH
Data-in hold time
7
-
10
-
ns
8,20
Refresh period(4096 cycles)
-
64
-
64
ms
12,13
Refresh period(8192 cycles)
-
64
-
64
ms
12,13
Refresh period(L-part)
-
128
-
128
ms
12,13
38 tWCS
Write command set-up time
0
-
0
-
ns
9
39 tCWD
/CAS to /WE delay time
34
-
36
-
ns
9,16
40 tRWD
/RAS to /WE delay time
70
-
80
-
ns
9
41 tAWD
Column address to /WE delay time
45
-
50
-
ns
9
42 tCSR
/CAS set-up time(CBR cycle)
5
-
5
-
ns
18
43 tCHR
/CAS hold time(CBR cycle)
10
-
10
-
ns
19
44 tRPC
/RAS to /CAS precharge time
5
-
5
-
ns
45 tCPT
/CAS precharge time(CBR counter test)
25
-
30
-
ns
46 tROH
/RAS hold time referenced to /OE
5
-
5
-
ns
47 tOEA
/OE access time
-
13
-
15
ns
48 tOED
/OE to data delay
13
-
15
-
ns
49 tOEZ
Output buffer turn-off delay time from /OE
0
10
0
15
ns
50 tOEH
/OE command hold time
13
-
15
-
ns
51 tCPWD
/WE delay time from /CAS precharge
45
-
54
-
ns
52 tRHCP
/RAS hold time from /CAS precharge
30
-
35
-
ns
53 tWRP
/WE to /RAS precharge time(CBR cycle)
10
-
10
-
ns
54 tWRH
/WE to /RAS hold time(CBR cycle)
10
-
10
-
ns
55 tWTS
Write command set-up time(test mode in)
10
-
10
-
ns
56 tWTH
Write command hold time(test mode in)
10
-
10
-
ns
57 tRASS
/RAS pulse width(self refresh)
100K
-
100K
-
ns
58 tRPS
/RAS precharge time(self refresh)
100
-
110
-
ns
59 tCHS
/CAS hold time(self refresh)
-50
-
-50
-
ns
60 tDOH
Output data hold time
5
-
5
-
ns
37 tREF
4Mx16,EDO DRAM
Rev.12/Sep.98
7
6
6
HY51V64164A,HY51V65164A
AC CHARACTERISTICS
Continued
50ns
# Symbol
60ns
Parameter
Min
Max
Min
Max
Unit
Note
61 tREZ
Output buffer turn-off delay from /RAS
0
10
0
15
ns
6
62 tWEZ
Output buffer turn-off delay from /WE
0
10
0
15
ns
6
63 tWED
/WE to data delay time
15
-
15
-
ns
64 tOEP
/OE precharge time
5
-
5
-
ns
65 tWPE
/WE pulse width(EDO cycle)
5
-
5
-
ns
66 tOCH
/OE to /CAS hold time
5
-
5
-
ns
67 tCHO
/CAS hold time to /OE
5
-
5
-
ns
4Mx16,EDO DRAM
Rev.12/Sep.98
8
HY51V64164A,HY51V65164A
TEST MODE
50ns
# Symbol
60ns
Parameter
Unit
Min
Max
Min
Max
Note
1
tRC
Random read or write cycle time
89
-
109
-
ns
2
tRWC
Read-modify-write cycle time
125
-
145
-
ns
3
tHPC
EDO mode cycle time
25
-
30
-
ns
4
tHPRWC
EDO mode read-modify-write cycle time
62
-
70
-
ns
5
tRAC
Access time from /RAS
-
55
-
65
ns
4,5,10,11
6
tCAC
Access time from /CAS
-
18
-
20
ns
4,5,10
7
tAA
Access time from column address
-
30
-
35
ns
4,5,11
8
tCPA
Access time from /CAS precharge
-
35
-
40
ns
4
14 tRAS
/RAS pulse width
55
10K
65
10K
ns
15 tRASP
/RAS pulse width(EDO mode)
55
100K
65
100K
ns
16 tRSH
/RAS hold time
20
-
20
-
ns
17 tCSH
/CAS hold time
45
-
55
-
ns
18 tCAS
/CAS pulse width
13
10K
15
10K
ns
27 tRAL
Column address to /RAS lead time
30
-
35
-
ns
39 tCWD
/CAS to /WE delay time
39
-
41
-
ns
40 tRWD
/RAS to /WE delay time
75
-
85
-
ns
41 tAWD
Column address to /WE delay time
50
-
55
-
ns
47 tOEA
/OE access time
-
18
-
20
ns
48 tOED
/OE to data delay
18
-
20
-
ns
50 tOEH
/OE command hold time
18
-
20
-
ns
51 tCPWD
/WE delay time from /CAS precharge
50
-
59
-
ns
4Mx16,EDO DRAM
Rev.12/Sep.98
9
4
16
9
9
HY51V64164A,HY51V65164A
NOTE
1. An initial pause of 200µs is required after power-up followed by 8 /RAS-only refresh cycles before proper device
operation is achieved. In case of using internal refresh counter, a minimum of 8 /CAS- before-/RAS initialization
cycles instead of 8 /RAS-only refresh cycles are required. The device should be carefully initialized to be prevented
from being entered into multi bit parallel test mode during initialization.
2. If /RAS=VSS during power-up, the HY51V64164A, HY51V65164A could begin an active cycle. This condition results in
higher current than necessary current which is demanded from the power supply during power-up.
3. It is recommended that /RAS and /CAS track with Vcc during power-up or be held at a valid VIH in order to minimize
the power-up current.
4. V IH(min.) and V IL(max.) are reference levels for measuring timing of input signals. Transition times are measured
between VIH(min.) and VIL(max.), and are assumed to be 2ns for all inputs.
5. Measured at VOH=2.0V and VOL=0.8V with a load equivalent to 1TTL loads and 100pF.
6. tWEZ, tREZ, tCEZ and tOEZ define the time at which the output achieves the open circuit condition and is not referenced
to output voltage levels.
7. Either tRCH or tRRH must be satisfied for a read cycle.
8. These parameters are referenced to /CAS leading edge in early write cycles and to /WE leading edge in read-modifywrite cycles and late write cycle.
9. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If tWCS ≥ tWCS(min.), the cycle is an early write cycle and data out pin will remain open
circuit (high impedance) through the entire cycle. If tRWD ≥ tRWD(min.), tCWD ≥ tCWD(min.), tAWD ≥ tAWD(min), and tCPWD ≥
tCPWD(min.), the cycle is a read-modify-write cycle and data out will contain data read from the selected cell. If neither
of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate.
10.Operation within the tRCD(max.) limit ensures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC.
11.Operation within the tRAD(max.) limit ensures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only.
If tRAD is greater than the specified tRAD(max.) limit, then access time is controlled by tAA.
12.tREF(max)=128ms is applied to L-parts.
13.A burst of 4096(4K refresh part) /RAS-only refresh cycles must be executed within 64ms (128ms for L-parts) after
exiting self refresh.A burst of 8192(8K refresh part) /RAS-only refresh cycles must be executed within 64ms (128ms
for L-parts) after exiting self refresh.(CBR refresh & Hidden refresh : 4K cycle/64ms)
14.tASC,tCAH are referenced to the earlier /CAS falling edge.
15.tCP is specified from the last /CAS rising edge in the previous to the first /CAS falling edge in the next cycle.
16.tCWD is referenced to the later /CAS falling edge at word read-modifiy-write cycle.
17.tCWL is specified from /WE falling edge to the earlier /CAS rising edge.
18.tCSR is referenced to the earlier /CAS falling before /RAS transition low.
19.tCHR is referenced to the later /CAS rising high after /RAS transition low.
20.tDS is specified for the earlier /CAS falling edge and tDH is specified by the later /CAS falling edge in early write cycle.
CAPACITANCE
(TA = 0°C to 70°C , VCC = 3.3 ± 0.3V, VSS = 0V, f = 1MHz, unless otherwise noted.)
Symbol
Parameter
Typ.
Max
Unit
CIN1
Input Capacitance (A0~A12)
-
5
pF
CIN2
Input Capacitance (/RAS, /CAS, /WE, /OE)
-
7
pF
CDQ
Data Input / Output Capacitance (DQ0~DQ15)
-
7
pF
4Mx16,EDO DRAM
Rev.12/Sep.98
10