IDT7381 16-BIT CASCADABLE ALU COMMERCIAL TEMPERATURE RANGE 16-BIT CMOS CASCADABLE ALU FEATURES: − − − − − − − − − − − − − IDT7381 DESCRIPTION: High-performance 16-bit Arithmetic Logic Unit (ALU) 25ns to 55ns clocked ALU operations Ideal for radar, sonar or image processing applications 74S381 instruction set (8 functions) Replaces Gould S614381 or Logic Devices L4C381 Cascadable with or without carry look-ahead Pipeline or flow-through modes Internal feedback path for accumulation Three-state outputs TTL-compatible Produced with advanced submicron CMOS technology Available in PLCC Speeds available: L/25/30/40/55 The IDT7381 is a high-speed cascadable Arithmetic Logic Unit (ALU). These three-bus devices have two input registers, an ultra-fast 16-bit ALU and 16-bit output register. With IDT’s high-performance CMOS technology, the IDT7381 can do arithmetic or logic operations in 25ns. The IDT7381 functionally replaces four 54/74S381 four-bit ALUs in a 68-pin package. The two input operands, A and B, can be clocked or fed through for flexible pipelining. The F output can also be set into clocked or flow-through mode. An output enable is provided for three-state control of the output port on a bus. The IDT7381 has three function pins to select 1 of 8 arithmetic or logic operations. The two R and S selection pins determine whether A, B, F or 0 are fed into the ALU. This ALU has carry-out, propagate and generate outputs for cascading using carry look-ahead. FUNCTIONAL BLOCK DIAGRAM A0 B0 -1 5 -1 5 16 ENA 16 A R EG B R EG A MUX CL K ENB B MUX 0000 H FT AB 0000 H S MUX R MUX RS 0 -1 2 P G C1 6 OVF Z I 16-BIT ALU C0 EN F FTF 0-2 3 F RE G F M UX PO W E R SU P P LY OE GND VCC 16 F0 - 15 COMMERCIAL TEMPERATURE RANGE APRIL 2001 1 c 2001 Integrated Device Technology, Inc. DSC-2525/- IDT7381 16-BIT CASCADABLE ALU COMMERCIAL TEMPERATURE RANGE B8 B9 B 10 B 11 B 12 A9 9 10 2 A10 11 A11 12 1 68 67 66 65 64 63 62 61 60 Pin 1 59 Desig nato r 58 A12 13 57 B4 A13 14 56 B3 A14 15 55 B2 A15 16 54 B1 CL K 17 53 B0 VCC 18 52 ENA GND 19 51 ENB C 16 20 50 FT AB P 21 49 RS 1 G 22 48 RS 0 Z 23 47 I 2 O VF 24 46 I 1 EN F 25 45 I 0 FTF 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 PLCC TOP VIEW 2 F1 F2 F3 F4 F5 F6 F7 F8 F9 F 10 F 11 F 12 F 13 F 14 F 15 OE J68 - 1 F0 3 B 13 4 B 14 A3 5 B 15 A4 6 A0 A5 7 A1 A6 8 A2 A7 A8 PIN CONFIGURATION B7 B6 B5 C0 IDT7381 16-BIT CASCADABLE ALU COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION Pin Name I/O Description A0 - A15 I Sixteen–bit data input port. B0 - B15 I Sixteen–bit data input port. ENA I Register enable for the A input port; active low pin. ENB I Register enable for the B input port; active low pin. FTAB I Flow–through control pin. When this pin is high, both register A and B are transparent. F0 – F15 O Sixteen–bit data output port. ENF I Register enable for the F output port; active low pin. FTF I Flow–through control pin. When this pin is high, the F register is transparent. CLK I Clock input. OE I Output enable control pin. When this pin is high, the output port F is in a high impedance state. When low, the output port F is active. C0 I Carry input. This pin receives arithmetic carries from less significant ALU components in a cascade configuration. C16 O Carry output. This pin produces arithmetic carries to more significant ALU components in a cascaded configuration. OVF O This pin indicates a two’s complement arithmetic overflow, when high. Z O This pin indicates a zero output result, when high. RS0 – RS1 I Two control pins used to select input operands for the R and S multiplexers. I0 - I2 I Three control pins to select the ALU function performed. P O Indicates the carry propagate output state to the ALU. G O Indicates the carry generate output state to the ALU. VCC Power supply pin, 5V. GND Ground pin, 0V. R AND S MUX TABLE ALU FUNCTION TABLE RS1 RS0 R Mux S Mux I2 I1 I0 0 0 A F 0 0 0 F=0 0 1 A 0 0 0 1 F = R + S + C0 1 0 0 B 0 1 0 F = R + S + C0 1 1 A B 0 1 1 F = R + S + C0 1 0 0 F = R xor S 1 0 1 F = R or S 1 1 0 F = R and S 1 1 1 F = all 1’s 3 Function IDT7381 16-BIT CASCADABLE ALU COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) Symbol Description CAPACITANCE (TA = +25°C, f = 1.0MHz) Max. Unit Symbol Parameter(1) Conditions Pkg. Typ. Unit CIN Input Capacitance VIN = 0V PGA 10 pF PLCC 5 PGA 12 PLCC 7 VTERM Terminal Voltage with Respect to Ground –0.5 to VCC + 0.5 V VCC Power Supply Voltage –0.5 to +7.0 V TSTG Storage Temperature –55 to +125 °C IOUT DC Output Current 50 mA C OUT Output Capacitance VOUT = 0V pF NOTE: 1. This parameter is sampled at initial characterization and is not production tested. NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Under no circumstances should an input of an I/O Pin be greater than VCC + 0.5V. DC ELECTRICAL CHARACTERISTICS Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5% Symbol Test Conditions(1) Parameter Min. Typ.(2) Max. Unit 2 — — V VIH Input HIGH Level Guaranteed Logic HIGH Level VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V IIH Input HIGH Current VCC = Max., VIN = 2.7V — — 10 µA IIL Input LOW Current VCC = Max., VIN = 0.5V — — –10 µA IOS(3) Short Circuit Current VCC = Max., VOUT = GND IOZ Off State (High Impedance) VCC = Max. Output Current VOH Output HIGH Voltage VCC = Min. VOL Output LOW Voltage VCC = Min. –20 — –100 mA VO = 0.5V — –0.1 –20 µA VO = 2.7V — –0.1 20 IOH = –4mA 2.4 — — V IOL = 8mA — — 0.5 V VIN = VIH or VIL VIN = VIH or VIL NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4 IDT7381 16-BIT CASCADABLE ALU COMMERCIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5% Symbol Test Conditions(1) Parameter Min. Typ.(2) Max. Unit ICC Quiescent Power Supply Current VCC = Max. VIN =GND or VCC — 2 6 mA ∆ICC(3) Quiescent Power Supply Current TTL Input HIGH VCC = Max. VIN = 3.4V — 0.5 1 mA/ input ICCD(4) Dynamic Power Supply Current VCC = Max. Outputs disabled VIN = GND or VCC Mode: FTAB = FTF = 1 — 15 48 µA/ MHz ICCD1 Dynamic Power Supply Current VCC = Max. Outputs Disabled All Data Inputs Disabled fi = 10MHz, fCP = 10MHz 50% Duty Cycle VIL = GND, VIH = VCC Mode: FTAB = FTF = 1 — 20 33 mA ICCD2(6) Dynamic Power Supply Current VCC = Max. Outputs Enabled. (CL = 50pF) All Data Inputs Sw itching fi = 10MHz, fCP = 10MHz — 40 60 mA Outputs Disabled — 22 39 mA Outputs Enabled — 42 76 mA 50% Duty Cycle VIL = GND, VIH = VCC Mode: FTAB = FTF = 1 IC(7) Total Power Supply Current VCC = Max. VIN = GND or VCC All Data Inputs Switching fi = 10MHz, fCP = 10MHz 50% Duty Cycle NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived from ICCD1 for use in Total Power Supply calculations. 5. Total power supply current is calculated as follows: IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCP + fiNi) ICC = Quiescent Current ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz. 6. This parameter is not production tested but is an indicator of the power dissipated with outputs loaded. 7. Values for these conditions are examples of the IC formula in note 5 above. These are guaranteed but not tested. 5 IDT7381 16-BIT CASCADABLE ALU COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS (VCC = 5V ± 5%, TA = 0°C to +70°C) Maximum Combinational Propagation Delays IDT7381L25 From Input Z,OVF IDT7381L30 F0–15 P, G, N C16 F0–15 P, G, N CLK 13 22 C0 — — I0–2, RS0, RS1 — 22 22 CLK 27 22 26 C0 22 — 16 I0–2, RS0, RS1 22 22 22 22 A0–A15, B0–B15 — 18 25 CLK 13 — — C0 — — I0–2, RS0, RS1 — 22 A0–A15, B0–B15 26 C0 I0–2, RS0, RS1 Z,OVF C16 Unit 26 22 20 28 30 28 ns 16 16 — — 20 20 ns 22 — 28 28 28 ns 22 33 28 30 28 ns 16 28 — 20 20 ns 28 28 28 28 ns 22 — 24 30 28 ns — 19 — — — ns 16 16 — — 20 20 ns 22 22 — 28 28 28 ns 18 25 22 32 24 30 28 ns 22 — 16 16 28 — 20 20 ns 22 22 22 22 28 28 28 28 ns FTAB = 0, FTF = 0 FTAB = 0, FTF = 1 FTAB = 1, FTF = 0 FTAB = 1, FTF = 1 Maximum Combinational Propagation Delays IDT7381L40 From Input IDT7381L55 F0–15 P, G, N Z,OVF C16 F0–15 P, G, N Z,OVF C16 Unit CLK 26 30 44 32 32 38 53 36 ns C0 — — 28 20 — — 34 22 ns I0–2, RS0, RS1 — 32 34 35 — 42 42 42 ns CLK 46 30 44 32 56 38 53 36 ns C0 30 — 28 20 37 — 34 22 ns I0–2, RS0, RS1 40 32 34 35 55 42 42 42 ns A0–A15, B0–B15 — 30 40 32 — 36 46 37 ns CLK 26 — — — 32 — — — ns C0 — — 28 20 — — 34 22 ns I0–2, RS0, RS1 — 32 34 35 — 42 42 42 ns A0–A15, B0–B15 40 30 40 32 55 36 46 37 ns C0 30 — 28 20 37 — 34 22 ns I0–2, RS0, RS1 40 32 34 35 55 42 42 42 ns FTAB = 0, FTF = 0 FTAB = 0, FTF = 1 FTAB = 1, FTF = 0 FTAB = 1, FTF = 1 NOTES: 1. Only for FTF = 0. 2. Minimum propagation delays are not production tested but guaranteed to be greater than or equal to 3ns. 6 IDT7381 16-BIT CASCADABLE ALU COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS (VCC = 5V ± 5%, TA = 0°C to +70°C) - (Cont'd.) Minimum Set-up and Hold Times Relative to Clock (CLK) IDT7381L25 Input IDT7381L30 IDT7381L40 IDT7381L55 Set-up Hold Set-up Hold Set-up Hold Set-up Hold Unit A0–A15, B0–B15 6 0 6 0 6 0 8 0 ns C0 (1) 16 0 16 0 16 0 21 0 ns I0–2, RS0, RS1 (1) 24 0 29 0 32 0 44 0 ns ENA, ENB, ENF 6 0 6 0 6 0 8 0 ns A0–A15, B0–B15 16 0 25 0 28 0 35 0 ns C0 16 0 16 0 16 0 21 0 ns I0–2, RS0, RS1 24 0 29 0 32 0 44 0 ns ENF 6 0 6 0 6 0 8 0 ns FTAB = 0, FTF = X FTAB = 1, FTF = 0 Minimum Clock Cycle Times and Pulse Widths Parameter IDT7381L25 IDT7381L30 IDT7381L40 IDT7381L55 Unit Clock LOW Time 6 8 10 14 ns Clock HIGH Time 6 8 10 14 ns Clock Period 20 25 34 43 ns IDT7381L25 IDT7381L30 IDT7381L40 IDT7381L55 Unit Enable Time 10 15 18 20 ns Disable Time 10 15 18 20 ns Maximum Output Enable/Disable Times Parameter NOTES: 1. Only for FTF = 0. 2. Minimum propagation delays are not production tested but guaranteed to be greater than or equal to 3ns. 7 IDT7381 16-BIT CASCADABLE ALU COMMERCIAL TEMPERATURE RANGE WAVEFORMS FOR FTAB = 0, FTF = X T1 T2 CLK Set-up Hold A 0- 15 DATA 1 DATA 2 DATA 3 B 0- 15 Set-up DATA 1 C0 Hold DATA 3 DATA 2 Set-up Hold I 0- 2 , DATA 1 DATA 2 RS 0- 1 Set-up ENA, ENB ENF DATA 1 DATA 3 Hold DATA 2 DATA 3 OE Prop. 1 Disable Enable F 0- 15 Result (FTF = 0) Prop. 3 Prop. 2 Prop. 1 Disable Enable F 0- 15 Result (FTF = 1) Prop. 2 Prop. 1 P, G Result Prop. 2 Prop. 3 Prop. 1 Result Z, OVF Prop. 2 Prop. 3 Prop. 1 C 16 Result Prop. 1: Propagation delay with respect to the CLK. Prop. 2: Propagation delay with respect to I 0- 2 , RS 0- 2. Prop. 3: Propagation delay with respect to C0. 8 IDT7381 16-BIT CASCADABLE ALU COMMERCIAL TEMPERATURE RANGE WAVEFORMS FOR FTAB = 1, FTF = X T1 T2 CLK (FTF = 0) Set-up Hold A 0- 15 DATA 1 DATA 2 DATA 3 B 0- 15 Set-up DATA 1 C0 Hold DATA 2 Set-up DATA 3 Hold I0- 2 , DATA 1 DATA 2 DATA 3 RS 0- 1 Set-up DATA 2 DATA 1 ENF Hold DATA 3 OE Prop. 1 Disable Enable F 0- 15 Result (FTF = 0) Prop. 4 Prop. 3 Prop. 2 Disable Enable F 0- 15 Result (FTF = 1) Prop. 4 (for FTF = 1 only) Prop. 2 Result P, G Prop. 2 Prop. 4 (For FTF = 1 only) Prop. 3 Result Z, OVF Prop. 4 (For FTF = 1 only) Prop. 3 Prop. 2 C 16 Prop. Prop. Prop. Prop. 1: 2: 3: 4: Result Propagation Propagation Propagation Propagation delay delay delay delay with with with with respect respect respect respect to to to to the CLK. I0- 2 , RS 0- 2. C0. A, B. 9 IDT7381 16-BIT CASCADABLE ALU COMMERCIAL TEMPERATURE RANGE PROPAGATION DELAY CALCULATIONS FOR TWO IDT7381S To Output From Input To Set PUT Time Flags (1) F0 – 15 Relative to Clock (CLK) FTAB = 0, FTF = 0 CLK C0 I0 – 2, RS0 – 1 A0 – 15, B0 – 15 ENA, ENB,ENF As in 16-bit case .... .... .... .... (Clk → C16) + (C0 → flag) (C0 → C16) + (C0 → flag) (I0–2, RS0–1 → C16) + (C0 → flag) .... .... .... (C0 → C16) + (C0 set–up time) (I0–2, RS0–1 → C16) + (C0 set–up time) As in 16-bit case As in 16-bit case FTAB = 0, FTF = 1 CLK C0 I0 – 2, RS0 – 1 A0 – 15, B0 – 15 ENA, ENB,ENF (Clk → C16) + (C0 → F0–15) (C0 → C16) + (C0 → F0–15) (I0–2, RS0–1 → C16) + (C0 → F0–15) .... .... (Clk → C16) + (C0 → flag) (C0 → C16) + (C0 → flag) (I0–2, RS0–1 → C16) + (C0 → flag) .... .... .... (C0 → C16) + (C0 set–up time) (I0–2, RS0–1 → C16) + (C0 set–up time) As in 16-bit case As in 16-bit case FTAB = 1, FTF = 0 CLK C0 I0 – 2, RS0 – 1 A0 – 15, B0 – 15 ENA, ENB,ENF As in 16-bit case .... .... .... .... .... (C0 → C16) + (C0 → flag) (I0–2, RS0–1 → C16) + (C0 → flag) (A0–15, B0–15 → C16) + (C0 → flag) .... .... (C0 → C16) + (C0 set–up time) (I0–2, RS0–1 → C16) + (C0 set–up time) As in 16-bit case As in 16-bit case FTAB = 0, FTF = 1 CLK C0 I0 – 2, RS0 – 1 A0 – 15, B0 – 15 ENA, ENB,ENF Don't care condition (C0 → C16) + (C0 → F0–15) (I0–2, RS0–1 → C16) + (C0 → F0–15) (A0–15, B0–15 → C16) + (C0 → F0–15) .... Don't care condition (C0 → C16) + (C0 → flag) (I0–2, RS0–1 → C16) + (C0 → flag) (A0–15, B0–15 → C16) + (C0 → flag) .... .... .... .... .... .... NOTE: 1. Flags are P, G, OVF, Z and C16. 10 IDT7381 16-BIT CASCADABLE ALU COMMERCIAL TEMPERATURE RANGE CASCADING THE IDT7381 Some applications require 32-bit or wider input operands. Cascading is the hardware solution. It provides a high speed alternative in handling more than 16-bit wide operands. 1. Cascading the IDT7381 Cascading to 32-bit wide operands takes only two IDT7381s and no external hardware. However, cascading to data widths greater than 32bit can be done in two ways: without external hardware (slow method) or by using a carry look ahead generator. a) Cascading the IDT7381 without a carry-look-ahead generator: (Figures 1 and 2) 1. Connect the C16 output of the least significant device into the C0 input of the next most significant device. 2. Common lines to all devices are: RS 0–1, I0–2, Clk, FTF, FTAB, ENA, ENB, ENF. 3. Take OVF, C16, P, G of the most significant device as valid. 4. The system’s zero flag (Z) is obtained by ANDing all zero flag results. b) Cascading three or more IDT7381s with carry-look-ahead (CLA) generator: (Figure 3) 1. Connect the P and G outputs of each device to the CLA generator’s corresponding inputs. 2. Take the CLA generator outputs into the C0 inputs of each device (except for the least significant one). 3. Common lines to all devices are: RS 0–1, I0–2, Clk, FTF, FTAB, ENA, ENB, ENF. 4. Take OVF, C16, P, G of the most significant device as valid. 5. Carry-in to the system should be connected to the C0 input of the least significant device and also to the CLA generator. 2. Time Delay Considerations Once cascading has taken place, time delays may become critical in high performance systems. Our main interest here is focused on “propagation delays”, i.e. calculating the time required for an input signal to propagate through several cascaded devices up to a specific output in another device within the cascaded system. 11 Propagation Delay The propagation delay for two devices between the input and output of interest (input to output delay) is done as follows: 1. Calculate delay between the input and C16 in the first device. 2. Calculate delay between C0 and the output in the second device. 3. Add both results. The following table is an example on how to build a propagation delay table for all inputs in a 32-bit IDT7381 cascaded system. Propagation delay calculations can be extended to n–cascaded devices as the sum of the delays in all devices between the input and output of interest. That is: (Input)1 → (C16)1 = t1 ... (C0)i → (C16)i = ti (C0)i + 1 → (C16)i + 1 = ti + 1 ... (C0)n → (Output)n = tn Where the subscript i denotes the device number and the arrow (→) represents the delay in between. Notice that i + 1 is the immediate upper device from device i. Adding the delays ti we get: Propagation delay = t1 + t2 + ... + ti + ti + 1 + ... + tn Total Delay As seen from Figure 8, the propagation delay is within the IDT7381 devices only. A complete analysis should also include the delay associated with the transmission line Li (which depends on the line length and its impedance). This line delay should then be added to the propagation delay to obtain the total delay for the cascaded system: Total delay = Propagation delay + Transmission line delay IDT7381 16-BIT CASCADABLE ALU COMMERCIAL TEMPERATURE RANGE A 16 - 31 G B 16 - 31 A 0 - 15 B 0 - 15 11 RS 0 - 1 ID T7381 ID T7381 P Clk, I 0 -2 , ENA, ENB ENF, FTF, FTAB C 16 MSD C 16 C0 LSD Z F 16 - 3 1 F 0 - 15 C0 OVF Z Z C IN Figure 1. Cascading Two IDT7381s to 32 Bits A 32 - 47 G B 32 - 47 A 16 - 31 A 0 - 15 ID T7381 ID T73 81 P B 16 - 31 B 0 - 15 11 ID T7381 C 16 OVF Z C 16 C0 Z MSD C 16 C0 LS D Z C0 Z F 32 - 4 7 F 16 - 3 1 RS0 -1 C lk, I 0 - 2 , EN A, EN B EN F, FTF, FTA B C IN F 0 - 15 Figure 2. Cascading Three IDT7381s to 48 Bits Wide without a Carry-lookahead Generator A 32 G B 32 - 47 - 47 A 16 B 16 A 0 - 15 - 31 ID T7381 ID T7381 P - 31 B 0 - 15 11 ID T7381 C 16 OVF P G Z Z C0 C0 LS D MSD F 32 F 16 -4 7 C n+y EN A, EN B EN F, FTF, FTA B P G Z C0 Z RS0 -1 C lk, I 0 - 2 , F 0 - 15 -3 1 P1 G1 C n+x FC T182/A Looka he ad G ene rator P0 G0 Cn Figure 3. Cascading Three IDT7381s to 48 Bits Wide with a Carry-lookahead Generator 12 C IN IDT7381 16-BIT CASCADABLE ALU COMMERCIAL TEMPERATURE RANGE B 16 - 31 16 A 16 - 31 16 A M ux B M ux R M ux B Reg A Reg B Reg A Reg B 0 - 15 16 A 0 - 15 16 A M ux S M ux B M ux R M ux 16-Bit ALU CLK S M ux 16-Bit ALU C C 16 0 M SD LSD F Reg F Reg F M ux F M ux 16 16 F 0 - 15 F 16 - 3 1 Figure 4. 32-Bit Configuration for FTAB = 0, FTF = 0 B 16 - 31 A 16 - 31 16 16 B Reg A Reg A M ux B Reg A Reg B M ux R M ux B 0 - 15 16 A 0 - 15 16 A M ux S M ux S M ux R M ux 16-Bit ALU M SD B M ux 16-Bit ALU C C 16 0 F M ux LSD F M ux 16 16 F 16 - 3 1 F 0 - 15 Figure 5. 32-Bit Configuration for FTAB = 0, FTF = 1 13 CLK IDT7381 16-BIT CASCADABLE ALU COMMERCIAL TEMPERATURE RANGE A 16 - 31 16 A 0 - 15 16 B 16 - 31 16 B 0 - 15 16 CLK A M ux B M ux R M ux A M ux S M ux B M ux R M ux 16-Bit ALU S M ux 16-Bit ALU C C 16 0 M SD LSD F Reg F Reg F M ux F M ux 16 16 F 0 - 15 F 16 - 3 1 Figure 6. 32-Bit Configuration for FTAB = 1, FTF = 0 A 16 - 31 B 16 - 31 16 A 0 - 15 16 A M ux B M ux R M ux B 0 - 15 16 16 A M ux B M ux S M ux R M ux C C 16 16-Bit ALU S M ux 16-Bit ALU 0 M SD LSD F M ux F M ux 16 16 F 16 - 3 1 F 0 - 15 Figure 7. 32-Bit Configuration for FTAB = 1, FTF = 1 14 IDT7381 16-BIT CASCADABLE ALU COMMERCIAL TEMPERATURE RANGE D0 L1 D1 L2 In Dn — t1 — OU TPUT — t2 — — tn — Figure 8. Propagation Delay = t1 + t2 + . . . + tn N-Cascaded Devices AC TEST CONDITIONS Input Rise levels GND to 3V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load Figure 1 15 IN PUT IDT7381 16-BIT CASCADABLE ALU COMMERCIAL TEMPERATURE RANGE TEST WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS SWITCH POSITION Test Open Drain V CC 7.0V Disable Low All Other Tests V OUT V IN 50pF T C 500 Ω L SET-UP, HOLD, AND RELEASE TIMES DATA INPUT tH t SU TIM ING INPUT ASYNCHRONOUS CONTROL PRES ET CLEA R ETC. SYNCHRONOUS CONTROL PRES ET CLEA R CLOCK ENABLE ETC. t REM t SU Open DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. D.U.T. R Closed Enable Low 500 Ω Pulse Generator Switch 3V 1.5V 0V 3V 1.5V 0V PULSE WIDTH LOW -HIGH-LOW PULS E 1.5V tW 3V 1.5V 0V HIGH-LOW -HIGH PULS E 1.5V 3V 1.5V 0V tH ENABLE AND DISABLE TIMES PROPAGATION DELAY ENAB LE 3V 1.5V SAM E PHA SE INPUT TRANSITION t PLH t PHL OUTPUT t PLH OPPOS ITE PHASE INPUT TRANSITION t PHL DISABLE 3V CONTROL INPUT 0V 1.5V OUTPUT NORMA LLY LOW 3V SW ITCH CLOSE D 3.5V 1.5V OUTPUT NORMA LLY HIGH SW ITCH OPEN 3.5V 0.3V t PZH 1.5V 0V 0V t PLZ t PZL V OH 1.5V V OL V OL t PHZ 0.3V V OH 1.5V 0V 0V NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns 16 IDT7381 16-BIT CASCADABLE ALU COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXX Device Type XX Speed X Package CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 J Plastic Leaded Chip C arrier (J68-1) 25 30 40 55 Speed Grade 7381L 16-Bit ALU for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc. 17