IDT74FST3244 IDT74FST32244 PRELIMINARY OCTAL BUS SWITCH Integrated Device Technology, Inc. FEATURES: The FST3244/32244 belong to IDT's family of Bus switches. Bus switch devices perform the function of connecting or isolating two ports without providing any inherent current sink or source capability. Thus they generate little or no noise of their own while providing a low resistance path for an external driver. These devices connect input and output ports through an n-channel FET. When the gate-to-source junction of this FET is adequately forward-biased the device conducts or the resistance between input and output ports is small. Without adequate bias on the gate-to-source junction of the FET, the FET is turned off, therefore with no VCC applied, the device has hot insertion capability. The low on-resistance and simplicity of the connection between input and output ports reduces the delay in this path to close to zero. The FST32244 integrates terminating resistors in the device, thus eliminating the need for external 25Ω series resistors. The FST3244 and FST32244 are octal TTL-compatible bus switches. The OE pins provide output enable control for all 8 bits. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION • Bus switches provide zero delay paths • Extended commercial range of –40°C to +85°C • Low switch on-resistance: FST3xxx – 5Ω FST32xxx – 28Ω • TTL-compatible input and output levels • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • Available in QSOP, TSSOP, SOIC and PDIP • Pin-compatible with FCT244/FCT244T DESCRIPTION: OEA OEA 1 20 Vcc OA1 DA0 2 19 OEB DA2 OA2 OB0 3 18 OA0 DA3 OA3 DA1 4 17 DB0 OB1 5 16 OA1 15 DB1 DA0 OA0 DA1 OEB P20-1 SO20-2 SO20-8 SO20-9 DB0 OB0 DA2 6 DB1 OB1 OB2 7 14 OA2 DB2 OB2 DA3 8 13 DB2 DB3 OB3 OB3 9 12 OA3 GND 10 11 DB3 3255 drw 01 PIN DESCRIPTION Pin Names OEA, OEB Description Output Enable Inputs (Active LOW) DA0-3, OA0-3 A Port Bits DB0-3, OB0-3 B Port Bits DIP/SOIC/ QSOP/TSSOP TOP VIEW 3255 drw 02 3255 tbl 03 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGES 1996 Integrated Device Technology, Inc. AUGUST 1996 10.1 DSC-3255/3 1 IDT74FST3244, IDT74FST32244 OCTAL BUS SWITCH COMMERCIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS(1) Symbol Description VTERM(2) Terminal Voltage with Respect to GND TSTG Storage Temperature I OUT FUNCTION TABLE Unit V OEA OEB H –65 to +150 °C L 128 mA Max. –0.5 to +7.0 Maximum Continuous Channel Current 3255 tbl 02 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condiitions for extended periods may affect reliability. 2. VCC, Control and Switch terminals. H OA Hi-Z OB Hi-Z Description Disconnect H DA Hi-Z Connect H L Hi-Z DB Connect L L DA DB Connect 3255 tbl 03 NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care CAPACITANCE(1) Symbol Conditions(2) Typ. Unit Parameter CIN Control Input Capacitance CI/O Switch Input/Output Capacitance 4 Switch Off pF pF 3255 tbl 04 NOTES: 1. Capacitance is characterized but not tested 2. TA = 25°C, f = 1MHz, VIN = 0V, VOUT = 0V DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = –40°C to +85°C, VCC = 5.0V ±5% Parameter Input HIGH Voltage Test Conditions(1) Guaranteed Logic HIGH for Control Inputs Min. 2.0 Typ.(2) — Max. — Unit V VIL Input LOW Voltage Guaranteed Logic LOW for Control Inputs — — 0.8 V II H Input HIGH Current VCC = Max. VI = VCC — — ±1 µA II L Input LOW Voltage VI = GND — — ±1 I OZH High Impedance Output Current VCC = Max. VO = V CC — — ±1 I OZL (3-State Output pins) VO = GND — — ±1 Symbol VIH GND(3) µA I OS Short Circuit Current VCC = Max., VO = — 300 — mA VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V VCC = Min. VIN = 0.0V — 5 7 Ω RON Switch On Resistance(4) 3xxx I ON = 30mA 32xxx 17 28 40 VCC = Min. VIN = 2.4V 3xxx — 10 15 I ON = 15mA 32xxx 20 35 48 Ω I OFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 4.5V — — ±1 µA I CC Quiescent Power Supply Current VCC = Max., V I = GND or VCC — 0.1 3 µA NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. Measured by voltage drop between ports at indicated current through the switch. 10.1 3255 lnk 05 2 IDT74FST3244, IDT74FST32244 OCTAL BUS SWITCH COMMERCIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS Symbol ∆ICC ICCD IC Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Total Power Supply Current (6) Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open Enable Pin Toggling 50% Duty Cycle VCC = Max. Outputs Open Enable Pin Toggling (4 Switches Toggling) fi = 10MHz 50% Duty Cycle Min. — Typ.(2) 0.5 Max. 1.5 Unit mA VIN = VCC VIN = GND — 30 40 µA/ MHz/ Switch VIN = VCC VIN = GND — 1.2 1.6 mA VIN = 3.4 VIN = GND — 1.5 2.4 NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fiN) ICC = Quiescent Current ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fi = Input Frequency N = Number of Switches Toggling at fi All currents are in milliamps and all frequencies are in megahertz. 3255 tbl 06 SWITCHING CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = –40°C to +85°C, VCC = 5.0V ±5% 3244 Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ |QCI| Description Data Propagation Delay DA, DB to OA, OB OA, OB to DA, DB (3,4) Switch Turn on Delay OEA to DA, OA, OEB to DB, OB Switch Turn off Delay OEA to DA, OA, OEB to DB, OB(3) Charge Injection (5,6) Condition(1) CL = 50pF RL = 500Ω 32244 Min.(2) — Typ. — 0.25 1.25 Unit ns 1.5 — 6.5 7.5 ns 1.5 — 5.5 5.5 ns — 1.5 — — Max. pC 3255 tbl 07 NOTES: 1. See test circuit and waveforms. 2. Minimum limits guaranteed but not tested. 3. This parameter is guaranteed by design but not tested. 4. The bus switch contributes no propagation delay other than the RC delay of the on resistance of the switch and the load capacitance. The time constant for the switch alone is of the order of 0.25 ns for 50 pF load. Since this time is constant and much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay of the bus switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 5. Measured at switch turn off, load = 50 pF in parallel with 10 MΩ scope probe, VIN = 0.0 volts. 6. Characterized parameter. Not 100% tested. 10.1 3 IDT74FST3244, IDT74FST32244 OCTAL BUS SWITCH COMMERCIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS V CC SWITCH POSITION 500Ω V OUT VIN Pulse Generator Test Switch Open Drain Disable Low Closed 7.0V Enable Low D.U.T. Open All Other Tests 50pF RT 3255 lnk 08 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 500Ω CL 3255 lnk 03 SET-UP, HOLD AND RELEASE TIMES DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tH tSU tREM tSU PULSE WIDTH 3V 1.5V 0V 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW 3V 1.5V 0V HIGH-LOW-HIGH PULSE 1.5V 3V 1.5V 0V tH 3255 lnk 05 3255 lnk 04 ENABLE AND DISABLE TIMES PROPAGATION DELAY ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V VOH 1.5V VOL DISABLE 3V 1.5V 0V CONTROL INPUT tPZL OUTPUT NORMALLY LOW 3V 1.5V 0V SWITCH CLOSED tPLZ tPZH OUTPUT NORMALLY HIGH 3255 lnk 06 SWITCH OPEN 3.5V 3.5V 1.5V 0.3V VOL tPHZ 0.3V VOH 1.5V 0V 0V 3255 lnk 07 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns 10.1 4 IDT74FST3244, IDT74FST32244 OCTAL BUS SWITCH COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XX FST XX Temp. Range Device Type X Package P SO Q PG Plastic DIP (P20-1) Small Outline IC (SO20-2) Quarter-size Small Outline Package (SO20-8) Thin Shrink Small Outline Package (SO20-9) 3244 32244 Octal Bus Switch 74 –40°C to +85°C 3255 drw 08 10.1 5