LXT914 Flexible Quad Ethernet Repeater Datasheet The LXT914 is an integrated multi-port repeater designed for mixed-media networks. It provides all the active circuitry required for the repeater function in a single CMOS device. It includes one Attachment Unit Interface (AUI) port and four 10BASE-T transceivers. The AUI port is mode selectable: DTE mode allows connection of an external transceiver (10BASE2, 10BASE5, 10BASE-T or FOIRL) or a drop cable. MAU mode creates a MAU output allowing direct connection to another DTE interface. The 10BASE-T transceivers are entirely selfcontained with internal filters which simplify the design work required for FCC-compliant EMI performance. An inter-repeater backplane interface allows 128 or more 10BASE-T ports to be cascaded together. In addition, a serial port provides information for network management. The LXT914 requires only a single 5-volt power supply due to an advanced CMOS fabrication process. Product Features ■ ■ ■ ■ ■ ■ ■ Four integrated 10BASE-T transceivers and one AUI transceiver on a single chip Programmable DTE/MAU interface on AUI port Seven integrated LED drivers with four unique operational modes On-chip transmit and receive filtering Automatic partitioning of faulty ports, enabled on an individual port basis Automatic polarity detection and correction Programmable squelch level allows extended range in low-noise environments ■ Synchronous or asynchronous interrepeater backplane supports “hot swapping” Inter-repeater backplane allows cascaded repeaters, linking 128 or more 10BASE-T ports Serial port for selecting programmable options 68-pin PLCC (Commercial or Extended temp range) 100-pin PQFP (Commercial temp range) ■ Switched Repeater Clusters ■ ■ ■ ■ Applications ■ ■ LAN Repeaters Integrated Repeaters As of January 15, 2001, this document replaces the Level One document known as Flexible Quad Ethernet Repeater. Order Number: 248989-001 January 2001 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT914 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners. Datasheet Flexible Quad Ethernet Repeater — LXT914 Contents 1.0 LXT914 Pin Assignments and Signal Descriptions ..................................... 7 2.0 Functional Description...........................................................................................14 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 Introduction..........................................................................................................14 External Interfaces ..............................................................................................14 2.2.1 10BASE-T Ports .....................................................................................14 2.2.2 AUI Port..................................................................................................14 2.2.3 Serial Port...............................................................................................15 2.2.4 Inter-Repeater Backplane ......................................................................15 2.2.4.1 Synchronous IRB Operation......................................................15 2.2.4.2 Asynchronous IRB Operation ....................................................15 Internal Repeater Circuitry ..................................................................................16 Initialization..........................................................................................................16 2.4.1 Local Management Mode Initialization ...................................................16 2.4.2 External Management Mode Initialization ..............................................20 10BASE-T Port Operation ...................................................................................21 2.5.1 10BASE-T Reception .............................................................................21 2.5.1.1 Programmable Internal Squelch Level ......................................22 2.5.1.2 Polarity Detection and Correction..............................................22 2.5.2 10BASE-T Transmission ........................................................................22 2.5.3 10BASE-T Link Integrity Testing ............................................................22 AUI Port Operation ..............................................................................................23 2.6.1 AUI Reception ........................................................................................23 2.6.2 AUI Transmission ...................................................................................23 2.6.3 AUI Mode Selection (DTE/MAU) ............................................................23 Collision Handling................................................................................................24 Security Mode .....................................................................................................24 LED Display.........................................................................................................25 Application Information .........................................................................................28 3.1 3.2 12-Port Hub Repeater .........................................................................................28 8-Port Print or File Server....................................................................................28 4.0 Test Specifications ..................................................................................................36 5.0 Mechanical Specifications....................................................................................41 Datasheet 3 LXT914 — Flexible Quad Ethernet Repeater Figures 1 2 3 4 5 6 7 8 9 10 11 LXT914 Block Diagram ......................................................................................... 7 LXT914 Pin Assignments...................................................................................... 8 Global State Machine.......................................................................................... 18 Partitioning State Machine .................................................................................. 19 Integrated LED Driver Indications ....................................................................... 27 12-Port Application Schematic, 68-Pin PLCC Package ...................................... 30 8-Port Application Schematic, LED Mode 1 with AUISEL = MAU....................... 34 Serial Port Timing................................................................................................ 39 Inter-Repeater Bus Timing .................................................................................. 40 LXT914PC/PE Package Specifications............................................................... 41 LXT914QC Package Specifications .................................................................... 42 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 LXT914 Power, Ground and Clock Signal Descriptions........................................ 9 LXT914 Inter-Repeater Backplane Signal Descriptions...................................... 10 LXT914 Mode Select and Control Signal Descriptions ....................................... 10 LXT914 Serial Port Signal Descriptions (External Management Mode) ............. 11 LXT914 Serial Port Signal Descriptions (Local Management Mode) .................. 11 LXT914 Miscellaneous Control Signal Descriptions ........................................... 12 LXT914 LED Driver Signal Descriptions ............................................................. 12 LXT914 Repeater Port Signal Descriptions ........................................................ 13 Setup Register Bit Assignments.......................................................................... 20 Setup Register Bit Definitions ............................................................................. 20 Packet Status Register Bit Assignments............................................................. 21 Packet Status Register Bit Definitions................................................................. 21 AUI Mode Selection (DTE/MAU) ......................................................................... 23 LED Mode Selection ........................................................................................... 25 Mode 0 (Default) LED Truth Table ...................................................................... 25 Mode 1 LED Truth Table..................................................................................... 26 Mode 2 LED Truth Table..................................................................................... 26 Mode 3 LED Truth Table..................................................................................... 26 Manufacturers Magnetics List ............................................................................. 29 Absolute Maximum Ratings ................................................................................ 36 Recommended Operating Conditions ................................................................. 36 I/O Electrical Characteristics1 (over recommended range) ................................. 36 AUI Electrical Characteristics (over recommended range) ................................. 37 Twisted-Pair Electrical Characteristics (over recommended range) ................... 37 IRB Electrical Characteristics (over recommended range) ................................. 38 Switching Characteristics (over recommended range) ....................................... 38 Serial Port Timing—External Mode (over recommended range) ........................ 38 Inter-Repeater Bus Timing (over recommended range) ..................................... 39 Tables 4 Datasheet Flexible Quad Ethernet Repeater — LXT914 Revision History Revision Datasheet Date Description 5 Flexible Quad Ethernet Repeater — LXT914 1.0 LXT914 Pin Assignments and Signal Descriptions Figure 1. LXT914 Block Diagram FPS/SECAUI LOC/EXT A/SYNC DOP DON DIP DIN DO/DI DO/DI DO/DI DOP DON DIP DIN CIP CIN AUISEL* Datasheet 4 4 4 Filter RESET SYSCLK Twisted-Pair Port #1 F F F TP Port #2 TP Port #3 TP Port #4 Control Management Port (Serial I/F) Repeater (State Machine, Timing Recovery, FIFO, etc.) Inter-Repeater Backplane Port AUI Port (Mode selectable DTE/MAU) * The AUI Select function is provided on a dedicated AUISEL pin in the 100-pin PQFP (LXT914QC). In the 68-pin PLCC (LXT914PC/PE) the AUI Select function is provided through shared usage of the JM LED pin. SENI SENO SDI SDO SCLK IRENA IRDEN IRCFS IRCOL IRDAT BCLKIO 4 LED Drivers TP1 - 4 AUI CF JM 7 LXT914 — Flexible Quad Ethernet Repeater GND1 IRCOL IRCFS IRDEN IRDAT IRENA VCC3 VCC2 VCC1 VCC8 VCC7 TPDIP1 TPDIN1 TPDIP2 TPDIN2 TPDIP3 TPDIN3 Figure 2. LXT914 Pin Assignments 9 8 7 6 5 4 3 2 1 68 6766 65 6463 62 61 60 10 59 11 58 12 57 13 56 14 55 15 54 16 53 17 Rev # 52 18 51 19 50 20 Part # LXT914PC/PE XX 49 21 LOT # XXXXXX 48 22 FPO # XXXXXXXX 47 23 46 24 45 25 44 26 27 2829 303132 33343536 3738 39 4041 42 43 LXT914PC/PE TPDIP4 TPDIN4 GND8 TPDON1 TPDOP1 VCC6 TPDOP2 TPDON2 GND7 TPDON3 TPDOP3 VCC5 TPDOP4 TPDON4 GND6 AUICIN AUICIP FPS/SECAUI SECTP4 SECTP3 LEDCF SECTP2 LEDJM/AUISEL SECTP1/DSQE LEDTP1 n/c LEDTP2 RESET LEDTP3 TEST n/c LEDTP4 SCLK/SCLKIO LEDAUI n/c GND2 RTS/SDO/LEDMO LEDM1 SDI GND3 SENO RBIAS SENI/CS GND4 n/c GND5 LOC/EXT A/SYNC AUIDOP n/c AUIDON SYSCLK AUIDIP n/c AUIDIN BCLKIO n/c n/c n/c AUISEL n/c n/c VCC1 n/c BCLKIO SYSCLK A/SYNC LOC/EXT CS/SENI SENO SDI LEDMO/SDO/RTS SCLK/SCLKIO TEST RESET DSQE/SECTP1 SECTP2 SECTP3 SECTP4 FPS/SECAUI VCC4 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Part # LOT # FPO # n/c n/c n/c AUICIP AUICIN n/c AUIDIP AUIDIN n/c LXT914QC 8 LXT914QC XX XXXXXX XXXXXXXX Rev # 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 n/c GND9 IRCOL IRCFS IRDEN IRDAT IRENA VCC10 n/c VCC9 VCC8 VCC7 VCC6 TPDIP1 TPDIN1 TPDIP2 TPDIN2 TPDIP3 TPDIN3 n/c n/c n/c TPDIN4 TPDIP4 n/c n/c n/c LEDTP3 LEDTP4 LEDAUI GND1 LEDM1 GND2 RBIAS GND3 GND4 n/c AUIDOP AUIDON 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 n/c GND5 TPDON4 TPDOP4 VCC2 VCC3 TPDOP3 TPDON3 GND6 GND7 TPDON2 TPDOP2 VCC4 VCC5 TPDOP1 TPDON1 GND8 n/c LEDCF LEDJM/AUISEL LEDTP1 LEDTP2 Datasheet Flexible Quad Ethernet Repeater — LXT914 Table 1. LXT914 Power, Ground and Clock Signal Descriptions Pin # Datasheet Symbol I/O 27 VCC1 — 61 VCC2 — 3 62 VCC3 — 26 69 VCC4 — 49 70 VCC5 — 55 88 VCC6 — 67 89 VCC7 — 68 90 VCC8 — — 91 VCC9 — — 93 VCC10 — PLCC PQFP 1 2 Description Power Supply Inputs. These pins each require a +5 VDC power supply. The various pins may be supplied from a single power source, but special de-coupling requirements may apply. Each VCC input must be within ±0.3 V of every other VCC input. 9 39 GND1 — 34 41 GND2 — 36 43 GND3 — 38 44 GND4 — 39 58 GND5 — 46 65 GND6 — 52 66 GND7 — 58 73 GND8 — — 99 GND9 — 37 42 RBIAS — Bias. This pin provides bias current for the internal circuitry. The 100 µA bias current is provided through an external 12.4 kΩ resistor to ground. Backplane Clock. This 10 MHz clock synchronizes multiple repeaters on a common backplane. In the synchronous mode, BCLKIO must be supplied to all repeaters from a common external source. In the asynchronous mode, BCLKIO is supplied only when a repeater is outputting data to the bus. Each repeater outputs its internally recovered clock when it takes control of the bus. Other repeaters on the backplane then sync to BCLKIO for the duration of the transmission. 10 4 BCLKIO I/O 11 6 SYSCLK I Ground. These pins provide ground return paths for the various power supply pins. System Clock. The required 20 MHz system clock is input at this pin. Clock must have a 40-60 duty cycle with < 10 ns rise time. 9 LXT914 — Flexible Quad Ethernet Repeater Table 2. LXT914 Inter-Repeater Backplane Signal Descriptions PLCC PQFP Symbol I/O Description 4 94 IRENA I/O Inter-Repeater Backplane Enable. This pin allows individual LXT914 repeaters to take control of the Inter-Repeater Backplane (IRB) data bus (IRDAT). The IRENA bus must be pulled up locally by a 330 Ω resistor.1 5 95 IRDAT I/O IRB Data. This pin is used to pass data between multiple repeaters on the IRB. The IRDAT bus must be pulled up locally by a 330 Ω resistor.1 6 96 IRDEN O IRB Driver Enable. The IRDEN pin is used to enable external bus drivers which may be required in synchronous systems with large backplanes. This is an active Low signal, maintained for the duration of the data transmission. IRDEN must be pulled up locally by a 330 Ω resistor. 7 97 IRCFS I/O 8 98 IRCOL I/O IRB Collision Flag Sense (IRCFS) and IRB Collision (IRCOL). These two pins are used for collision signalling between multiple LXT914 devices on the Inter-Repeater Backplane (IRB). Both the IRCFS bus and the IRCOL bus must be pulled up globally with 330 Ω resistors. (IRCFS requires a precision resistor [±1%].)2 NOTES: 1. IRENA and IRDAT can be buffered between boards in multi-board configurations. Where buffering is used, a 330 Ω pull-up resistor can be used on each signal, on each board. Where no buffering is used, the total impedance should be no less than 330 Ω. 2. IRCFS and IRCOL cannot be buffered. In multi-board configurations, the total impedance on IRCOL should be no smaller than 330 Ω. IRCFS should be pulled up only once, by a single 330 Ω, 1% resistor. Table 3. LXT914 Mode Select and Control Signal Descriptions PLCC 12 13 10 PQFP 8 9 Symbol A/SYNC LOC/EXT I/O Description I Backplane Sync Mode Select. This pin selects the backplane sync mode. When this pin is left floating an internal pull-up defaults to the Asynchronous mode (A/SYNC High). In the asynchronous mode 12 or more LXT914s can be connected on the backplane, and an external 10 MHz backplane clock source is not required. When the synchronous mode is selected (A/SYNC tied Low), 32 or more LXT914s can be connected to the backplane and an external 10 MHz backplane clock source is required. I Management Mode Select. This pin selects the management mode. When this pin is left floating, an internal pull-up defaults to the Local management mode (LOC/EXT High). In the Local mode, setup parameters are downloaded from an EEPROM during initialization. Once initialized with the setup parameters, the repeater functions independently. 28 33 LEDJM/ AUISEL I/O LED Driver or DTE/MAU Select. At reset, this pin selects the mode of the AUI port. If left floating, an internal pull-down device forces the AUI port to DTE mode. If pulled High with an external resistor, the port changes to a MAU, in which case the functions of the LEDJM pin are disabled and the default LED mode (Refer to Table 7) is not available. — 30 AUISEL I DTE/MAU Select. This pin changes the mode of the AUI port independent of the condition at reset. This function is available only in the 100-pin PQFP package. 17 14 35 40 LEDM0 I/O LEDM1 I/O LED Mode 0 & 1 Select. These two pins select one of four possible LED modes of operation. The Functional Description section describes the four modes. Datasheet Flexible Quad Ethernet Repeater — LXT914 Table 4. LXT914 Serial Port Signal Descriptions (External Management Mode) PLCC 14 Table 5. 11 Symbol SENI I/O Description I Serial Enable Input. This active Low input is used to access the LXT914 serial interface. To write to the serial input (SDI), an External Management Device (EMD) must drive this pin from High to Low. The input must be asserted Low concurrent with the appearance of data on SDI and remain Low for the duration of the serial input transaction. 15 12 SENO O Serial Enable Output. This active Low output is used to access the serial interface of an EMD. When the LXT914 sends a data stream to the EMD through the serial port (SDO), this output transitions from High to Low and remains Low for the duration of the serial transmission. 16 13 SDI I Serial Data Input. This pin is the input for the EMD serial interface. Setup and operating parameters are supplied to the LXT914 in a serial data stream through this port when operating in the External Management Mode. 17 14 SDO I/O Serial Data Output. After each packet transmission or interrupt event, the LXT914 reports status information to the EMD in a serial data stream through this port. 18 16 SCLK I Serial Clock. This 10 MHz clock synchronizes the serial interface between the LXT914 and the EMD. Both devices must be supplied from the same clock source. In synchronous mode, SCLK and BCLK may be tied together. LXT914 Serial Port Signal Descriptions (Local Management Mode) PLCC 14 Datasheet PQFP PQFP Symbol I/O Description CS O Chip Select. The LXT914 is designed for use with an EEPROM or similar device which may be used to store setup parameters and serially download them to the LXT914 during initialization. In a single-device application or in the first device of a daisy chain application, this pin is an active High Chip Select output used to enable the EEPROM. SENI I Serial Enable Input. In subsequent devices of a daisy-chain configuration, a High-to-Low transition on this pin enables the serial input port (SDI). The input must be asserted concurrent with the appearance of data on SDI and remain Low for the duration of the serial input transaction. 11 15 12 SENO O Serial Enable Output. During initialization, the LXT914 accepts 48 bits of setup data through the SDI port. After the 48th bit, the LXT914 asserts this pin Low. When multiple LXT914 devices are connected in a daisy-chain, this output is tied to the SENI input of the next device in the chain. Thus each device in the chain is serially enabled by the previous device until all the devices have read in their 48 bits of setup data. 16 13 SDI I Setup Data Input. This pin is the serial input port for the setup parameters (48 bits).This pin should be tied Low if no EEPROM is present. 17 14 RTS I/O Request To Send. In a single-device application or in the first device of a daisy chain application, this pin outputs a 9-bit, active High sequence. This pin must be tied to the EEPROM DI input to trigger the EEPROM to download its stored data. In subsequent devices this pin is not used. 18 16 SCLKIO I/O Serial Clock. A 1 MHz clock provided by the first LXT914 in the chain to all subsequent repeaters and the EEPROM. In the Local mode all repeaters have their SCLKIO pins tied together. 11 LXT914 — Flexible Quad Ethernet Repeater Table 6. LXT914 Miscellaneous Control Signal Descriptions PLCC I/O Description 18 TEST I Test Mode Select. This pin must be tied Low for normal operation. 20 19 RESET I RESET. This pin resets the LXT914 circuitry when pulled High for ≥ 1 ms. DSQE (Local) I DSQE. In Local Mode, this pin controls the SQE function. When High, the SQE function of the AUI port is disabled. When Low, SQE is enabled. SECTP1 (External) I Security Mode Select (TP Port 1). In External Mode, this pin enables the security mode for twisted-pair port 1. When pulled High, the LXT914 Jams the port. This pin must be tied Low if external security control is not required. SECTP2 SECTP3 SECTP4 (External) I I I Security Mode Select (TP Ports 2–4). In External Mode, these pins enable the security mode for the respective twisted-pair ports (TP1 through TP4). When pulled High, the LXT914 jams the affected port. The SEC pins must be tied Low if external security control is not required. FPS (Local) I First Position Select. In the Local mode this pin identifies the first device in a daisy chain configuration. When tied High (First position), the LXT914 controls the local EEPROM by providing clock and handshaking. When tied Low (Not First), the LXT914 will accept CLK and data in its turn from previous LXT914s in the data chain. SECAUI (External) I Security Mode Select (AUI Port). In the External mode this pin enables the security mode for the AUI port. When pulled High, the LXT914 jams the AUI port. The security feature is available only in External management mode. 22 23 24 25 21 22 23 24 25 LXT914 LED Driver Signal Descriptions PLCC 27 PQFP 32 Symbol LEDCF I/O Description O Collision & FIFO Error LED Driver. This tri-state LED driver pin reports collisions and FIFO errors. It pulses Low to report collisions, and pulses High to report FIFO errors. When this pin is connected to the anode of one LED and to the cathode of a second LED, the LXT914 will simultaneously monitor and report both conditions independently. Jabber/MJLP & Manchester Code Violation LED Driver. This tri-state LED driver pin reports jabber and code violations. It pulses Low to report MAU Jabber Lockup Protection (MJLP), and pulses High to report Manchester code violations. When this pin is connected to the anode of one LED and to the cathode of a second LED, the LXT914 will simultaneously monitor and report both conditions independently. 28 33 LEDJM O 29 34 LEDTP1 O 30 35 LEDTP2 O 31 36 LEDTP3 O 32 37 LEDTP4 O 33 12 Symbol 19 21 Table 7. PQFP 38 LEDAUI O Twisted-Pair Port LED Drivers. These tri-state LED drivers use an alternating pulsed output to report TP port status. Each pin should be tied to a pair of LEDs (to the anode of one LED and the cathode of a second LED). When connected this way, each pin reports five separate conditions (receive, transmit, link integrity, reverse polarity and auto partition). AUI Port LED Driver. This tri-state LED driver uses an alternating pulsed output to report AUI port status. This pin should be tied to a pair of LEDs (to the anode of one LED and the cathode of a second LED). When connected this way, this pin reports five separate conditions (receive, transmit, receive jabber, receive collision and auto partition. Datasheet Flexible Quad Ethernet Repeater — LXT914 Table 8. Datasheet LXT914 Repeater Port Signal Descriptions PLCC PQFP Symbol I/O 40 41 46 AUIDOP O 47 AUIDON O 42 48 AUIDIP I 43 49 AUIDIN I 44 54 AUICIP I/O 45 55 AUICIN I/O 56 57 71 72 TPDOP1 TPDON1 O O 54 53 68 67 TPDOP2 TPDON2 O O 50 51 63 64 TPDOP3 TPDON3 O O 48 47 60 59 TPDOP4 TPDON4 O O 66 65 87 86 TPDIP1 TPDIN1 I I 64 63 85 84 TPDIP2 TPDIN2 I I 62 61 83 82 TPDIP3 TPDIN3 I I 60 59 77 76 TPDIP4 TPDIN4 I I Description AUI Data Outputs (Positive and Negative). These pins are the positive and negative data outputs for the AUI Port. In MAU Mode these pins are connected to the DI pins of the DTE. AUI Data Input (Positive and Negative). These pins are the positive and negative data inputs for the AUI Port. In MAU Mode, these pins are connected to the DO pins of the DTE. AUI Collision (Positive and Negative). These pins are the positive and negative Collision inputs for the AUI Port in DTE Mode. In MAU Mode, these pins output a collision indication to the DTE. Twisted-Pair Data Outputs (Positive and Negative). These pins are the positive (TPDOP1-4) and negative (TPDON1-4) outputs to the network from the respective twisted-pair ports. Twisted-Pair Data Inputs (Positive and Negative). These pins are the positive (TPDIP1-4) and negative (TPDIN1-4) inputs from the network to the respective twisted-pair ports. 13 LXT914 — Flexible Quad Ethernet Repeater 2.0 Functional Description 2.1 Introduction The LXT914 is an integrated hub repeater for 10BASE-T networks. The hub repeater is the central point for information transfer across the network. The LXT914 offers multiple operating modes to suit a broad range of applications ranging from simple 4-port stand-alone hubs or attachments for print and file servers, up to intelligent 128-port enterprise systems with microprocessor/gate array management. The main functions of the LXT914 hub repeater are data recovery and re-transmission and collision propagation. Data packets received at the AUI or 10BASE-T ports are detected and recovered by the port receivers before being passed to the repeater core circuitry for re-timing and re-transmission. Data packets received through the IRB port are essentially passed directly to the core for retransmission. After recovery of a valid data packet, the repeater broadcasts it to all enabled stations, except the originator station. 2.2 External Interfaces The LXT914 includes four 10BASE-T ports with internal filters. The LXT914 also includes an Attachment Unit Interface (AUI) port, a serial port and an Inter-Repeater Backplane (IRB) port. The serial port allows an external device such as an EEPROM to download setup parameters to the repeater. In more complex designs the serial port can also be used to monitor repeater status. The IRB port enables multiple LXT914 devices to be cascaded, creating a large, multi-port repeater. 2.2.1 10BASE-T Ports The four 10BASE-T transceiver ports are completely self-contained. Since the transmitters and receivers include the required filtering, only simple, inexpensive transformers are required to complete the 10BASE-T interface. Each individual Twisted-Pair (TP) port is implemented in accordance with the IEEE 802.3 10BASE-T standard. 2.2.2 AUI Port The AUI port mode is selectable (DTE mode or MAU mode). With DTE mode selected, the AUI port allows connection of an external transceiver (10BASE2, 10BASE5, 10BASE-T or FOIRL) or a drop cable. With MAU mode selected, the AUI port establishes a MAU output allowing direct connection to another DTE interface. 14 Datasheet Flexible Quad Ethernet Repeater — LXT914 2.2.3 Serial Port The serial port provides the management interface to the LXT914. Refer to Test Specifications for serial port timing. The serial port can be either unidirectional or bidirectional, depending on the management mode selected. In the Local management mode the serial port is unidirectional (input only), and is used only to download setup parameters during initialization. The Local mode is intended for use with a simple EEPROM, but the serial port may be tied Low if an EEPROM is not required. In the External management mode, the serial port is bi-directional (input for setup parameters, output for status reports). The External mode is intended for use with an External Management Device (EMD) and a Media Access Controller (MAC). The EMD (typically a gate array) communicates with a microprocessor (e.g., Intel 8051) and can control up to three LXT914 repeaters. This simplifies design of a relatively standard 12-port repeater on a single printed circuit board. 2.2.4 Inter-Repeater Backplane The Inter-Repeater Backplane (IRB) allows several LXT914s to function as a single repeater. Refer to Test Specifications for IRB timing. The IRB also allows several multi-repeater boards to be integrated in a standard rack and to function as a single unit. The IRB supports “hot swapping” for easy maintenance and troubleshooting. Each individual repeater distributes recovered and re-timed data to other repeaters on the IRB for broadcast on all ports simultaneously. This simultaneous rebroadcast allows the multi-repeater system to act as a single large repeater unit. The maximum number of repeaters on the IRB is limited by bus loading factors such as parasitic capacitance. The IRB can be operated synchronously or asynchronously. 2.2.4.1 Synchronous IRB Operation In the synchronous mode, a common external source provides the 10 MHz backplane clock (BCLKIO) and the 20 MHz system clock (SYSCLK) to all repeaters. BCLKIO must be synchronous to SYSCLK and may be derived from SYSCLK using a divide-by-two circuit. In the synchronous mode 32 or more LXT914 repeaters may be connected on the IRB, providing 128 10BASE-T ports and 32 AUI ports. 2.2.4.2 Asynchronous IRB Operation In the asynchronous mode an external BCLKIO source is not required. The repeaters run independently until one takes control of the IRB. The transmitting repeater then outputs its own 10 MHz clock onto the BCLKIO line. All other repeaters sync to that clock for the duration of the transmission. In the asynchronous mode 12 or more LXT914 devices may be connected to the IRB, providing 48 10BASE-T ports and 12 AUI ports. Note: Datasheet The maximum number of repeaters which may be linked on the backplane is limited by board design factors. The numbers listed above are engineering estimates only. Stronger drivers and reduced capacitive loading in PCB layout may allow an increased device count. 15 LXT914 — Flexible Quad Ethernet Repeater 2.3 Internal Repeater Circuitry The basic repeater circuitry is shared among all the ports within the LXT914. It consists of a global repeater state machine, several timers and counters and the timing recovery circuit. The timing recovery circuit includes a FIFO for re-timing and recovery of the clock which is used to clock the receive data out onto the IRB. The shared functional blocks of the LXT914 are controlled by the global state machine (Figure 3). This diagram and all associated notations used are in strict accordance with section 9.6 of the IEEE 802.3 standard. The LXT914 also implements the Partition State Diagram as defined by the IEEE 802.3 standard and shown in Figure 4. The value of CCLimit as implemented in the LXT914 is 64. The CCLimit value sets the number of consecutive collisions that must occur before the port is subjected to automatic partitioning. Auto-partition/re-connection is also supported by the LXT914 with Tw5 conforming to the standard requirement of 450 to 560 bit times. 2.4 Initialization The following description applies to the initial power-on reset and to any subsequent hardware reset. When a reset occurs (RESET pin pulled High for > 1 ms), the device senses the levels at the various control pins (see Table 3) to determine the correct operating modes for Management, LEDs, and the AUI port functions. 2.4.1 Local Management Mode Initialization An internal pull-up causes the LXT914 to default to the Local management mode unless the LOC/ EXT pin is tied Low. In the Local mode the serial port is a unidirectional interface used only to download setup parameters from an external device. In a Locally managed multiple-repeater (daisy chain) configuration, the first repeater in the chain performs special functions. The First Position Select (FPS) pin is used to establish position (FPS High = First, FPS Low = Not First). After establishing the Hardware mode, each LXT914 monitors the FPS pin to determine its position. If FPS is High (First Position), the repeater performs the following functions: 1. Outputs a 1 MHz Serial Clock (SCLK). SCLK is derived from the 20 MHz SYSCLK input in ASYNC mode and from BCLKIO in SYNC mode; it is supplied to the SCLK inputs of all other repeaters on the bus and to the EEPROM. 2. Asserts Chip Select (CS) High to enable the EEPROM. 3. Outputs a serial 9-bit request-to-send (RTS) strobe. The programmable device responds to the RTS strobe with a serial data stream containing the setup parameters for all repeaters in the chain. 4. Clocks the first 48 serial data input (SDI) bits from the EEPROM into its setup register. Refer to Table 9 and Table 10 for Setup Register bit assignments. 5. Asserts Serial Enable Output (SENO) Low to enable the next repeater in line. 16 Datasheet Flexible Quad Ethernet Repeater — LXT914 The second repeater has FPS tied Low and Serial Enable Input (SENI) connected to the Serial Enable Output (SENO) of the first repeater. When enabled by a Low on SENI, each repeater downloads its portion of the stream, then stops accepting data and asserts SENO Low. The SENO pin is linked to the SENI input of the next repeater. This enables the next repeater to clock in its 48bit word and so on. If FPS is Low (Not First Position), the repeater performs the following functions: 1. Syncs to the 1 MHz Serial Clock (SCLK) input. SCLK is supplied by the First Position repeater. 2. Responds to SENI Low by enabling the SDI port. 3. Clocks 48 bits from the EEPROM into its setup register through the SDI port. 4. Asserts SENO Low to enable the next repeater in line. Datasheet 17 LXT914 — Flexible Quad Ethernet Repeater Figure 3. Global State Machine Power On START Begin UCT IDLE Out (ALL) = Idle Collin(ANY) = SQE[NÁ Port(Collin = SQE)] Datain(ANY) = II * Collin(ALL) = SQE:[NÁ Port(Datain = II)] SEND PREAMBLE PATTERN Out (ALLXN) = Preamble Pattern Collin(ANYXN) = SQE Collin(N) = SQE + Datain(N) = II * Collin(ALL) = SQE TT(ALLXN) 62 * DataRdy * Collin(ALL) = SQE * Datain(N) = II SEND TWO ONES Out (ALLXN) = TwoOnes Collin(ANYXN) = SQE Collin(N) = SQE + Datain = II * Collin(ALL) = SQE TwoOnesSent * Collin(ALL) = SQE * Datain(N) = II SEND DATA Out (ALLXN) = Data Collin(N) = SQE + Datain(N) = II * Collin(ALL) = SQE * AllDataSent * TT(ANAYXN) < 96 Collin(ANYXN) = SQE TRANSMIT COLLISION RECEIVE COLLISION Out (All) = Jam Out (ALLXN) = Jam Collin(ALL) = SQE * TT(ALL) 96 * Tw2Done Collin(ONLY1) = SQE * TT(ALL) 96:[MÁ Port(Collin = SQE)] Collin(ANYXN) = SQE Datain(N) = II * Collin(ALL) = SQE * TT(ALLXN) 96 * AllDataSent Datain(N) = II * Collin(ALL) = SQE * TT(ALLXN) 96 * Tw2Done ONE PORT LEFT Out (ALLXM) = Jam Collin(ANYXM) = SQE Datain(M) = II* Collin(ALL) = SQE* Tw2Done WAIT StartTw1 Out(ALL) = Idle Collin(ANY) = SQE + Tw1Done 18 Datasheet Flexible Quad Ethernet Repeater — LXT914 Figure 4. Partitioning State Machine Begin COUNT CLEAR CC(X) = 0 Datain(X) = DIPresent(X) Collin(X) = CIPresent(X) DIPresent(X) = II * CIPresent(X) = SQE COLLISION COUNT IDLE Datain(X) = DIPresent(X) Collin(X) = CIPresent(X) PARTITION WAIT DIPresent(X) = II + CIPresent(X) = SQE Datain(X) = II Collin(X) = SQE WATCH FOR COLLISION StartTw5 Datain(X) = DIPresent(X) DIPresent(X) = II *CIPresent(X) = SQE Collin(X) = CIPresent(X) PARTITION HOLD Datain(X) = II Collin(X) = SQE DIPresent(X) = II * CIPresent(X) = SQE CIPresent(X) = SQE Tw5Done * DIPresent(X) = II * CIPresent(X) = SQE DIPresent(X) = II + CIPresent(X) = SQE COLLSION COUNT INCREMENT PARTITION COLLISION WATCH CC(X) = CC(X) + 1 Datain(X) = DIPresent(X) Datain(X) = II Collin(X) = SQE Collin(X) = CIPresent(X) StartTw6 StartTw5 CIPresent(X) = SQE DIPresent(X) = II CIPresent = SQE CC(X) ≥ CCLimit + (Tw6Done * CIPresent(X) = SQE) DIPresent(X) = II * CIPresent(X) = SQE * CC(X) < CCLimit * Tw6Done Tw5Done * DIPresent(X) = II * CIPresent(X) = SQE WAIT TO RESTORE PORT Datain(X) = II Collin(X) = SQE CC(X) = 0 DIPresent(X) = II * CIPresent (X) = SQE Datasheet 19 LXT914 — Flexible Quad Ethernet Repeater Table 9. Setup Register Bit Assignments Register D7 D6 D5 D4 D3 D2 D1 D0 SR(0) DISLI3 DISLI2 DISLI1 DISAP4 DISAP3 DISAP2 DISAP1 DISAPA SR(1) DISTX2 DISTX1 DISTXA DPRC4 DPRC3 DPRC2 DPRC1 DISLI4 SR(2) ERSQ1 DISRX4 DISRX3 DISRX2 DISRX1 DISRXA DISTX4 DISTX3 SR(3) DFIFOE DPFRM DSQE DMCV ERXJAB ERSQ4 ERSQ3 ERSQ2 SR(4) RES RES RES RES RES RES RES RES SR(5) RES RES RES RES RES RES RES RES Table 10. Setup Register Bit Definitions Bit DISAPx 1 = Disable Auto-Partitioning on Port x DISLIx 1 = Disable Link Integrity on Port x (Twisted-pair ports only) DPRCx 1 = Disable Polarity Reverse detection and Correction on Port x (Twisted-pair ports only) DISTXx 1 = Disable Transmit on Port x DISRXx 1 = Disable Receive on Port x ERSQx 1 = Enable Reduced Squelch on Port x (Twisted-pair ports only) ERXJAB 1 = Enable Receive JAB (Long Packet) (Global) DMCV 1 = Disable entering Tx Collision state on reception of Manchester Code Violation DSQE 1 = Disable Signal Quality Error to provide heartbeat (AUI port only) DPFRM 1 = Disable End-of-Frame checking for polarity correction (Global) DFIFOE 1 = Disable entering Tx Collision state on FIFO over/underflow condition (Global) DMJLP RES 2.4.2 Definition 1 = Disable MJLP counter (Global) Reserved. Must be set to 0. External Management Mode Initialization The LXT914 operates in the External management mode when the LOC/EXT pin is tied Low. In the External mode, the serial port is a bidirectional interface between the LXT914 and an external management device (EMD). The serial port is used to download initial setup parameters to the repeater and to monitor status reports from the repeater. The LXT914 setup parameters can be changed at any time by the EMD. The initialization process for each repeater in a managed mode configuration is the same, regardless of its position; each repeater is connected directly to the EMD. Each LXT914 initializes as follows: 1. Syncs to the 10 MHz Serial Clock (SCLK) input. SCLK must be supplied from an external source. 2. Responds to SENI Low by enabling the SDI port. 3. Clocks 48 bits from the EMD into its setup register through the SDI port. 4. Once initialized, the LXT914 reports its status in a 48-bit serial stream after every packet transmission or interrupt event. Refer to Table 11 and Table 12 for packet status register bit assignments and definitions. 20 Datasheet Flexible Quad Ethernet Repeater — LXT914 Table 11. Packet Status Register Bit Assignments Register D7 D6 D5 D4 D3 D2 D1 D0 PSR(0) COL2 COL1 COLA RX4 RX3 RX2 RX1 RXA PSR(1) PR2 PR1 LLS4 LLS3 LLS2 LLS1 COL4 COL3 PSR(2) SPA AP4 AP3 AP2 AP1 APA PR4 PR3 PSR(3) LP3 LP2 LP1 LPA SP4 SP3 SP2 SP1 PSR(4) RXJABA MJLP LCOL4 LCOL3 LCOL2 LCOL1 LCOLA LP4 PSR(5) RES RXCOL MANCV FIFOER RXJAB4 RXJAB3 RXJAB2 RXJAB1 Table 12. Packet Status Register Bit Definitions Bit† Definition RXx Received Packet on Twisted-Pair Port 1-4 or on AUI Port COLx Transmit Collision of Twisted -Pair Port 1-4 or on AUI Port LLSCx Link Loss State on Twisted-Pair Port 1-4 or on AUI Port PRx Polarity reversed on Twisted-Pair Port 1-4 or on AUI Port APx Auto-Partition circuit isolated Twisted-Pair Port 1-4 or the AUI Port SPx Short Packet (less than 74 bits) on Twisted-Pair Port 1-4 or on AUI Port LPx Long Packet (more than 1.3 ms) on Twisted-Pair Port 1-4 or on AUI Port LCOLx Late Collision on Twisted-Pair Port 1-4 or on AUI Port MJLP MAU Jabber Lockup Protection RXJABx Receive Jabber Lockup Protection FIFOER FIFO overflow/underflow MANCV Manchester Code Violation RXCOL Receive Collision on the AUI Port RES † Reserved. Not used The notation ABCDx means bit ABCD associated with port x, which can be any of the four Twisted-Pair Ports or the AUI Port. 2.5 10BASE-T Port Operation 2.5.1 10BASE-T Reception Each LXT914 10BASE-T port receiver acquires data packets from its twisted-pair input (TPDIP/ TPDIN). An internal RC filter and an intelligent squelch function discriminate noise from link test pulses and valid data streams. The receive function is activated only by valid data streams (above the squelch level and with proper timing). If the differential signal at the DI circuit inputs falls below 75% of the threshold level (unsquelched) for eight bit times (typical), the port receiver enters the idle state. Datasheet 21 LXT914 — Flexible Quad Ethernet Repeater 2.5.1.1 Programmable Internal Squelch Level The 10BASE-T port receivers have two squelch levels: a normal level or default setting and a reduced level squelch (-4.5 dB) selected when the ERSQx is set in the Setup register. When used with Low noise media such as shielded twisted-pair cabling, the reduced squelch level allows longer loop lengths in the network. 2.5.1.2 Polarity Detection and Correction The LXT914 10BASE-T ports detect and correct for reversed polarity by monitoring link pulses and end-of-frame sequences. A reversed polarity condition is declared when the port receives sixteen or more incorrect link pulses consecutively, or four frames with reversed start-of-idle sequence. In these cases the receiver reverses the polarity of the signal and thereby corrects for this failure condition. If the port enters the link fail state and no valid data or link pulses are received within 96 to 128 ms, the polarity is reset to the default non-flipped condition. (If Link Integrity Testing is disabled, polarity detection is based only on received data.) 2.5.2 10BASE-T Transmission Each LXT914 10BASE-T port receives NRZ data from the repeater core and passes it through a Manchester encoder. The encoded data is then transmitted to the twisted-pair network (the DO circuit). The advanced integrated pulse shaping and filtering network produces the pre-distorted and pre-filtered output signal to meet the 10BASE-T jitter template. An internal continuous resistor-capacitor filter is used to remove any high-frequency clocking noise from the pulse shaping circuitry. Integrated filters simplify the design work required for FCC compliant EMI performance. During idle periods, the LXT914 10BASE-T ports transmit link integrity test pulses in accordance with the 802.3 10BASE-T standard. Data packets transmitted by the LXT914 contain a minimum of 56 preamble bits before the start of frame delimiter (SFD). In the Asynchronous mode, preamble regeneration takes place on the transmit side. In the Synchronous mode, the preamble is regenerated on the receive side and distributed via the IRB. If the total packet is less than 96 bits including the preamble, the LXT914 extends the packet length to 96 bits by appending a Jam signal (1010...) at the end. 2.5.3 10BASE-T Link Integrity Testing The LXT914 fully supports the 10BASE-T Link Integrity test function. The link integrity test determines the status of the receive side twisted-pair cable. Link integrity testing is enabled unless disabled via the DISLIx bit in the Setup register. When enabled, the receiver recognizes link integrity pulses transmitted in the absence of data traffic. With no data packets or link integrity pulses within 100 (±50) ms, the port enters a link fail state and disables its transmitter. The port remains in the link fail state until it detects three or more data packets or link integrity pulses. 22 Datasheet Flexible Quad Ethernet Repeater — LXT914 2.6 AUI Port Operation 2.6.1 AUI Reception The LXT914 AUI port receiver acquires data packets from the network (AUIDIP/AUIDIN). Only valid data streams above the squelch level activate the receive function. If the differential signal at the DI circuit inputs falls below 75% of the threshold level (unsquelched) for 8 bit times (typical), the AUI receiver enters the idle state. 2.6.2 AUI Transmission The LXT914 AUI port receives NRZ data from the repeater core, and passes it through a Manchester encoder. The encoded data then goes out on the network (AUIDOP/AUIDON). 2.6.3 AUI Mode Selection (DTE/MAU) The LXT914 allows the user to change the mode of the AUI from a DTE to a MAU interface. This option is available on both 68- and 100-pin versions except as follows: • When using the LEDJM/AUISEL pin to select the AUI interface mode the following is true: After reset the state of the LEDJM/AUISEL pin is sensed for the correct mode. The LEDJM/ AUISEL pin when floated or pulled Low will select the DTE interface and the LEDJM/ AUISEL output is still available. When the LEDJM/AUISEL pin is pulled High the MAU interface is selected and the LEDJM/AUISEL function is unavailable. • The 100-pin PQFP has an additional pin, AUISEL (pin 30). When using this pin to select the AUI interface mode the LEDJM/AUISEL pin is still a functional LED driver. The AUISEL pin is not latched after reset and is actively polled to determine which AUI interface mode is to be used. Refer to Table 13. Table 13. AUI Mode Selection (DTE/MAU) App # AUISEL (PQFP only) LEDJM/ AUISEL (both pkgs) AUI Mode Available LED Modes 1 Low Low DTE default, 0-3 2 Low High MAU 1-3 † High Low MAU default, 0-3 4 High High MAU 1-3 3 † Datasheet Application 3 is valid only when using the 100-pin PQFP. 23 LXT914 — Flexible Quad Ethernet Repeater 2.7 Collision Handling A collision occurs when two or more repeater ports receive simultaneously, or when the AUI CIP/ CIN signal is active. The LXT914 fully complies with the IEEE 802.3 collision specifications, both in individual and multi-repeater applications. In multiple-repeater configurations, collision signaling on the IRB allows all repeaters to share collision parameters, acting as a single large repeater. IRCOL is a digital open-drain pin. IRCFS is an analog/digital port. The IRCOL and IRCFS lines are pulled up globally (i.e., each signal requires one pull-up resistor for all boards). If there are eight 3-repeater boards in the system, all eight boards share a single pull-up resistor for IRCOL and a single pull-up resistor for IRCFS. The global pull-up may be located on one of the boards, or on the backplane. The IRCFS line requires a precision (± 1%) resistor. The IRENA, IRDAT and IRDEN lines are each pulled up locally (one pull-up resistor per board) if external bus drivers are used. If no bus drivers are used then only one global pull-up per signal is used. 2.8 Security Mode The LXT914 security mode is fully transparent to the user. In the External management mode, the security feature is available for all four TP ports and the AUI port. In the Local mode, security is available for the TP ports only (the SECAUI input is reassigned as FPS). The security inputs are normally held Low to disable the security feature. Any input can independently be pulled High to scramble the respective port for any given length of time. For applications which do not require security control, the SEC pins must be tied Low. The security mode pins are real time response inputs. This allows the board designer to screen the destination address with an application specific device and (on match of the destination address) to assert the security input to jam the respective port for the given frame. This real time detection and jam assertion method provides the flexibility to implement customer specific solutions. The destination address decoding and security signal assertion functions can be integrated into the external management device. 24 Datasheet Flexible Quad Ethernet Repeater — LXT914 2.9 LED Display The LED display interface consists of seven integrated LED drivers, one for each of the five network ports and two for common functions. Each pin provides a three-state pulsed output (+5 V, high Z, and 0 V) which allows multiple conditions to be monitored and reported independently. Table 14 shows the LED Mode selected with each LEDM1 and LEDM0 combination. Figure 5 shows the LED Driver output conditions, and Tables 15 through 18 list the repeater states associated with each of the five conditions. Note: If LED mode 0 is selected and the LEDJM/AUISEL pin is High (which selects MAU Mode), the device defaults to LED Mode 1. LED Mode 0 is not available when LEDJM/AUISEL is pulled High. Table 14. LED Mode Selection † LEDM1 LEDM0 PLCC pin 35 17 PQFP pin 40 14 Low Low 0 (default)† Low High 1 High Low 2 High High 3 LED Mode Selected This mode is not available when using the LEDJM/AUISEL pin to select a MAU interface in the AUI port. In this case, the LED Mode defaults to LED Mode 1. LED Mode 0 (Default) This mode is selected when LEDM1 and LEDM0 are floating or pulled Low. Refer to Table 15. This mode is not available when using the LEDJM/AUISEL pin to select a MAU interface in the AUI port. In this case, the LED Mode defaults to Mode 1. LED Mode 1 This mode is selected when LEDM1 is floating or pulled Low and LEDM0 is pulled High by a pull-up resistor. Refer to Table 16. LED Mode 2 This mode is selected when LEDM1 is pulled High by a pull-up resistor and LEDM0 is floating or pulled Low. Refer to Table 17. LED Mode 3. This mode is selected when LEDM1 is pulled High by a pull-up resistor and LEDM0 is also pulled High by a pull-up resistor. Refer to Table 18. Table 15. Mode 0 (Default) LED Truth Table Datasheet Condition LEDTP 1–4 LEDAUI LEDCF LEDJM 1 Rx Link Pulse N/A FIFO Error Manchester Code Violation 2 Tx Packet Tx Packet N/A N/A MAU Jabber Lockup 3 Reversed Polarity N/A Collision 4 Rx Packet Rx Packet N/A N/A 5 Partitioned Out Partitioned Out N/A N/A Protection (MJLP) 25 LXT914 — Flexible Quad Ethernet Repeater Table 16. Mode 1 LED Truth Table Condition LEDTP 1–4 LEDAUI LEDCF LEDJM 1 Rx Link Pulse N/A MAU Jabber Lockup Protection (MJLP) N/A 2 N/A N/A N/A N/A 3 N/A N/A Collision N/A 4 Rx Packet Rx Packet N/A N/A 5 N/A N/A N/A N/A Table 17. Mode 2 LED Truth Table Condition LEDTP 1–4 LEDAUI LEDCF LEDJM 1 Rx Link Pulse N/A MAU Jabber Lockup Protection (MJLP) N/A 2 Partitioned Out Partitioned Out N/A N/A 3 N/A N/A Collision N/A 4 Rx Packet Rx Packet N/A N/A 5 N/A N/A N/A N/A Table 18. Mode 3 LED Truth Table 26 Condition LEDTP 1–4 LEDAUI LEDCF LEDJM 1 Rx Link Pulse N/A MAU Jabber Lockup Protection (MJLP) N/A 2 Rx Packet Rx Packet N/A N/A 3 Partitioned Out Partitioned Out Collision N/A 4 N/A N/A N/A N/A 5 N/A N/A N/A N/A Datasheet Flexible Quad Ethernet Repeater — LXT914 Figure 5. Integrated LED Driver Indications +5 V 2 mA Operation 5 mA Operation +5 V 820 Ω 330 Ω Red Red LXT914 LED Driver LXT914 LED Driver 470 Ω Green 70 Ω Green 820 Ω 330 Ω Condition 1: Steady Green 4 ms 4 ms 4 ms Condition 2: Blinking Green 4 ms 4 ms 4 ms 4 ms 4 ms +5V High Z 0V (Gnd) 256 ms 4 ms 4 ms 256 ms 4 ms 4 ms 4 ms 4 ms 4 ms 4 ms 4 ms +5V High Z 0V (Gnd) Condition 3: Steady Red 4 ms 4 ms 4 ms Condition 4: Blinking Red +5V High Z 0V (Gnd) 256 ms 256 ms 4 ms 4 ms 4 ms 4 ms 4 ms 4 ms 4 ms 4 ms +5V High Z 0V (Gnd) 5.33 Hz Condition 5: Alternating Red/Green 4 ms 4 ms 4 ms 4 ms 4 ms 4 ms 4 ms +5V High Z 0V (Gnd) 93.75 ms Datasheet 27 LXT914 — Flexible Quad Ethernet Repeater 3.0 Application Information 3.1 12-Port Hub Repeater Figure 6 (Sheets 1 through 4) shows a simple 12-port hub repeater application with 3 LXT914s. This application also provides two additional AUI ports—one DB-15 connector and one coaxial port. The application shown uses the asynchronous backplane mode so no external backplane clock source is required. Figure 6 (Sheet 1) shows the XL93C46 EEPROM which downloads the setup parameters for all the LXT914 devices at initialization. (This EEPROM could be replaced with a simple pull down resistor on the SDI pin. This will select the default conditions of the set up register.) A single 20 MHz crystal provides the SYSCLK for all three LXT914 chips. The LXT914 hub repeater on Sheet 1 provides the AUI DB-15 connector as well as four twisted-pair ports. Table 19 lists transformers suggested for use with the LXT914. Figure 6 (Sheet 2) shows a second LXT914 hub repeater with four TP ports and a coaxial port. The MD-001 coax transceiver is used to implement the port. Sheet 3 shows the third LXT914 device with its four TP ports and indicator LEDs. The AUI port of the third LXT914 hub repeater is not used. Sheet 4 of the schematic shows the LEDs for the remaining LXT914 devices, along with the LED operation table. 3.2 8-Port Print or File Server Figure 7 (Sheets 1 and 2) shows an eight-port repeater attachment for an existing single port AUI or 10BASE5 interface. This application can be added to a current design with an existing AUI or 10BASE5 interface. This circuit allows increased connectivity without the need for another external remote hub. The application shown is a 68-pin PLCC, an asynchronous backplane with both LXT914s in the first position. In Figure 7 (Sheet 1) the LXT914 is set up with the LEDs in Mode 1 with one LED per port and a single collision LED. The twisted pair port LEDs display link integrity only. (Refer to Table 16.) LED Mode 1 is selected by pulling LEDM0 High with a 1 kΩ resistor on pin 17 and pulling LEDM1 Low with pin 35 attached to ground. Figure 7 (Sheet 2) has the same configuration, mode of operation and LED Mode as used in Sheet 1. However, the AUI port has been configured as a MAU interface. This is selected when LEDJM/ AUISEL on pin 28 is pulled up through a 1 kΩ resistor. This mode disables the LEDJM pin as an LED driver. (See Table 13.) The MAU interface now configured on the LXT914 allows the AUI port to attach to a DTE interface. This application increases connectivity to any existing single-port Ethernet design. This unique application allows the designer to integrate an external hub, eliminating the need for additional external equipment. 28 Datasheet Flexible Quad Ethernet Repeater — LXT914 Table 19. Manufacturers Magnetics List Manufacturer Quad Transmit Quad Receive Bell Fuse S553-5999-02 S553-5999-03 Fil-Mag 23Z339 23Z338 HALO TD54-1006L1 TD01-1006L1 TD42-2006Q; TD43-2006K; TG42-1406N1 TG54-1006N2 TG01-1006N2 TG43-1406N TG44-S010NX (Octal) Kappa Datasheet Tx/Rx Pairs TP4003P TP497P101 Nanopulse 5976 5977 PCA EPE6009 EPE6010 Pulse Eng. PE68810 PE68820 VALOR PT4116 PT4117 PE65745; PE65994; PE65746; PE65998 PT4069N1; PT4068N1; ST7011S2; ST7010S2 29 30 † RESET CLK20 SDIN SCLKIO SENO1 1 GND 8 R21 15K C2 .1uF 4 XL93C46 DO U2 DI SK CS 3 2 1 R7 78.7 1% GND 1% R6 78.7 1% VCC 12.4K R20 GND R5 78.7 1% 40 41 42 43 44 45 21 22 23 24 25 37 35 19 20 11 10 15 17 18 14 16 7 8 4 5 1 2 10 9 13 12 16 15 TD01-0756K 7 8 4 5 1 2 T3 +12 LXT914PC AUIDOP AUIDON AUIDIP AUIDIN AUICIP AUICIN SECTP1/DSQE SECTP2 SECTP3 SECTP4 FPS/SECAUI RBIAS LEDM1 TEST RESET SYSCLK BCLKIO SENO* RTS/SDO/LEDM0 SCLKIO CS/SENI* SDI U1 1 10 9 13 12 16 15 GND FUSE C1 33uF F1 TPDIP1 TPDIN1 TPDIP2 TPDIN2 TPDIP3 TPDIN3 TPDIP4 TPDIN4 TPDOP1 TPDON1 TPDOP2 TPDON2 TPDOP3 TPDON3 TPDOP4 TPDON4 LEDAUI LEDTP1 LEDTP2 LEDTP3 LEDTP4 LEDCF LEDJM/AUISEL A/SYNC* LOC/EXT* IRENA* IRDAT IRDEN* IRCFS* IRCOL* GND 66 65 64 63 62 61 60 59 56 57 54 53 50 51 48 47 33 29 30 31 32 27 28 12 13 4 5 6 7 8 1 9 2 10 3 11 4 12 5 13 6 14 7 15 8 R8 R9 R10 R11 R12 R13 R14 R15 P1 DB15 0 24.9 24.9 24.9 24.9 24.9 24.9 24.9 24.9 VCC 100 1% R2 100 1% R1 1% 1% 1% 1% 1% 1% 1% 1% C4 100 1% R3 100 1% R4 120pF C3 120pF C5 RX1:1X4 T1 120pF |LINK |12PORT2.SCH |12PORT3.SCH |12PORT4.SCH 1 2 3 4 5 6 7 8 C6 120pF 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 330 330 TX1:1.41X4 T2 R17 R18 1% 330 R19 330 R16 VCC 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 RJ45X4 CN1A RJ45X4 CN1B RJ45X4 CN1C RJ45X4 CN1D COLLED AUILED TP1LED TP2LED TP3LED TP4LED CLK10 IRENA IRDAT IRCFS IRCOL B Size Title Document Number 12 Port HUB Application Sacramento, CA 95827 916-854-1185 Phone 916-854-1102 Fax When used with an EPROM, pin 17 of LXT914 (U1) may require either a 4.7kΩ pull-up (LEDMO High) or a 4.7kΩ pull-down (LEDMO Low). Refer to Level One Communications / Stephen D. Wasson Table 14 for details. 9750 Goethe Road GND VCC 20Mhz OUT NC Y1 0 Ohm R22 INSTALL EITHER RESISTOR OR EEPROM TP4 TP3 TP2 TP1 R LXT914 — Flexible Quad Ethernet Repeater Figure 6. 12-Port Application Schematic, 68-Pin PLCC Package (Sheet 1 of 4) Datasheet SENO2 Datasheet RESET CLK20 CLK10 SCLKIO SENO1 SDIN C10 .1uF 12.4K R39 PLACE CAPS CLOSE TO MD-001 VCC R37 78.7 1% R36 78.7 1% GND 1% C7 10uF 16v GND 10 9 6 5 4 3 2 1 LXT914 AUIDOP AUIDON AUIDIP AUIDIN AUICIP AUICIN MD-001 GND VCC DODO+ DIDI+ CDCD+ U4 SECTP1/DSQE SECTP2 SECTP3 SECTP4 FPS/SECAUI RBIAS LEDM1 TEST RESET SYSCLK BCLKIO SENO* RTS/SDO/LEDM0 SCLKIO CS/SENI* SDI U3 R38 78.7 1% GND 40 41 42 43 44 45 21 22 23 24 25 37 35 19 20 11 10 15 17 18 14 16 VEE HBE N/C RXI TXO CDS 11 16 12 18 17 20 TPDIP1 TPDIN1 TPDIP2 TPDIN2 TPDIP3 TPDIN3 TPDIP4 TPDIN4 TPDOP1 TPDON1 TPDOP2 TPDON2 TPDOP3 TPDON3 TPDOP4 TPDON4 LEDAUI LEDTP1 LEDTP2 LEDTP3 LEDTP4 LEDCF LEDJM/AUISEL A/SYNC* LOC/EXT* IRENA* IRDAT IRDEN* IRCFS* IRCOL* 66 65 64 63 62 61 60 59 56 57 54 53 50 51 48 47 33 29 30 31 32 27 28 12 13 4 5 6 7 8 SQE DISABLED R27 R28 R29 R30 R31 R32 R33 R34 24.9 24.9 24.9 24.9 24.9 24.9 24.9 24.9 VCC 100 1% R24 100 1% R23 1% 1% 1% 1% 1% 1% 1% 1% C9 .75uF 1KV GND 100 1% R25 100 1% R26 120pF C11 120pF C12 R35 1:1 C8 .01uF 500V RX1:1X4 T4 C14 120pF 1 2 3 4 5 6 7 8 1M 1/2W C13 120pF 16 15 14 13 12 11 10 9 1 : 1 . 41 TX1:1.41X4 16 15 14 13 12 11 10 9 May 5, 1995 B Date: 12 Port HUB Application Document Number Size Title 9750 Goethe Road Sacramento, CA 95827 916-854-1185 Phone 916-854-1102 Fax Level One Communications LOCATE MD-001 AS CLOSE AS POSSIBLE TO BNC 1 2 3 4 5 6 7 8 T5 Sheet 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 2 J1 BNC RJ45X4 CN2A RJ45X4 CN2B RJ45X4 CN2C RJ45X4 CN2D of BNCLED TP5LED TP6LED TP7LED TP8LED IRENA IRDAT IRCFS IRCOL 4 1 REV TP8 TP7 TP6 TP5 Flexible Quad Ethernet Repeater — LXT914 Figure 6. 12-Port Application Schematic, 68-Pin PLCC Package (Sheet 2 of 4) A8323-01 31 32 RESET CLK20 CLK10 SCLKIO SENO2 SDIN GND 12.4K R52 1% GND 40 41 42 43 44 45 21 22 23 24 25 37 35 19 20 11 10 15 17 18 14 16 LXT914 AUIDOP AUIDON AUIDIP AUIDIN AUICIP AUICIN SECTP1/DSQE SECTP2 SECTP3 SECTP4 FPS/SECAUI RBIAS LEDM1 TEST RESET SYSCLK BCLKIO SENO* RTS/SDO/LEDM0 SCLKIO CS/SENI* SDI U5 TPDIP1 TPDIN1 TPDIP2 TPDIN2 TPDIP3 TPDIN3 TPDIP4 TPDIN4 TPDOP1 TPDON1 TPDOP2 TPDON2 TPDOP3 TPDON3 TPDOP4 TPDON4 LEDAUI LEDTP1 LEDTP2 LEDTP3 LEDTP4 LEDCF LEDJM/AUISEL A/SYNC* LOC/EXT* IRENA* IRDAT IRDEN* IRCFS* IRCOL* 66 65 64 63 62 61 60 59 56 57 54 53 50 51 48 47 33 29 30 31 32 27 28 12 13 4 5 6 7 8 R44 R45 R46 R47 R48 R49 R50 R51 24.9 24.9 24.9 24.9 24.9 24.9 24.9 24.9 VCC R41 100 1% R40 100 1% 1% 1% 1% 1% 1% 1% 1% 1% 3 1 100 1% R42 R43 100 1% DUAL LED D4 TP11LED TOP GREEN BOTTOM RED 1 2 3 4 5 6 7 8 C16 120pF 4 2 4 3 DUAL LED 2 D1 TP9LED 1 RX1:1X4 T6 C17 16 15 14 13 12 11 10 9 120pF 120pF 120pF C19 DUAL LED D2 TP12LED DUAL LED D3 TP10LED C18 3 1 3 1 4 2 4 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Date: B Size Title TX1:1.41X4 T7 RP2 820 7 6 5 4 3 2 1 May 5, 1995 Ports 9-12 105 Lake Forest Way Folsom, CA 916-985-3670 Voice 916-985-3512 Fax Level One Communications GND 470 Document Number 1 8 7 6 5 4 3 2 8 9 10 11 12 13 14 RP1 Sheet 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 3 RJ45X4 CN3A RJ45X4 CN3B RJ45X4 CN3C RJ45X4 CN3D 820 RP3 of PUP1 PUP2 PUP3 PDN1 PDN2 PDN3 IRENA IRDAT IRCFS IRCOL TP9 GND C15 .1uF VCC 4 1 REV TP12 TP11 TP10 1 LXT914 — Flexible Quad Ethernet Repeater Figure 6. 12-Port Application Schematic, 68-Pin PLCC Package (Sheet 3 of 4) A8324-01 Datasheet Datasheet TP5LED TP4LED TP3LED TP2LED TP1LED BNCLED AUILED TP5LED TP4LED TP3LED TP2LED TP1LED BNC AUI SOLID TOP BLINKING TOP ALTERNATING TOP/BOT BLINKING BOTTOM SOLID BOTTOM LED OPERATION TABLE AUI/BNC RX JAB TX RX COL RX PART TOP GREEN BOTTOM RED TOP GREEN BOTTOM RED TOP GREEN BOTTOM RED TOP GREEN BOTTOM RED TOP GREEN BOTTOM RED TOP GREEN BOTTOM RED TOP GREEN BOTTOM RED TP# LINK TX POL RX PART 4 4 3 4 3 4 3 4 3 4 3 2 4 1 3 DUAL LED D11 2 1 DUAL LED D10 2 1 DUAL LED D9 2 1 DUAL LED D8 2 1 DUAL LED D7 2 1 DUAL LED D6 2 3 820 1 DUAL LED D5 GND 1 RP5 8 7 6 5 4 3 2 8 9 10 11 12 13 14 470 RP4 7 6 5 4 3 2 1 2 3 4 5 6 7 8 820 RP6 COLLED TP8LED TP7LED TP6LED 1 GND VCC COL TP8LED TP7LED TP6LED C20 .1uF Date: B Size Title 4 3 4 3 4 3 12 Port HUB Application 9750 Goethe Road Sacramento, CA 95827 916-854-1185 Phone 916-854-1102 Fax May 5, 1995 Sheet 4 3 DUAL LED 2 1 D15 2 1 DUAL LED D14 2 1 DUAL LED D13 2 DUAL LED D12 1 Level One Communications Document Number BOTTOM RED TOP GREEN BOTTOM RED TOP GREEN BOTTOM RED TOP GREEN BOTTOM RED 4 of 820 R53 4 1 REV VCC PUP3 PDN3 PUP2 PDN2 PUP1 PDN1 Flexible Quad Ethernet Repeater — LXT914 Figure 6. 12-Port Application Schematic, 68-Pin PLCC Package (Sheet 4 of 4) A8325-01 33 34 RESET 20MHz BCLKIO VCC 12.4K R17 8 OUT 20MHz_OSC Y1 1% VCC R19 1K LXT914PC AUIDOP AUIDON AUIDIP AUIDIN AUICIP AUICIN SECTP1/DSQE SECTP2 SECTP3 SECTP4 FPS/SECAUI RBIAS LEDM1 TEST RESET SYSCLK BCLKIO SENO* RTS/SDO/LEDM0 SCLKIO CS/SENI* SDI U1 |LINK |PAGE2.SCH 40 41 42 43 44 45 21 22 23 24 25 37 35 19 20 11 10 15 17 18 14 16 A/SYNC* LOC/EXT* IRENA* IRDAT IRDEN* IRCFS* IRCOL* TPDIP1 TPDIN1 TPDIP2 TPDIN2 TPDIP3 TPDIN3 TPDIP4 TPDIN4 TPDOP1 TPDON1 TPDOP2 TPDON2 TPDOP3 TPDON3 TPDOP4 TPDON4 LEDAUI LEDTP1 LEDTP2 LEDTP3 LEDTP4 LEDCF LEDJM/AUISEL LED Mode 1 Selected 66 65 64 63 62 61 60 59 56 57 54 53 50 51 48 47 33 29 30 31 32 27 28 12 13 4 5 6 7 8 R5 R6 R7 R8 R9 R10 R11 R12 R15 330 24.9 24.9 24.9 24.9 24.9 24.9 24.9 24.9 R14 330 100 1% R2 100 1% R1 1% 1% 1% 1% 1% 1% 1% 1% R16 330 1% C2 120pf R13 330 VCC 100 1% R3 100 1% R4 C4 120pf 1 2 3 4 5 6 7 8 C3 120pf ircfs ircol irena irdat 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 510 R20 510 R21 510 R22 510 R23 RJ45X4 CN1A RJ45X4 CN1B RJ45X4 CN1C RJ45X4 CN1D D5 D4 D3 D2 9750 Goethe Road Sacramento,CA 95827 Phone 916-854-1185 FAX 916-854-1102 Title 8 Port File Server Application Size Document Number B Date: June 23, 1995 Sheet Level One Communications / Stephen D. Wasson TX1:1.41X4 TG54-1006N2 RX1:1X4 TG01-1006N2 T1 C5 120pf 1 2 3 4 5 6 7 8 T2 link4 link3 link2 link1 1 of TP4 TP3 TP2 TP1 510 R18 D1 YELLOW LED Green LEDs COLLISION REV 2 VCC LXT914 — Flexible Quad Ethernet Repeater Figure 7. 8-Port Application Schematic, LED Mode 1 with AUISEL = MAU (Sheet 1 of 2) A8326-01 Datasheet Datasheet CIP CIN DOP DON DIP DIN AUI Port RESET D10 1N4148 7 8 4 5 1 2 R24 15K C1 .1uF 13 12 13 12 16 15 RESET VCC R25 78.7 1% 12.4K R28 20MHz BCLKIO 1% R23 1K 40 41 42 43 44 45 21 22 23 24 25 37 35 19 20 11 10 15 17 18 14 16 AUISEL = MAU 10 7 10 9 8 9 TG01-0756 4 5 T5 1 16 2 15 VCC VCC R27 78.7 1% R26 78.7 1% LXT914PC AUIDOP AUIDON AUIDIP AUIDIN AUICIP AUICIN SECTP1/DSQE SECTP2 SECTP3 SECTP4 FPS/SECAUI RBIAS LEDM1 TEST RESET SYSCLK BCLKIO SENO* RTS/SDO/LEDM0 SCLKIO CS/SENI* SDI U2 LED Mode 1 Selected TPDIP1 TPDIN1 TPDIP2 TPDIN2 TPDIP3 TPDIN3 TPDIP4 TPDIN4 TPDOP1 TPDON1 TPDOP2 TPDON2 TPDOP3 TPDON3 TPDOP4 TPDON4 LEDAUI LEDTP1 LEDTP2 LEDTP3 LEDTP4 LEDCF LEDJM/AUISEL A/SYNC* LOC/EXT* IRENA* IRDAT IRDEN* IRCFS* IRCOL* 66 65 64 63 62 61 60 59 56 57 54 53 50 51 48 47 33 29 30 31 32 27 28 12 13 4 5 6 7 8 R33 R34 R35 R36 R37 R38 R39 R40 24.9 24.9 24.9 24.9 24.9 24.9 24.9 24.9 1K R41 ircfs ircol irena irdat 100 1% R30 100 1% R29 1% 1% 1% 1% 1% 1% 1% 1% 100 1% R31 100 1% R32 VCC 1 2 3 4 5 6 7 8 C8 120pf C6 120pf C9 120pf 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 Size B Date: Title 9750 Goethe Road Sacramento, CA 95827 June 20, 1995 Sheet 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 510 R45 510 R44 510 R43 510 R42 Level One Communications 8 Port File Server Application Document Number TX1:1.41X4 TG54-1006N2 T3 RX1:1X4 TG01-1006N2 T4 1 2 3 4 5 6 7 8 C7 120pf LINK8 LINK7 LINK6 LINK5 Green LEDs 2 RJ45X4 CN2A RJ45X4 CN2B RJ45X4 CN2C RJ45X4 CN2D D9 D8 D7 D6 of 2 REV - TP8 TP7 TP6 TP5 Flexible Quad Ethernet Repeater — LXT914 Figure 7. 8-Port Application Schematic, LED Mode 1 with AUISEL = MAU (Sheet 2 of 2) A8327-01 35 LXT914 — Flexible Quad Ethernet Repeater 4.0 Test Specifications Note: Minimum and maximum values in Tables 20 through 28, and Figures 8 and 9 represent the performance specifications of the LXT914 and are guaranteed by test except, where noted, by design. Table 20. Absolute Maximum Ratings Parameter Symbol Min Typ Max Units VCC -0.3 – 6 V LXT914PC/QC TOP 0 – +70 °C LXT914PE TOP -40 – +85 °C TST -65 – +150 °C Supply voltage Operating temperature Storage temperature Caution: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 21. Recommended Operating Conditions Parameter Symbol Min Typ Max Units VCC 4.75 5.0 5.25 V LXT914PC/QC TOP 0 – +70 °C LXT914PE TOP -40 – +85 °C Recommended supply voltage Recommended operating temperature Table 22. I/O Electrical Characteristics1 (over recommended range) Symbol Min Typ2 Max Units Supply current ICC – – 180 mA Input Low voltage VIL – – 0.8 V VILRESET – – 0.8 V VIH 2.0 – – V Parameter Input Low voltage (RESET) Input High voltage Test Conditions VCC = 5.25 V VIHRESET 4.0 – – V VCC = 4.75 V Output Low voltage VOL – – 0.4 V IOL = 1.6 mA Output Low voltage VOL – – 10 % VCC IOL < 10 µA Output Low voltage (LED) VOLL – – 1.0 V IOLL = 5 mA Input High voltage (RESET) Output High voltage VOH 2.4 – – V IOH = 40 µA Output High voltage VOH 90 – – % VCC IOH < 10 µA Output High voltage (LED) VOHL 4 – – V IOHL = -5 mA IIL – – 2 mA Input Low current VOL = .4 V NOTES: 1. Not applicable to IRB signals. IRB electrical characteristics are specified in Table 25. 2. Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to production testing. 36 Datasheet Flexible Quad Ethernet Repeater — LXT914 Table 22. I/O Electrical Characteristics1 (over recommended range) Parameter Output rise / fall time RESET pulse width RESET fall time Symbol Min Typ2 Max Units – – 3 8 ns CLOAD = 20 pF 1.0 – – ms VCC = 4.75 V – – 20.0 µs VIHRESET to VILRESET PWRESE T TFRESET Test Conditions NOTES: 1. Not applicable to IRB signals. IRB electrical characteristics are specified in Table 25. 2. Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to production testing. Table 23. AUI Electrical Characteristics (over recommended range) Symbol Min Typ† Max Units Input Low current IIL – – -700 µA Input High current IIH – – 500 µA Differential output voltage VOD ±550 – ±1200 mV Receive input impedance ZIN – 20 – kΩ Differential squelch threshold VDS – 220 – mV Parameter † Test Conditions Between CIP/CIN & DIP/ DIN Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to production testing. Table 24. Twisted-Pair Electrical Characteristics (over recommended range) Symbol Min Typ1 Max Units Transmit output impedance ZOUT – 5 – Ω Peak differential output voltage VOD 3.3 3.5 3.7 V Load = 100 Ω at TPOP and TPON Transmit timing jitter addition – – ± 6.4 ± 10 ns 0 line length Transmit timing jitter added by the MAU and PLS sections2 – – ± 3.5 ± 5.5 ns After line model specified by IEEE 802.3 for 10BASE-T Receive input impedance ZIN – 20 – kΩ Between TPIP/TPIN Differential squelch threshold (Normal threshold: ERSQx = 0) VDS 300 420 565 mV 5 MHz square wave input Differential squelch threshold (Reduced threshold: ERSQx = 1) VDSL 180 250 345 mV 5 MHz square wave input Parameter Test Conditions NOTES: 1. Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to production testing. 2. IEEE 802.3 specifies maximum jitter additions at 1.5 ns for the AUI cable, 0.5 ns from the encoder, and 3.5 ns from the MAU. Datasheet 37 LXT914 — Flexible Quad Ethernet Repeater Table 25. IRB Electrical Characteristics (over recommended range) Symbol Min Typ† VOL – .3 .6 V TF – 4 12 ns Input Low voltage: IRENA, IRCOL & IRDAT VILIRB – – 0.8 V RL = 330 Ω Input High voltage: IRENA, IRCOL & IRDAT VIHIRB 3.0 – – V RL = 330 Ω Input Low voltage: BCLKIO VILBCLK – – 0.4 V RL = 330 Ω Input High voltage: BCLKIO VIHBCLK 4.0 – – V RL = 330 Ω Parameter Output Low voltage Output rise or fall time † Max Units Test Conditions Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to production testing. Table 26. Switching Characteristics (over recommended range) Min Typ† Max Units 5.0 – 5.5 ms Unjab time – 9.6 – µs Time link loss – 60 – ms Time between Link Integrity Pulses 10 – 20 ms Interval for valid receive Link Integrity Pulses 4.1 – 30 ms Parameter Maximum transmit time Jabber Timing Link Integrity Timing † Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to production testing. Table 27. Serial Port Timing—External Mode (over recommended range) Symbol Minimum Typical† Maximum Units SCLKIO High to SENI Low (active) tS1 0 – 50 ns Parameter SCLKIO High to SDIN data valid tS2 0 – 50 ns SCLKIO High to SENO Low (active) tS3 5 – 15 ns SCLKIO Low to SDOUT data valid tS4 5 – 15 ns † 38 Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to production testing. Datasheet Flexible Quad Ethernet Repeater — LXT914 Figure 8. Serial Port Timing SCLKIO RESET tS1 SENI tS2 SDIN tS3 SENO tS4 1 2 3 4 5 6 48 SDOUT Table 28. Inter-Repeater Bus Timing (over recommended range) Symbol Minimum Typical† Maximum Units tIRB1 10 – 150 ns Start of Frame to IRENA Low (active) tIRB2 125 – 225 ns BCLKIO to IRDAT valid (Synchronous mode) tIRB3 5 – 30 ns BCLKIO to IRDAT valid (Asynchronous mode) tIRB3 – 50 – ns IRENA Low (active) to TP outputs active tIRB4 525 – 600 ns IRENA Low (active) to AUI output active tIRB5 475 – 525 ns End of Frame clock to IRENA High (inactive) tIRB6 5 – 30 ns IRENA High (inactive) to IRDEN High (inactive) tIRB7 95 – 105 ns IRENA High (inactive) to TP outputs inactive tIRB8 575 – 600 ns IRENA High (inactive) to AUI output inactive tIRB9 425 – 450 ns Parameter Start of Frame to IRDEN Low (active) † Datasheet Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to production testing. 39 LXT914 — Flexible Quad Ethernet Repeater Figure 9. Inter-Repeater Bus Timing Rx DATA tIRB4 TPs tIRB8 tIRB5 tIRB9 AUI tIRB7 tIRB1 IRDEN tIRB6 tIRB2 IRENA tIRB3 IRDAT BCLKIO 40 Datasheet Flexible Quad Ethernet Repeater — LXT914 5.0 Mechanical Specifications Figure 10. LXT914PC/PE Package Specifications 68-Pin Plastic Leaded Chip Carrier • Part Number LXT914PC for Commercial Temperature Range (0°C to +70°C) • Part Number LXT914PE for Extended Temperature Range (-40°C to +85°C) Inches CL Millimeters Dim Min Max Min Max A 0.165 0.180 4.191 4.572 A1 0.090 0.120 2.286 3.048 A2 0.062 0.083 1.575 2.108 B 0.050 – 1.270 – C 0.026 0.032 0.660 0.813 D 0.985 0.995 25.01 9 25.27 3 D1 0.950 0.958 24.13 0 24.33 3 F 0.013 0.021 0.330 0.533 C B D1 D D A2 A A1 F Datasheet 41 LXT914 — Flexible Quad Ethernet Repeater Figure 11. LXT914QC Package Specifications 100-Pin Quad Flat Package • Part Number LXT914QC • Commercial Temperature Range (0°C to +70°C) Inches D Millimeters D1 Dim Max Min Max A – 0.134 – 3.40 A1 0.010 – 0.25 – A2 0.100 0.120 2.55 3.05 B 0.009 0.015 0.22 0.38 D 0.931 0.951 23.65 24.15 D1 0.783 0.791 19.90 20.10 D3 0.742 REF 0.695 0.715 17.65 18.15 E1 0.547 0.555 13.90 14.10 E3 0.486 REF 12.35 REF e 0.026 BSC† (nominal) 0.65 BSC† (nominal) 0.026 E1 E 18.85 REF E L † Min 0.037 0.65 D Side pin count = 30 E Side pin count = 20 0.95 L1 0.077 REF θ 1.95 REF 0° 7° 0° 7° θ3 5° 16° 5° 16° e/ e 2 BSC = Basic Spacing Between Centers θ3 L1 A2 A θ A1 42 L B θ3 Datasheet