ADVANCE INFORMATION PI6C1202 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Precision Clock Generator for Laser Printers Features Description Supports laser printer pixel rates up to 120 MHz. Jitter less than 200ps. Easily programmable frequency selections via parallel interface. Post divider (R) designed to load only during the Beam Detect interval. Source clock input can be from crystal or oscillator. Crystal frequency range from 8 MHz to 22 MHz. Oscillator frequency range from 8 MHz to 30 MHz. Active LOW asynchronous reset input for synchronization with engine via Beam Detect Input. Synchronized Beam Detect Output to support external state machines. Glitch-less clock output after Beam Detect. Supports dynamic frequency changes on a line-per-line basis. Mixed line resolution supports half-toning and gray scale operations. Minimizes controller memory utilization (low-resolution text mixed with high-resolution images). On-chip VCO loop filter (no external components). On-chip crystal oscillator (modified Pierce). Single 5V power supply. Low power consumption. Packaging: 20-pin wide body SOIC (S), 20-pin wide body TSSOP (L) The PI6C1202 is an advanced CMOS clock generator designed specifically to support pixel clock generation in low-cost laser printers. Capable of generating highly stable clock frequencies up to 120 MHz, this device supports printer engines with dot resolutions of 1,200 dpi and above. Page speeds may range from 4 pages per minute to better than 60 pages per minute. Mixed-line resolution supports half-toning and gray scale operations (low-resolution text mixed with high-resolution images) and minimizes controller memory utilization. Pinout Diagram X1/ICLK 1 20 BDOWID X2 2 19 GND SEL0 3 18 PCLK 4 17 GND 16 BD# GND 20-Pin L, S SEL1 5 SEL2 6 15 BDOUT VCC 7 14 BDOPOL AGND 8 13 R0 OE 9 12 R1 10 11 R2 AVCC Functional Block Diagram Prescale X1 X2 CLK IN .. 2 Phase & Freq Det Charge Pump Loop Filter VCO Multiplier .. N 0 1 2 SEL BD# OE Control & Resolution Select (R) BDOUT PCLK R0 R1 R2 1 PXXXX 09/06/01 ADVANCE INFORMATION PI6C1202 Precision Clock Generator for Laser Printers 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Pin Description Pin Name 1 X1/ICLK 2 X2 4 GND 3 5 6 SEL(0- 2) 7 VCC D e s cription CRYSTAL, or input from external clock source. This pin is connected to a crystal or may be used to input an external reference frequency. When connected to a crystal, a 33pF (typ) capacitor should be connected from this pin to ground. When driven by an external clock there is no need for a capacitor. CRYSTAL. Output of Ring O scillator. This pin should typically have a 22pF capacitor to ground when used with a crystal. For fine- tuning the crystal frequency, this capacitor can be trimmed from 15pF to 33pF. If X1 is driven by an external clock source, there is no need for a capacitor. Digital Ground Selects VCO/Crystal Multiplication Ratio.These pins can be dynamically changed anytime (not recommended during active imaging).These inputs must be tied HIGH/LO W or driven actively to guarantee that the setting stays valid. Refer to Table 2 for additional information. These pins have internal pull- up resistors. Digital VCC 8 AGND 9 OE 10 AVCC Analog VCC 11 12 13 R(0- 2) O utput Resolution Selection. Used to set the final dot resolution. The divide ratios set by these pins are all tightly aligned synchronous outputs designed to eliminate glitches and allow dynamic changes to the output clock dot resolution frequency on a per- line basis. These pins can only be changed during the BD# (Beam Detect) active interval. The signals should be externally latched at least one or two PCLK cycles prior to BD# going active to guarantee internal latches setup and hold times. R0 allows single- pin control for 1/4 or 1/8 mode (assuming R1 and R2 = 1). Please refer to Table 1 for further information. These pins have internal pull- up resistors. 14 BDOPOL Beam Detect Output Polarity: This pin is used to set the polarity of the BDOUT output (pin 15). When this pin is LO W, the BDOUT polarity is active HIGH. When this pin is HIGH, the BDO UT polarity is active LOW. This pin is pulled up internally. 15 BDO UT Beam Detect O utput. This pin signals the start of a new line after synchronization has occurred. The BDOUT signal will go active when the incoming BD# signal is detected and synchronized. The width of this pulse is dependent upon the VCO frequency and the current PCLK setting. Please refer to the timing diagram for additional information. The polarity of BDO UT can be controlled by BDO PO L (pin 14) and the width can be set to 1 or 2 PCLKs by BDOWID (pin20). BDOUT can be 3- stated by the O E pin. BDOUT has a 12mA balanced drive CMO S output. 16 BD# Beam Detect Input from Engine. The engine signal that drives this pin indicates that the end (or beginning) of a line has been detected. Since this signal is typically an asynchronous strobe, this active- low edge- sensitive input is extremely metastable- resistant. This input has a TTL- compatible input threshold with hysteresis. This pin has an internal pull- up resistor. 17 GND Digital Ground 18 PCLK Pixel Clock O utput. The output frequency of this pin is a function of the crystal (or input clock) frequency (prescaled to 1/2, the multiply ratio as set by SEL(0- 2) and the final divide ratio as set by R(0- 2): PCLK = Crystal x (1/2) x [32, 16, or 8 as defined by SEL(0- 1)] x (1/8 or 1/4 as controlled by R0 - assumes R1=R2=1). This output can be glitchlessly synchronized to an external asynchronous event by asserting the BD# input. The minimum indeterminacy of the alignment to the external event is controlled by the width of the VCO clock. Please refer to timing diagrams for additional information. The PCLK output can be 3- stated by the OE pin. This pin has a 12mA balanced- drive CMOS output. 19 GND Digital Ground 20 Analog Ground O utput Enable. When pulled HIGH, this pin will enable the PCLK and the BDO UT outputs. When pulled LO W, these pins are 3- stated. This pin has an internal pull- up resistor. BDO WID Beam Detect O utput Width: This pin is used to set the width of the BDOUT output (pin 15). When this pin is LO W, the BDOUT width is two PCLK periods. When this pin is HIGH, the BDOUT width is one PCLK period. This pin has an internal pull- up resistor. 2 PXXXX 09/06/01 ADVANCE INFORMATION PI6C1202 Precision Clock Generator for Laser Printers 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Basic PLL Flow Diagram 0 Prescaler Divider XTAL SEL 1 2 R0 R1 R2 Synchronous Counter/Divider Dot Resolution VCO/Multiplier .. 2 PCLK BDOUT . .. 2 to . 256 x8, x16, x32 BD# Table 2. VCO Multiplier Pin Setting Table 1. Dot Resolution Divider Pin Setting R2 R1 R0 Function R SEL2 SEL1 SEL0 Function 0 0 0 ÷ 16 16 1 0 0 Reserved 0 0 1 ÷ 32 32 1 0 1 x8 0 1 0 ÷ 64 64 1 1 0 x32 0 1 1 ÷ 128 128 1 1 1 x16 1 0 0 ÷ 256 256 1 0 1 ÷2 2 1 1 0 ÷4 4 1 1 1 ÷8 8 Note: 1. The relationship of the VCO to PCLK is controlled by the R synchronous divider. For example: (a) 1 PCLK = 4 VCO clocks if R0 = 0 & R1 = R2 = 1 (b) 1 PCLK = 8 VCO clocks if R0 = 1 & R1 = R2 = 1 3 PXXXX 09/06/01 ADVANCE INFORMATION PI6C1202 Precision Clock Generator for Laser Printers 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .............................................................. 65°C to +150°C Ambient Temperature with Power Applied .................................. 0°C to +70°C Supply Voltage to Ground Potential (Inputs & Vcc only) ......... 0.3V to +7.0V DC Input Voltage ...................................................................... 0.5V to +7.0V DC Output Current ............................................................................... 120 mA Power Dissipation ................................................................................... 1.0 W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Electrical Characteristics (VCC = 5V ±5%. TA = 0°C to 70°C) Symbol VIH(1) Te s t Conditions (2) De s cription Input HIGH Voltage All Inputs except X1 & BD# VIHX1(1) Input HIGH Voltage X1 X1 Input VBDTH(1) Input Threshold Voltage BD# Input LOW Voltage VIL(1) M in. Typ.(3) M ax. 2.0 VCC - 1.0 VCC = 4.75V to 5.25V 1.2 1.4 All Inputs 0.8 IIH Input HIGH Current w/ Pull- up All Inputs except X1, VCC = Max., VIN = VCC 5 IIL Input LOW Current w/ Pull- up All Inputs except X1, VCC = Max., VIN = 0V 50 IIHX1 Input HIGH Current X1 X1 Input, VCC = Max., VIN = VCC 150 IILX1 Input LOW Current X1 X1 Input, VCC = Max., VIN = 0V 150 VOH Output HIGH Voltage All Outputs except X2, VCC = Min., IOH = 12mA 2.4 VOL Output LOW Voltage All Outputs except X2, VCC = Min., IOL = +12mA 0.4 IOS(1,4) Short Circuit Current VCC = 5.25V, VOUT = GND 25 Dynamic Supply Current VCC = 5.0V, X1 = 20 MHz SEL = x16 35 VCC = 5.0V, X1 = 15 MHz SEL = x32 50 VCC = 5.0V, X1 = 17.5 MHz, SEL = x32 60 IC Units V µA V mA Notes: 1. These parameters are guaranteed by design and measured at characterization only. 2. For Max. or Min. conditions, use appropriate values specified under Electrical Characteristics for the appropriate device type. 3. Typical values are shown at VCC = 5.0V, +25°C ambient and maximum loading. 4. Not more than one output should be shorted at one time. Duration of test should not exceed one second. 4 PXXXX 09/06/01 ADVANCE INFORMATION PI6C1202 Precision Clock Generator for Laser Printers 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Characteristics (VCC = 5V ±5%. TA = 0º C to 70º C) Symbol D e s cription tR(1) tF(1) Te s t Conditions PCLK O utput Rise Time (0.8V to 2.0V) Typ. M ax. 2 2 1.5 7.5 1.5 6.0 50/50 45/55 8 22 120 352 8 30 480 CL = 30pF PCLK O utput Fall Time (2.0V to 0.8V) tPZH(1) tPZL(1) O E to PCLK O utput Enable Time (Please refer to the Test Circuit & Waveform) tPHZ(1) tPLZ(1) O E to PCLK O utput Disable Time (Please refer to the Test Circuit & Waveform) dT(1) M in. CL = 30 pF, RL = 500 O hms Rpu = 500 O hms to 7V (for tPZL and tPLZ only) PCLK Duty Cycle FXTALIN Crystal Input Frequency (Production tested at 15.0 MHz) Within the following VCO frequency range FVCO(2) VCO Frequency with FXTALIN PCLK = 88 MHz Driven Input Frequency (Production tested at 4,20,22, and 30 MHz) Within the following VCO frequency range VCO Frequency with FIN PCLK = 120 MHz 120 PCLK one sigma jitter X1 = 15 MHz, SEL = x32, R = 8 50 200 FIN FVCO(2) TJIS (1) TJAB(1) PCLK short term peak- to- peak jitter TVCO(3) VCO clock period 2 8.333 TPCLK(4) PCLK clock period Units ns % MHz ps ns Notes: 1. These parameters are guaranteed by design and measured at characterization only. 2. The VCO frequency can be determined by the following formula: FVCO = FXTALIN or FIN 2 x N N = VCO multiplier value. See Table 2 For example: For X1 = 20 MHz and SEL = x16, then: FVCO = (20 MHz / 2) x 16 = 160 MHz For X1 = 15 MHz and SEL = x32, then: FVCO = (15 MHz / 2) x 32 = 240 MHz 3. The VCO clock period is determined by the formula: TVCO = 1 / FVCO. For design aid only. 4. TPLCK = TVCO x R, R = output dot resolution divider function (see Table 1). For design aid only. Not subject to production testing. Bench Characterization Waveform Enable and Disable Timing Bench Characterization Test Circuit Te s t Open Drain Disable LOW Enable LOW Closed All Other Inputs Open Pulse Generator CL Switch = Load Capacitance OE (Includes jig and probe Capacitance) RL = Load Resistance RPU = Pull-Up Resistance Rt = Termination Resistance VOUT 1.5V tPZL +7V VIN 3V Disable (Should be equal to Zout of Pulse Generator) 3.5V Output Normally Low 500Ω RPU 30pF CL Output Normally High 500Ω RL 0V tPLZ 1.5V 3.3V 0.3V tPHZ tPZH D.U.T Rt Enable 1.5V 1.5V 0.3V 0V VOL VOH 0V Pulse Generator for All Pulses: Rate ≤ 1.0 NGz; Zout ≤ 50 ohms, tF, tR ≤ 2.5ns 5 PXXXX 09/06/01 ADVANCE INFORMATION PI6C1202 Precision Clock Generator for Laser Printers 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Timing Table(4) (VCC = 5V ±5%. TA = 0º C to 70º C) Symbol De s cription M in. Typ. M ax. Minimum BD# Pulse Width(2) 22 TVCO Time from BD# Active to BDsync 18 TVCO 19 TVCO T3 Synchronous Time from BD# to BDOUT 19 TVCO + 0.5 TPCLK + tD - 0.5 tJT3 20 TVCO + 0.5 TPCLK + tD + 0.5 tJT3 T4(1) Width of BDOUT Pulse BDOWID = 0 BDOWID = 1 2 TPCLK - 0.5 tJT4 1 TPCLK - 0.5 tJT4 T5 Time from BDOUT active to the first valid rising edge of PCLK 0.47 TPCLK - 0.5 tJT5 T6 Total time from BD# active to the first valid rising edge of PCLK T3 + T5 = 19 TVCO + 0.97 TPCLK + tD 0.5 tJT6 T3 + T5 = 20 TVCO + 1.0 TPCLK + tD + 0.5 tJT6 tD On- chip total buffer delays See Note 3 See Note 3 tJT3(5) T3 peak- to- peak jitter 0ps tJT4(5) T4 peak- to- peak jitter 0ps tJT5(5) T5 peak- to- peak jitter 0ps tJT6(5) T6 peak- to- peak jitter 0ps T1 T2(1) 2 TPCLK 1 TPCLK 2 TPCLK + 0.5 tJT4 1 TPCLK + 0.5 tJT4 0.5 TPCLK 0.5 TPCLK + 0.5 tJT5 200 ps Notes: 1. These parameters are guaranteed by design and functional test only. 2. The width of the BD# pulse (T1) MUST meet the minimum width requirements of 22 TVCO. BD# pulses less than 22 TVCO will not achieve synchronization and will not generate BDOUT. For measurement purposes, the falling edge of BD# should be 6 ns or less. 3. tD is extracted from initial product characterization. It varies with both VCC and temperature. The following linear regression formulas may be used to calculate tD for 4.75V < VCC < 5.25V and 0oC < TA < 70oC. This is provided for design purposes only. A +10% guardband of the calculated value will be used for production testing. A. Linear regression of tD vs. VCC at a fixed temperature: tD = Slope x VCC + Intercept Te mpe rature (o C) 0 20 40 60 80 Intercept (ns) 14.032 14.756 15.585 16.771 17.107 Slope (ns/V) 1.224 1.296 1.396 1.568 1.564 B. Linear regression of tD vs. Temperature at a fixed VCC: tD = Slope x Temperature + Intercept VCC (V) 4.50 4.75 5.00 5.25 5.50 Intercept (ns) 8.578 8.206 7.872 7.586 7.364 (ns/oC) 0.019 0.018 0.017 0.017 0.014 Slope 4. TVCO = VCO clock period. TPCLK = PCLK clock period. 5. Parameters obtained from initial characterization, not subject to production testing. 6 PXXXX 09/06/01 ADVANCE INFORMATION PI6C1202 Precision Clock Generator for Laser Printers 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Timing Diagram PLL to Output Clock and Beam Detect Reset Sequence 0 ... 20 22 25 VCO/PLL ... ... BD# T1 1.3V ... BDsync (internal) T2 1.5V T3 T6 BDOUT T4 T5 ... ... 1.5V PCLK (entering low) ... PCLK (entering high) Note: 1. The PCLK frequency in this example is 1/4 the VCO frequency (R0=0 & R1=R2=1 ® see Table 1) For measurement purposes the BD# falling edge should be less than 6ns for 90% to 10%. VCC Power-Up and VCO Ramp to Lock Timing (Provided for Implementation Reference Purposes only). <-2.2ms-> <-------- VCO Ramp Up ---------> <------------ VCO Locked ---------->>>>> 5v 5v * Vcc 2v internal reset point ~2.2v 0v 0v 1234567890123456781234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 123456789012345678 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 123456789012345678 1234567890123456789012345678901212345678901234 1234567890123456781234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 123456789012345678 1234567890123456789012345678901212345678901234 1234567890123456781234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 123456789012345678 1234567890123456789012345678901212345678901234 1234567890123456781234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 123456789012345678 1234567890123456789012345678901212345678901234 1234567890123456781234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 5v VCO 0v 0 1 2 3 4 5 6 7 * Only one BDOUT Pulse is generated by the internal power-up reset. 8 9 10 11 12 13 14 15 16 17 5v 0v 18 Milliseconds 7 PXXXX 09/06/01 ADVANCE INFORMATION PI6C1202 Precision Clock Generator for Laser Printers 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 20-Pin SOIC (S) Package 20 .2914 .2992 7.40 7.60 .010 .029 0.254 x 45˚ 0.737 1 .496 12.60 .511 12.99 .0091 .0125 0-8˚ 0.41 .016 1.27 .050 .020 0.508 REF .030 0.762 .0926 .1043 2.35 2.65 .394 .419 10.00 10.65 SEATING PLANE .050 BSC 1.27 0.23 0.32 .013 .020 0.33 0.51 0.10 0.30 .0040 .0118 X.XX DENOTES CONTROLLING X.XX DIMENSIONS IN MILLIMETERS 20-Pin TSSOP (L) Package 20 .169 .177 4.3 4.5 1 .252 .260 6.4 6.6 .0256 BSC 0.65 .004 0.09 .008 0.20 .047 1.20 Max .007 .012 0.19 0.30 0.45 0.75 SEATING PLANE .018 .030 .238 .269 6.1 6.7 .002 0.05 .006 0.15 X.XX X.XX DENOTES CONTROLLING DIMENSIONS IN MILLIMETERS Ordering Information Orde ring Code D e s cription Package Type PI6C1202S Normal Drive 20- pin 300- mil SO IC PI6C1202L High Drive 20- pin 173- mil TSSO P Ope rating Range 0°C to +70°C Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 8 PXXXX 09/06/01