PI74FCT841T/843T/845T (25Ω SERIES) P174FCT2841T PI74FCT841T/843T/845T BUS INTERFACE LATCHES 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 (25Ω Series) PI74FCT2841T 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Fast CMOS Bus Interface Latches Product Features: • PI74FCT841/843/845/2841T is pin compatible with bipolar FAST™ Series at a higher speed and lower power consumption • 25Ω series resistor on all outputs (FCT2XXX only) • TTL input and output levels • Low ground bounce outputs • Extremely low static power • Hysteresis on all inputs • Industrial operating temperature range: –40°C to +85°C • Packages available: – 24-pin 300 mil wide plastic DIP (P) – 24-pin 150 mil wide plastic QSOP (Q) – 24-pin 150 mil wide plastic TQSOP (R) – 24-pin 300 mil wide plastic SOIC (S) Product Description: Pericom Semiconductor’s PI74FCT series of logic circuits are produced in the Company’s advanced 0.8 micron CMOS technology, achieving industry leading speed grades. All PI74FCT2XXX devices have a built-in 25-ohm series resistor on all outputs to reduce noise because of reflections, thus eliminating the need for an external terminating resistor. The PI74FCT841T/843T/845T and P174FCT2841T series are buffered interface latches. These transparent latches designed with 3-state outputs and are designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. When Latch Enable (LE) is HIGH, the flip-flops appear transparent to the data. The data that meets the set-up time when LE is LOW is latched. When OE is HIGH, the bus output is in the high impedance state. The PI74FCT841/2841T is a 10-bit latch, the PI74FCT843T is a 9-bit latch, and the PI74FCT845T is an 8-bit latch. PI74FCT841/843/845/2842T Logic Block Diagram D0 D1 D2 D3 D4 D5 DN–1 DN PRE D P D P Q D P Q LE CLR LE CLR D P Q D P Q LE CLR D P Q LE CLR D P Q LE CLR D P Q LE CLR LE Q CLR LE CLR CLR LE OE Y0 Y1 Y2 Y3 1 Y4 Y5 YN–1 YN PS2025A 03/11/96 PI74FCT841T/843T/845T (25Ω SERIES) P174FCT2841T BUS INTERFACE LATCHES 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI74FCT841/2841T 10-Bit Latch Product Configuration Product Pin Description OE 1 24 Vcc D0 2 23 Y0 D1 3 22 Y1 D2 4 21 Y2 D3 5 20 Y3 D4 6 19 Y4 D5 7 18 Y5 D6 8 17 Y6 D7 9 16 Y7 D8 10 15 Y8 D9 11 14 Y9 GND 12 13 LE 24-PIN P24 Q24 R24 S24 Pin Name YN DN LE OE CLR PRE GND VCC Description 3-State Latch Outputs Latch Data Inputs Latch Enable Input Output Enable Control Clear Latch Preset Latch High, Preset Overrides CLR Ground Power Truth Table(1) PI74FCT843T 9-Bit Latch Product Configuration Inputs OE 1 24 Vcc D0 2 23 Y0 D1 3 22 Y1 D2 4 21 Y2 D3 5 20 Y3 D4 6 19 Y4 D5 7 18 Y5 Latched (High Z) D6 8 17 Y6 D7 9 16 Y7 24-PIN P24 Q24 R24 S24 D8 10 15 Y8 CLR 11 14 PRE GND 12 13 LE Function High-Z PI74FCT845T 8-Bit Latch Product Configuration Vcc OE1 1 24 OE2 2 23 OE3 D0 3 22 Y0 D1 4 21 Y1 D2 5 20 Y2 D3 6 19 Y3 D4 7 18 Y4 D5 8 17 Y5 D6 9 16 Y6 D7 10 15 Y7 CLR 11 14 PRE GND 12 13 LE 24-PIN P24 Q24 R24 S24 LE DN X X H L H H YN Z Z Z QN X L H H H H L X Z NC Transparent H H H H L L H H L H L H L H Latched H H L L X NC NC Preset H L L X X H H Clear L H L X X L L Preset L L L X X H H Latched (High Z) L H H L X Z L Latched (High Z) H L H L X Z H 1. 2 CLR PRE OE H H H H H H H H H Outputs Internal H = High Voltage Level L = Low Voltage Level X = Don't Care NC = No Change Z = High Impedance PS2025A 03/11/96 PI74FCT841T/843T/845T (25Ω SERIES) P174FCT2841T BUS INTERFACE LATCHES 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................................................. –65°C to +150°C Ambient Temperature with Power Applied ................................. -40°C to +85°C Supply Voltage to Ground Potential (Inputs & Vcc Only) .......... –0.5V to +7.0V Supply Voltage to Ground Potential (Outputs & D/O Only) ....... –0.5V to +7.0V DC Input Voltage ......................................................................... –0.5V to +7.0V DC Output Current ................................................................................... 120 mA Power Dissipation ......................................................................................... 0.5W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 5.0V ± 5%) Parameters Description Test Conditions(1) Min. Typ(2) Max. Units VOH Output HIGH Voltage VCC = Min., VIN = VIH or VIL IOH = –15.0 mA 2.4 3.0 V VOL Output LOW Current VCC = Min., VIN = VIH or VIL IOL = 48 mA 0.3 0.50 V VOL Output LOW Current VCC = Min., VIN = VIH or VIL IOL = 12 mA (25Ω Series) 0.3 0.50 V VIH Input HIGH Voltage Guaranteed Logic HIGH Level VIL Input LOW Voltage Guaranteed Logic LOW Level IIH Input HIGH Current VCC = Max. IIL Input LOW Current IOZH High Impedance IOZL Output Current VIK Clamp Diode Voltage VCC = Min., IIN = –18 mA IOFF Power Down Disable VCC = GND, VOUT = 4.5V IOS Short Circuit Current VCC = Max.(3), VOUT = GND VH Input Hysteresis 2.0 V 0.8 V VIN = VCC 1 µA VCC = Max. VIN = GND –1 µA VCC = MAX. VOUT = 2.7V 1 µA VOUT = 0.5V –1 µA –0.7 –1.2 V — — 100 µA –60 –120 mA 200 mV Capacitance (TA = 25°C, f = 1 MHz) Parameters(4) Description Test Conditions Typ Max. Units CIN Input Capacitance VIN = 0V 6 10 pF COUT Output Capacitance VOUT = 0V 8 12 pF Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is determined by device characterization but is not production tested. 3 PS2025A 03/11/96 PI74FCT841T/843T/845T (25Ω SERIES) P174FCT2841T BUS INTERFACE LATCHES 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Power Supply Characteristics Test Conditions(1) Parameters Description Min. Typ(2) Max. Units ICC Quiescent Power Supply Current VCC = Max. VIN = GND or VCC 0.1 500 µA ∆ICC Supply Current per Input @ TTL HIGH VCC = Max. VIN = 3.4V(3) 0.5 2.0 mA ICCD Supply Current per Input per MHz(4) VCC = Max., Outputs Open OE = GND; LE = Vcc One Input Toggling 50% Duty Cycle VIN = VCC VIN = GND 0.15 0.25 mA/ MHz IC Total Power Supply Current(6) VCC = Max., Outputs Open fCP = 10 MHZ 50% Duty Cycle OE = GND; LE = Vcc fI = 5 MHZ One Bit Toggling VCC = Max., Outputs Open fCP = 10 MHZ 50% Duty Cycle OE = GND; LE = Vcc Eight Bits Toggling fI = 2.5 MHZ 50% Duty Cycle VIN = VCC VIN = GND 1.5 3.5(5) mA VIN = 3.4V VIN = GND 1.8 4.5(5) VIN = VCC VIN = GND 3.0 6.0(5) VIN = 3.4V VIN = GND 5.0 14.0(5) Notes: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device. 2. Typical values are at Vcc = 5.0V, +25°C ambient. 3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested. 6. IC =IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fINI) ICC = Quiescent Current ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fI = Input Frequency NI = Number of Inputs at fI All currents are in milliamps and all frequencies are in megahertz. 4 PS2025A 03/11/96 PI74FCT841T/843T/845T (25Ω SERIES) P174FCT2841T BUS INTERFACE LATCHES 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI74FCT841/2841T Switching Characteristics over Operating Range 841AT/2841AT 841BT/2841BT Com. Parameters tPLH tPHL tSU tH tPLH tPHL tW tPZH tPZL tPHZ tPLZ Description Propagation Delay DN to YN (LE = HIGH) Setup Time Data to LE Hold Time Data to LE Propagation Delay LE to YN LE Pulse Width(3) (HIGH) Output Enable Time OE to YN Output Disable Time(3) OE to YN Conditions(1) CL = 50 pF RL = 500Ω CL = 300 pF(3) RL = 500Ω CL = 50 pF RL = 500Ω CL = 50 pF RL = 500Ω CL = 300 pF(3) RL = 500Ω CL = 50 pF RL = 500Ω CL = 50 pF RL = 500Ω CL = 300 pF(3) RL = 500Ω CL = 50 pF RL = 500Ω CL = 5 pF(3) RL = 500Ω 841CT/2841CT Com. Com. Min Max Min Max Min Max Unit 1.5 9.0 1.5 6.5 1.5 5.5 ns 1.5 8.0 1.5 13.0 1.5 13.0 ns 2.5 — 2.5 — 2.5 — ns 2.5 — 2.5 — 2.5 — ns 1.5 12.0 1.5 8.0 1.5 6.4 ns — 16.0 — 15.5 — 15.0 ns 4.0 — 4.0 — 4.0 — ns 1.5 10.0 1.5 8.0 1.5 6.5 ns 1.5 23.0 1.5 14.0 1.5 12.0 ns 1.5 7.0 1.5 6.0 1.5 5.7 ns 1.5 8.0 1.5 7.0 1.5 6.0 ns Notes: 1. See test circuit and wave forms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not production tested. 5 PS2025A 03/11/96 PI74FCT841T/843T/845T (25Ω SERIES) P174FCT2841T BUS INTERFACE LATCHES 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI74FCT843T Switching Characteristics over Operating Range 843AT 843BT Com. Parameters tPLH tPHL tSU tH tPLH tPHL tPLH tREM tPLH tREM tW tW tW tPZH tPZL tPHZ tPLZ Description Propagation Delay DN to YN (LE = HIGH) Setup Time Data to LE Hold Time Data to LE Propagation Delay LE to YN Propagation Delay PRE to YN Recovery Time PRE to YN Propagation Delay CLR to YN Recovery Time(3) CLR to YN LE Pulse Width(3) (HIGH) PRE Pulse Width(3) (LOW) CLR Pulse Width(3) (LOW) Output Enable Time OE to YN Output Disable Time(3) OE to YN Conditions(1) CL = 50 pF RL = 500Ω CL = 300 pF(3) RL = 500Ω CL = 50 pF RL = 500Ω CL = 50 pF RL = 500Ω CL = 300 pF(3) RL = 500Ω CL = 50 pF RL = 500Ω CL = 50 pF RL = 500Ω CL = 300 pF(3) RL = 500Ω CL = 50 pF RL = 500Ω CL = 5 pF(3) RL = 500Ω 843CT Com. Com. Min Max Min Max Min Max Unit 1.5 9.0 1.5 6.5 1.5 5.5 ns 1.5 8.0 1.5 13.0 1.5 13.0 ns 2.5 — 2.5 — 2.5 — ns 2.5 — 2.5 — 2.5 — ns 1.5 12.0 1.5 8.0 1.5 6.4 ns 1.5 16.0 1.5 15.5 1.5 15.0 ns 1.5 11.0 1.5 8.0 1.5 7.0 ns 1.5 11.0 1.5 10.0 1.5 9.0 ns 1.5 11.0 1.5 10.0 1.5 9.0 ns 1.5 13.0 1.5 10.0 1.5 9.0 ns 4.0 5.0 4.0 1.5 — — — 10.0 4.0 4.0 4.0 1.5 — — — 8.0 4.0 4.0 4.0 1.5 — — — 6.5 ns ns ns ns 1.5 23.0 1.5 14.0 1.5 12.0 ns 1.5 7.0 1.5 6.5 1.5 5.7 ns 1.5 8.0 1.5 7.0 1.5 6.0 ns Notes: 1. See test circuit and wave forms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not production tested. 6 PS2025A 03/11/96 PI74FCT841T/843T/845T (25Ω SERIES) P174FCT2841T BUS INTERFACE LATCHES 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI74FCT845T Switching Characteristics over Operating Range 845AT 845BT Com. Parameters tPLH t PHL tSU tH tPLH tPHL tPLH tREM tPLH tREM tW tW tW tPZH tPZL tPHZ tPLZ Description Propagation Delay DN to YN (LE = HIGH) Setup Time Data to LE Hold Time Data to LE Propagation Delay LE to YN Propagation Delay PRE to YN Recovery Time(3) PRE to YN Propagation Delay CLR to YN Recovery Time(3) CLR to YN LE Pulse Width(3) (HIGH) PRE Pulse Width(3) (LOW) CLR Pulse Width(3) (LOW) Output Enable Time OE to YN Output Disable Time(3) OE to YN Conditions(1) CL = 50 pF RL = 500Ω CL = 300 pF(3) RL = 500Ω CL = 50 pF RL = 500Ω CL = 50 pF RL = 500Ω CL = 300 pF(3) RL = 500Ω CL = 50 pF RL = 500Ω CL = 50 pF RL = 500Ω CL = 300 pF(3) RL = 500Ω CL = 50 pF RL = 500Ω CL = 5 pF(3) 845CT Com. Com. Min Max Min Max Min Max Unit 1.5 9.0 1.5 6.5 1.5 5.5 ns 1.5 8.0 1.5 13.0 1.5 13.0 ns 2.5 — 2.5 — 2.5 — ns 2.5 — 2.5 — 2.5 — ns 1.5 12.0 1.5 8.0 1.5 6.4 ns 1.5 16.0 1.5 15.5 1.5 15.0 ns 1.5 11.0 1.5 8.0 1.5 7.0 ns 1.5 11.0 1.5 10.0 1.5 9.0 ns 1.5 11.0 1.5 10.0 1.5 9.0 ns 1.5 13.0 1.5 10.0 1.5 9.0 ns 4.0 5.0 4.0 1.5 — — — 10.0 4.0 4.0 4.0 1.5 — — — 8.0 4.0 4.0 4.0 1.5 — — — 6.5 ns ns ns ns 1.5 23.0 1.5 14.0 1.5 12.0 ns 1.5 7.0 1.5 6.5 1.5 5.7 ns 1.5 8.0 1.5 7.0 1.5 6.0 ns RL = 500Ω Notes: 1. See test circuit and wave forms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not production tested. Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 7 PS2025A 03/11/96