MQ312-03 Application Manual Real Time Clock Module RTC-4701 In pursuit of "Saving" Technology ,Epson electronic device. Our Lineup of semiconductors, Liquid crystal displays and quartz devices assists in creating the products of our customers' dreams. Epson IS energy savings. NOTICE • No part of this material may be reproduced or duplicated in any form or any means without the written permission of Seiko Epson. • Seiko Epson reserves the right to make changes to this material without notice. • Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. • Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. • This material of portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of international Trade and industry or other approval from another government agency. CONTENTS OVERVIEW ......................................................................................................................................................... 1 BLOCK DIAGRAM.............................................................................................................................................. 1 TERMINAL DESCRIPTION ................................................................................................................................ 2 CHARACTERISTICS .......................................................................................................................................... 3 1. ABSOLUTE MAXIMUM RATINGS ........................................................................................................................ 3 2. OPERATING CONDITIONS ................................................................................................................................ 3 3. OSCILLATION CHARACTERISTICS .................................................................................................................... 3 4. DC CHARACTERISTICS ................................................................................................................................... 3 5. TEMPERATURE SENSOR CHARACTERISTICS..................................................................................................... 4 6. AC CHARACTERISTICS ................................................................................................................................... 5 REGISTERS........................................................................................................................................................ 6 1. REGISTER TABLE ........................................................................................................................................... 6 2. CLOCK AND CALENDAR REGISTERS (SAME IN BANK 0 AND BANK1 : REG-0 TO REG-6 )..................................... 7 3. ALARM REGISTERS (SAME IN BANK 0 AND BANK1: REG-7 TO REG-A ) ............................................................ 8 4. TIMER COUNTER AND CONTROL REGISTER 1 ( BANK 0 : REG-C TO REG-E )..................................................... 8 5. CONTROL REGISTER ( BANK 0 : REG-F ) ....................................................................................................... 9 6. ADDITIONAL COUNTER ( BANK1 : REG-B,C )................................................................................................. 10 7. CONTROL REGISTER 3 (BANK 1 : REG-F) ..................................................................................................... 11 HOW TO USE ................................................................................................................................................... 12 1. READ/WRITE OF DATA .................................................................................................................................. 12 2. ALARM INTERRUPT....................................................................................................................................... 13 3. TIMER INTERRUPT ....................................................................................................................................... 14 4. FOE START FUNCTION ................................................................................................................................. 16 EXTERNAL CONNECTION EXAMPLE ........................................................................................................... 16 MIGRATING TO BACKUP, AND RETURNING ............................................................................................... 17 EXTERNAL DIMENSION.................................................................................................................................. 18 MARKING LAYOUT ......................................................................................................................................... 18 REFERENCE DATA ......................................................................................................................................... 19 APPLICATION NOTES..................................................................................................................................... 20 1. NOTES ON HANDLING ................................................................................................................................... 20 2. NOTES ON PACKAGING................................................................................................................................. 20 Serial RTC module with alarm and timer function RTC - 4701JE • Built-in 32.768 kHz crystal oscillator with frequency adjusted • Alarm interrupt function for day of week, day, hour, and minute • Timer interrupt function which can be set up between 1/4096 second and 255 minutes • OVF interrupt function based on 12-bit additional counter • Ability to detect stopping of oscillation and time update • Automatic adjustment for leap year • Built-in temperature sensor ( voltage output : -7.6 mV/°C Typ.) • Wide range of interface voltage between 1.6 and 5.5 V • Wide range of clock voltage between 1.6 and 5.5 V • Low power consumption at 0.5 µA / 3 V (Typ.) • Available as small package ( JE : VSOJ-20 pin ) Overview This module is a serial interface real time clock that has a built-in crystal oscillator. The module offers many functions such as clock & calendar circuitry with automatic leap year adjustment (from seconds to year), additional counter, alarm, Timer interrupt, stopping of oscillation, and time update. In addition, it is equipped with a diode temperature sensor (analog voltage output). The serial interface can be controlled by three signal lines, and it saves the port which a system uses most. Because it is available in small package VSOJ in high density mounting, it is ideally suited for applications such as mobile phones, handy terminals or other small electronic systems. Block diagram Control Line 32.768 kHz OSC DIVIDER CLOCK and VTEMP / SOFF CALENDAR Temperature Sensor FOUT FOUT FOE CONTROLLER TIMER REGISTER / AIRQ INTERRUPTS ALARM REGISTER / TIRQ CONTROLLER CONTROL REGISTER DATA BUS CLK INTERFACE CE CIRCUIT Page - 1 and SYSTEM CONTROLLER MQ312-03 Terminal description RTC - 4701JE 20. N.C. 1. VDD 19. N.C. 2. FOUT 1 3. C E 20 4. / AIRQ 18. N.C. 5. / TIRQ 17. N.C. 16. N.C. 6. CLK 15. N.C. 7. DATA 14. N.C. 10 8. FOE 11 9. VTEMP 10. / SOFF 13. N.C. 12. N.C. VSOJ - 20pin 11. GND Signal name VDD Pin number 1 I/O - FOUT 2 Output CE 3 Input / AIRQ 4 Output This is an open drain output pin for alarm and additional counter interrupt. / TIRQ 5 Output This is an open drain output pin for Timer interrupt. CLK 6 Input DATA 7 FOE 8 Input VTEMP 9 Output / SOFF 10 GND 11 N.C. 12 - 20 Signal description This pin connects to the plus side of the power. This pin outputs the clock signal of frequency. (32.768 kHz CMOS output). Depending on the FOE input pin, output from the FOUT pin can be prohibited. This is a chip enabled input pin with the builit-in pull-down resistance. When the CE pin is at the "H" level, access to this RTC becomes possible. When the CE pin is at the "L" level, the DATA pin is at the high impedance level and the CLK and DATA pins cannot accept input. This is a shift clock input pin for serial data transmission. In the write mode, it takes in data from the DATA pin using the CLK signal rise edge. In the read mode, it outputs data from the DATA pin using the fall edge. This is a data input/output pin for serial data transmission. After the input rise Bi-directional of CE, by using the first 8-bit write data to set the write or read mode, this pin can be set as either input pin or output pin. Input This is the input pin for the FOUT output control. When the FOE pin is at the "H" level, the FOUT pin goes into the output state; when it is at the "L" level, the FOUT pin is at the high impedance level. This is the voltage output pin for the temperature sensor (analog). This is the input pin for the temperature sensor control. When the /SOFF pin is at the "H" level and the SON bit is 1, the temperature sensor circuitry starts and outputs a voltage according to the temperature of the VTEMP pin. When the /SOFF pin is at the "L" level, the temperature sensor circuitry stops and the VTEMP pin is at the high impedance level. This pin connects to the minus side (ground) of the power. This pin is not connected internally. Use OPEN, or GND or VDD to connect. * Be sure to connect a filter capacity of at least 0.1 µF close to VDD - GND. Page - 2 MQ312-03 Characteristics 1. Absolute maximum ratings Parameter Power voltage Input voltage Output voltage 1 Output voltage 2 Storage temperature 2. Symbol VDD VIN VOUT1 VOUT2 TSTG Condition input pin /AIRQ , /TIRQ pins FOUT,DATA pins - Symbol VDD VCLK TOPR Condition - Rating - 0.3 to +7.0 GND-0.3 to VDD+0.3 GND-0.3 to +8.0 GND-0.3 to VDD+0.3 - 55 to +125 Operating conditions Parameter Power voltage Clock voltage Operating temperature Rating 1.6 to 5.5 1.6 to 5.5 - 40 to +85 GND=0 V Unit V V V V °C GND=0 V Unit V V °C 3. Oscillation characteristics Parameter Symbol Condition Frequency stability Ta=+25 °C, VDD=3.0 V ∆f / fo Oscillation start time tSTA Ta=+25 °C, VDD=3.0 V Frequency temperature Top -10 to +70 °C, +25 °C standard characteristics Frequency voltage f/V Ta=+25 °C, VDD=1.6 to 5.5 V characteristics Aging fa Ta=+25 °C, VDD=3.0 V * Equivalent to 1 minute of monthly deviation 4. DC characteristics Parameter Current consumption (1) Current consumption (2) Current consumption (3) Current consumption (4) Current consumption (5) Current consumption (6) Current consumption (7) Current consumption (8) Input voltage Input leakage current Input resistance (1) Input resistance (2) Output voltage (1) Output voltage (2) Output leakage current Symbol IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 IDD7 IDD8 VIH VIL ILK RDWN1 RDWN2 VOH1 VOH2 VOH3 VOL1 VOL2 VOL3 VOL4 VOL5 IOZ Rating -6 5 ± 23 × 10 * 3 ( Max. ) -6 +10 / -120 × 10 Unit s ± 2.0 × 10 -6 /V ± 5.0 × 10 -6 /year If not specifically indicated, GND=0 V, VDD=1.6 to 5.5 V, Ta=-40 to +85 °C Condition Min. Typ. Max. Unit VDD=5 V CE,FOE,/SOFF = GND 1.0 2.0 µA /AIRQ,/TIRQ = VDD VDD=3 V 32.768 kHz output is OFF 0.5 1.0 µA Sensor output is OFF VDD=5 V, CE, /SOFF = GND 3.0 7.5 µA CL=0 pF VDD=3 V, 1.7 4.5 FOE,/AIRQ,/TIRQ = VDD µA CL=0 pF VDD=5 V, 32.768 kHz output is ON 8.0 20.0 µA CL=30 pF VDD=3 V, Sensor output is OFF 5.0 12.0 µA CL=30 pF VDD=5 V CE,FOE,/SOFF = GND 50 75 µA /AIRQ,/TIRQ = VDD VDD=3 V 32.768 kHz output is OFF 40 60 µA Sensor output is ON Input pin 0.8VDD VDD V 0 0.2VDD V Input Pin except CE. VIN= VDD or GND -0.5 0.5 µA VDD=5 V CE pin 75 150 300 kΩ VDD=3 V VIN=VDD 150 300 600 kΩ VDD=5 V, IOH=-1 mA DATA,FOUT pins 4.5 5.0 V VDD=3 V, IOH=-1 mA 2.0 3.0 V 2.9 3.0 V VDD=3 V, IOH=-100 µA VDD=5 V, IOL=1 mA DATA,FOUT pins GND GND+0.5 V VDD=3 V, IOL=1 mA GND GND+0.8 V GND GND+0.1 V VDD=3 V, IOL=100 µA VDD=5 V, IOL=1 mA /AIRQ, /TIRQ pins GND GND+0.25 V VDD=3 V, IOL=1 mA GND GND+0.4 V Output pins other than VTEMP -0.5 0.5 µA VOUT= VDD or GND Page - 3 MQ312-03 5. Temperature sensor characteristics TACR VSE If not specifically indicated, GND=0 V, Ta=-40 to +85 °C Condition Min. Typ. Max. Unit 1.48 V Ta=+25 °C , GND based output voltage VTEMP pin , VDD=2.7 to 5.5 V Ta=+25 °C , VDD=2.7 to 5.5 V ± 5.0 °C - 7.1 - 7.6 - 8.1 -40 °C ≤ Ta ≤ +85 °C , VDD=2.7 to 5.5 V mV/°C ∆NL TSOP -40 °C ≤ Ta ≤ +85 °C , VDD=2.7 to 5.5 V VDD=2.7 to 5.5 V Parameter Temperature output voltage Output precision Temperature sensitivity Linearity Temperature detection range Output resistance Symbol VTEMP Load condition CL RL Response time RO tRSP ♦Temperature sensitivity ♦Linearity ∆NL = - 40 Ta=+25 °C , VTEMP pin , VDD=2.7 to 5.5 V GND standard and VDD standard VDD=2.7 to 5.5 V 1.0 ± 2.0 + 85 % °C 3.0 kΩ 100 pF kΩ µs 500 200 VDD=3.0 V, CL=100 pF, RL=500 kΩ , within ±1 °C VSE = ( V ( 85 °C) - V ( -40 °C ) ) / 125 ( mV/ °C ) a x 100 (%) b a : Maximum deviation between the measured value of VTEMP and the approximate straight line b : Difference between the measured values at -40 and +85 °C VTEMP a [V] V(-40 °C) a Approximate straight line Output voltage b Measured value a V(85 °C) Ta -40 0 85 Temperature Output resistance ( Ro ) [°C] Ro = ∆V1 / ∆I1 RTC 1 MΩ VTEMP I1 OP. AMP. V1 Page - 4 MQ312-03 6. AC characteristics Parameter Symbol Condition CLK clock cycle CLK H pulse width CLK L pulse width CE setup time CE hold time CE recovery time Write data setup time Write data hold time Write data disable time Output mode switching time Read data delay time Output disable time tCLK t WH t WL tCS tCH tCR tDS tDH tWZ tDO tRD tRZ Input rise/fall time FOUT duty Oscillation detection time CL=50 pF CL=50 pF RL=10 kΩ tRF Duty tOSC If not specifically indicated, GND=0 V, Ta=-40 to +85 °C Unit VDD=3 V±10 % VDD=5 V±10 % Min. Typ. Max. Min. Typ. Max. 600 350 ns 300 175 ns 300 175 ns 300 175 ns 300 175 ns 400 300 ns 75 50 ns 75 50 ns 0 0 ns 0 0 ns 300 120 ns 200 100 ns 100 60 40 10 50 60 40 10 ns % ms Timing chart CE 50 % t CS t WH t WL t RF t RF t CH t CR 90 % CLK • Data Write DATA 10 % t DS t DH D0 D1 D6 D7 D0 (Setup code, setup address) • Data Read D6 D7 (Write data) t DO t RZ t WZ 90 % DATA D0 D1 D6 D7 D0 D6 D7 10 % t RD (Read data) (Setup code, setup address) Page - 5 Starting from here the DATA pin goes into the output mode. MQ312-03 Registers 1. Register table Bank 0 Address 0 1 Function second minute bit 7 fos fr bit 6 40 40 bit 5 20 20 bit 4 10 10 bit 3 8 8 bit 2 4 4 bit 1 2 2 bit 0 1 1 Read Write permitted permitted 2 hour fr • 20 10 8 4 2 1 permitted 3 day of week fr 6 5 4 3 2 1 0 permitted 4 day fr • 20 10 8 4 2 1 permitted 5 month fr C • 10 8 4 2 1 permitted 6 7 8 9 A B C D E F year minute alarm hour alarm day of week alarm day alarm Timer setup Timer counter control 1 control 2 80 AE AE AE AE TE 128 • • 4 4 4 2 4 * 4 TF • 2 2 2 1 2 * 2 AIE • 1 1 1 0 1 * 1 TIE • permitted permitted permitted permitted permitted permitted permitted permitted permitted permitted only bit 7 not permitted only bit 7 not permitted only bit 7 not permitted only bit 7 not permitted only bit 7 not permitted permitted permitted permitted permitted permitted permitted permitted permitted (note 3) permitted (note 6) Address 0 1 Function second minute bit 7 fos fr bit 6 40 40 bit 5 20 20 bit 4 10 10 bit 3 8 8 bit 2 4 4 bit 1 2 2 bit 0 1 1 Read Write permitted permitted 2 hour fr • 20 10 8 4 2 1 permitted 3 day of week fr 6 5 4 3 2 1 0 permitted 4 day fr • 20 10 8 4 2 1 permitted 5 month fr C • 10 8 4 2 1 permitted 6 7 8 9 A B C year minute alarm hour alarm day of week alarm day alarm additional counter 1 additional counter 2 80 AE AE AE AE 128 fr 40 40 * 6 * 64 AC1 20 20 20 5 20 32 AC0 10 10 10 4 10 16 OVF 2 2 2 1 2 2 512 1 1 1 0 1 1 256 permitted permitted permitted permitted permitted permitted permitted only bit 7 not permitted only bit 7 not permitted only bit 7 not permitted only bit 7 not permitted only bit 7 not permitted permitted permitted permitted permitted permitted permitted D E F control 3 - - ACIE ACE SON 40 20 10 8 40 20 10 8 * 20 10 8 6 5 4 3 * 20 10 8 * TD1 TD0 * 64 32 16 8 TI/TP AF • • TEST STOP RESET HOLD Bank 1 FOES TEST 8 4 8 4 8 4 3 2 8 4 8 4 2048 1024 - permitted only bit 7 not permitted permitted permitted (note 6) Note 1. Registers 0A are the same in Bank 0 and, Bank 1. Access to Bank 0 and Bank 1 are specified by the first 4 bits in the serial communication. Mode Bank 0 Bank 1 Write 3h 1h Read Ch 8h Note 2. At the initial power supply, the FOES, ACE, and SON bits are reset to 0. For the other bits, because their register values are not fixed, be sure to initialize them before use. During the initialization, do not use data other than date and time; otherwise there is no guarantee that the clock will operate. Note 3. Write is possible only when the AF, TF, and OVF bits are 0. Note 4. For bits indicated with " - ", write cannot be performed and the read-out value is not fixed. For bits indicated with " • ", after initialization use them at 0. Note 5. For bits indicated with " * ", they can be used as memory. Note 6. The TEST bit is reserved for testing work by EPSON. Be sure to it to 0 before use. Note 7. When the Timer counter (Bank 0,Address D) is read, the data value preset previously can be read. Page - 6 MQ312-03 2. Clock and calendar registers ( Same in Bank 0 and Bank1 : Reg-0 to Reg-6 ) ∙ Data is in the BCD format. For example, if the second register is "0101 1001", this means 59 seconds. The time measurement uses the 24-hour format (fixed). ∙ If the alarm interrupt is not used, registers 7 to A can be used as 7-bit memory register. In this case, be sure to set the AIE(Alarm Interrupt Enable) bit to 0 and forbid use of the alarm interrupt. ∙ If the Timer interrupt is not used, register D can be used as an 8-bit memory register. In this case, be sure to set the TIE (Timer Interrupt Enable) bit to 0 and forbid use of the Timer interrupt. ∙ Year register and leap year, and year-digit carry bits If the year register's 2-digit BCD is divided by four and the remainder is 0, this year is determined as the leap year. This works automatically for both the Western calendar as well as the Japanese Heisei calendar. (Year 00 is taken as a leap year.) Also, for the year register, 99 is followed by 00. At this time, the year-digit carry bit C (bit 6 of register 5) is set to 1. ∙ Day of week register The day of week register makes use of the 7 bits from 0 to 6. The bits are assigned as shown in the following table. Be sure not to set multiple days of week to 1. Bit 6 0 0 0 0 0 0 1 bit 5 0 0 0 0 0 1 0 bit 4 0 0 0 0 1 0 0 bit 3 0 0 0 1 0 0 0 bit 2 0 0 1 0 0 0 0 bit 1 0 1 0 0 0 0 0 bit 0 1 0 0 0 0 0 0 Day of week Sunday Monday Tuesday Wednesday Thursday Friday Saturday ∙ fos ( OSC Flag ) This flag is a bit for recording when the oscillation stops. This bit is used to detect when decrease in the power voltage causes the oscillation to stop. 1 indicates oscillation has stopped and this information is kept until 0 is written to it. This flag is not affected even when other bits (STOP, RESET) are 1. ∙ fr ( READ Flag ) This flag is a bit which becomes 0 when the RTC is set to the non-selection state (CE input pin becomes "L"), or 1 when the RTC is set to the selection state (CE becomes "H") during which there is a 1 second digit increase. Because of this characteristic, it becomes possible to determine whether a 1 second digit increase has occurred during read-out of the clock register. If fr is 1, it becomes necessary to read all the clock registers again. ∙ C (Year-digit Carry bit in register5.) When the year register advances from 99 to 00, if 0 is written to the value before the advance in year, this bit is set to 1. Even thought the year register of this RTC uses the lower 2 digits of the Western calendar, by looking at the year-digit carry bit, it becomes possible to handle the upper two digits of the Western calendar also. For example, the year-digit carry bit can be used to handle the four-digit year value in a way so that if it is 0, the upper two digits are considered as 19, or if it is 1 the upper two digits are considered as 20. Page - 7 MQ312-03 3. Alarm registers (Same in Bank 0 and Bank1: Reg-7 to Reg-A ) Alarm can be set to day of week, day, hour, or minute. Each of the respective alarm register has the AE bit (Alarm Enable bit) attached to bit 7. By taking advantage of this bit, the hourly alarm and daily alarm can easily be set up. The day of week alarm can be set to any multiple days of the week. When the AE bit is 0, the appropriate register and the clock register are compared; when the bit is 1, this means "don't care" and the data is ignored and the two are regarded as the same. When the alarm goes off, the AF (Alarm Flag) bit is set to 1; if at this moment the AIE (Alarm Interrupt Enable) bit is 1, the /ATIRQ pin is set to the low level and the interrupt signal occurs. If the AIE bit is 0, the alarm interrupt output from the /AIRQ pin will be prohibited. The relationship between the day of week alarm bit and each day of the week is shown as follows: bit Day of week bit 6 Saturday bit 5 Friday bit 4 bit 3 Thursday Wednesday bit 2 Tuesday bit 1 Monday bit 0 Sunday 4. Timer counter and control register 1 ( Bank 0 : Reg-C to Reg-E ) Address C D E bit 7 TE 128 • bit 6 * 64 • bit 5 TD1 32 • bit 4 TD0 16 TI/TP bit 3 * 8 AF bit 2 * 4 TF bit 1 * 2 AIE bit 0 * 1 TIE This is the register for controlling the presettable down counter of the 8 bits used during the Timer interrupt. TD0 and TD1 of Reg-C specify the count cycle of the down counter (source clock), and Reg-D specifies the preset value (split cycle) of this down counter. When the TE bit becomes 0, the presettable counter loads the content of the Timer counter and stops the counting. When the TE bit becomes 1, counting starts. During a source clock cycle, the down counter continues the countdown and when the data becomes zero, the TF (Timer Flag) is set to 1. At this moment, if the TIE (Timer Interrupt Enable) bit of Reg-E is 1 the /TIRQ pin is set to the low level and the interrupt signal occurs. When the TIE bit of becomes 0, output from the /TIRQ pin is prohibited. Also, when the TI/TP bit is 1, it reloads the data of the Timer counter register and then starts the countdown again (a repeat operation). On the other hand, when the TE bit is 1, even if the Timer counter (Reg-D) is set with the 0 data, the Timer interrupt from the /TIRQ pin does not occur. In order to operate the Timer as planned, it is necessary to set up the TE, TI/TP and TIE bits. • Timer interrupt and source clock selection TD1 TD0 Source clock 0 0 4096 Hz 0 1 64 Hz 1 0 Update in seconds 1 1 Update in minutes • Timer interrupt interval Timer counter setting value 4096 Hz 0 1 2 3 • • • 255 244.14 µs 488.28 µs 732.42 µs • • • 62.26 ms Source clock 64 Hz 15.625 ms 31.25 ms 46.875 ms • • • 3.984 s Update in seconds 1s 2s 3s • • • 255 s Update in minutes 1 min 2 min 3 min • • • 255 min ∙ TE bit: ( Timer Enable ) When the TE bit is set to 1, the presettable counter starts the countdown. When this bit becomes 0, the presettable counter stops the countdown. ∙ TI / TP bit: ( Interrupt Signal Output Mode Select. Interrupt / Periodic ) This bit sets up the output mode of the Timer interrupt signal. Page - 8 MQ312-03 TI / TP Function 0 Level interrupt mode As soon as the Timer interrupt occurs, the /TIRQ pin becomes “L” and the TF bit becomes 1. The /TIRQ pin remains at “L” until 0 is written to the TF bit. (However TIE=1) 1 Repeat interrupt mode As soon as the Timer interrupt occurs, the /TIRQ pin becomes "L" (however TIE=1) and the TF bit becomes 1. Then, the /TIRQ pin automatically returns to the high impedance level, and the TF bit remains at 1 until 0 is written to it. ∙ AF and TF bits: ( Alarm Flag , Timer Flag ) When an alarm occurs the AF bit becomes 1, and the TF bit is set to 1 when the down counter for the Timer interrupt becomes zero. Data is kept until 0 is written to both bits. 1 cannot be written to both bits. ∙ AIE and TIE bits: ( Alarm , Timer Interrupt Enable ) These two bits determine whether to trigger each interrupt signal when the alarm and Timer interrupt events occur. The AIE bit controls the alarm interrupt and the TIE bit controls the Timer interrupt. 5. Control register ( Bank 0 : Reg-F ) Address F bit 7 • bit 6 TEST bit 5 STOP bit 4 RESET bit 3 HOLD bit 2 • bit 1 • bit 0 • ∙ TEST bit: this bit is reserved for testing work by EPSON. Be sure to always set this bit to 0. Be careful not to set this bit to 1 accidentally when writing to other bits of Reg-F. It can be cleared by setting the CE pin to "L". ∙ STOP bit When this bit is set to 1, the clock stops after 2 kHz of split cycle counter. When this bit becomes 0 the clock resumes. ∙ RESET bit When this bit is set to 1, the counter between 2 kHz and 1 Hz is reset and the clock also stops. After 1 is written to this bit, this can be released by setting CE to "L". This bit is not influenced by states of the other bits. ∙ HOLD bit When this bit is set to 1, second digit increase is prohibited. If second digit increase happens while this bit is set to 1, when this bit returns to 0 the automatic compensation will work to correct by one unit. It is recommended that the HOLD bit be within one second. Page - 9 MQ312-03 • Function description table STOP 0 0 0 0 1 1 1 1 Bit RESET 0 0 1 1 0 0 1 1 HOLD 0 1 0 1 0 1 0 1 Clock runs *1 stops stops stops stops stops stops Alarm runs stops stops stops stops stops stops stops Function Timer counter runs *2 *3 *3 *3 *3 *3 *3 Additional counter runs *4 stops stops stops stops stops stops stops *1 : If the deviation is within one second, the automatic compensation function will kick in to perform the automatic compensation. *2: Runs at source clock other than source clock for Timer interrupt at 1/60 Hz (1 min). *3: Runs only when the source clock for Timer interrupt is at 4096 Hz. *4: Runs only the ACE( Additional Counter Enable ) bit is 1. 6. Additional counter ( Bank1 : Reg-B,C ) Address B C bit 7 128 fr bit 6 64 AC1 bit 5 32 AC0 bit 4 16 OVF bit 3 8 2048 bit 2 4 1024 bit 1 2 512 bit 0 1 256 This is a 12-bit presettable count-up counter. After the initial value is set, when the ACE (Additional Counter Enable) bit of control register 3 is set to 1, at the timing of the source clock selected at the AC0 and AC1 bits of Reg-C, count-up continues as long as the ACE bit is 1. When the above Additional counter overflows (FFFh -> 000h), the OVF bit becomes 1. At this moment, if the ACIE (Additional Counter Interrupt Enable) bit of control register 3 has been set to 1, it is possible to trigger the additional counter overflow interrupt at the /AIRQ pin. As long as the count-up operation is not stopped by the register operation, the clock operation continues even if the RTC is in the non-selection state (during backup), and interrupt from this state can happen. During data read of the additional counter, if the fr flag is 1, this indicates the counter has been updated during the read operation; therefore it is necessary to read the counter data again. Also, if 16 Hz is selected for the source clock, because the update timing cannot be caught at the fr flag when the counter is operating, an update check with data read at 2 times is required. However, while the counter is stopping, such data read at 2 times is not required. By using the additional counter function, time lapse measurement, various cooking Timer operations of interrupt after n minutes, and long Timer can be made possible. • additional counter and source clock selection AC1 AC0 Source clock 0 0 16 Hz 0 1 Update in seconds 1 0 Update in minutes 1 1 Update in hours Possible count range 0 to 255.93 seconds 0 to 4095 seconds 0 to 4095 minutes 0 to 4095 hours Page - 10 MQ312-03 7. Control register 3 ( Bank 1 : Reg-F ) Address F bit 7 FOES bit 6 TEST bit 5 bit 4 bit 3 bit 2 ACIE bit 1 ACE bit 0 SON ∙ FOES bit: ( FOE Start Mode ) When this bit is set to 1, the additional counter will not start at the time 1 is written to the ACE( Additional Counter Enable) bit of control register 3. With the ACE bit in 1, when the FOE input pin changes from the "H" level to the "L" level (fall edge), the additional counter will start. When the FOES bit is set to 0, the additional counter will start at the time the 1 is written to the ACE( Additional Counter Enable) bit of control register 3. When the power is supplied initially, this bit is reset to 0. ∙ ACIE bit: ( Additional Counter Interrupt Enable ) This bit determines whether the interrupt signal should be generated from the /AIRQ pin when the overflow interrupt event of the additional counter occurs. When the ACIE bit is 1, the interrupt signal is generated. ∙ ACE bit: ( Additional Counter Enable ) When this bit is set to 1, the additional counter starts the count-up. When this bit is set to 0, the additional counter stops the count-up. When the power is supplied initially, this bit is reset to 0. ∙ SON bit : ( Sensor ON ) When this bit is 1 and, furthermore, the /SOFF pin is at the "H" level, the built-in temperature sensor circuitry starts and the analog voltage is output from the VTEMP pin according to the temperature. When this bit is 0, the temperature sensor circuitry stops and the VTEMP pin is at the high impedance level. When the power is supplied initially, this bit is reset to 0. Page - 11 MQ312-03 How to use 1. Read/write of data After read/write and the CE input rise, the 4-bit mode is set up and then the 4-bit address is specified. Then, data read/write in units of 8 bits is performed. If input of unit of 8-bit data is not finished before the CE input falls, the 8-bit write data will be ignored at the time CE input falls. (The previous data is undetermined.) Both read and write use LSB-First. [ Write ] 1) Take 3 or 1 as the write mode in the first four bits after the CE input rise, and set the address to write to the next four bits. 2) The next 8 bits of write data is written to the address set earlier, and the next 8 bits of data is written to the address which is automatically incremented from the last one. 3) The address is incremented automatically in a cycle where address F is followed by 0. * Example of writing to Bank0 CE CLK DATA D0 D1 D2 D3 D0 D1 D2 D3 D0 Write mode setup code (3) Setup address (N) D1 D2 D3 D4 D5 D6 D7 D0 Data write(address N) D1 D2 D3 D4 D5 D6 D7 Data write(address N+1) [ Read ] 1) Take "C" or 8 as the read mode in the first four bits after the CE input rise, and set the address to read to the next four bits. 2) The next 8 bits of read data is read from the address set earlier, and the next 8 bits of data is read from the address which is automatically incremented from the last one. 3) The address is incremented automatically in a cycle where address "F" is followed by 0. * Example of reading Bank0 CE CLK D0 DATA D1 D2 D3 D0 D1 D2 D3 Read mode setup code (C) D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Setup address Data read(address N) Data read(address N+1) From here the DATA pin turns into the output [ Write/read mode setup code of bank 0 and bank 1 ] Mode Write Read Bank 0 3h Ch Bank 1 1h 8h * In the mode setting code, if a value other than those listed above is used, the subsequent data will be ignored and the DATA pin remains in the input state. Page - 12 MQ312-03 2. Alarm interrupt When the alarm matches and AIE=1, the /AIRQ pin outputs "L"; when AIE=0, the /AIRQ pin is at the high impedance level. The alarm interrupt is output when "carry" from the 10-second digit to minute digit occurs "1" "1" "1" AIF bit The AIE bit is not output in the 0 range. "0" "0" High impedance /AIRQ output "L" level "1" AF bit "0" Alarm interrupt timing 0 is written to the AF bit. • How to use it The day of week, day, hour, and minute can be set. For day of week, multiple days can be set at a time. To avoid unintended hardware interrupt during the alarm setup, it is recommended that initially both the AF bit and AIE bit be set to 0. Then, set up the alarm data, and apply zero clear to the AF flag in order to initialize the alarm circuitry with certainty. Afterwards, set the AIE bit to 1. If no hardware interrupt is desired to be used, set the AIE bit to 0, and monitor the AF bit with software as required. • Usage example 1 ) Set the alarm to go off at 6 PM tomorrow ∙ Write 0 to the AIE bit and the AF bit. ∙ Write 1 to the AE bit of the day alarm. ∙ Get the current day of week stored in register 3 in the day of week alarm register, left shift the data by 1 bit and then perform the write operation. (Be careful with the fr bit. If bit 6 is 1 (Saturday), write 01h (Sunday).) ∙ Write 18h to the hour alarm register. ∙ Write 00h to the minute alarm register. ∙ Apply zero clear to the AF bit. ∙ Write 1 to the AIE bit. 2 ) Set the alarm to go off at 6 am everyday except Saturday and Sunday ∙ Write 0 to the AIE bit and the AF bit. ∙ Write 1 to the AE bit of the day alarm. ∙ Write 3Eh to the day of week alarm register. ∙ Write 06h to the hour alarm register. ∙ Write 00h to the minute alarm register. ∙ Apply zero clear to the AF bit. ∙ Write 1 to the AIE bit. Page - 13 MQ312-03 3. Timer interrupt By setting the TI/TP bit, it is possible to select the level interrupt mode as well as the repeat interrupt mode. ( 1 ) Level interrupt mode ( TI/TP = 0 ) If TIE=1 when interrupt occurs, the /TIRQ pin becomes "L" output; if TIE=0, the /TIRQ pin enters the high impedance state. "1" "1" "1" TIE bit The TIE bit is not output in the 0 range. "0" "0" High impedance /TIRQ output "L" level "1" TF bit "0" Interrupt timing 0 is written to the TF bit. ( 2 ) Repeat interrupt mode ( TI/TP = 1 ) When interrupt occurs, if TIE = 1, the /TIRQ pin outputs "L" When interrupt occurs, if TIE= 0, the /TIRQ pin remains at the high impedance level; only the TF pin becomes 1 and stays that way. "1" TIE bit "0" High impedance /TIRQ output t RTN "L" level Automatic return "1" TF bit "0" Interrupt timing “0” is written to the TF bit. Page - 14 MQ312-03 • Automatic return The automatic return time (tRTN) in the repeat interrupt mode is determined by the source clock specified at Reg-C. Source clock 4069 Hz 64 Hz Update in seconds Update in minutes Automatic return time (tRTN) 0.122 ms 7.81 ms 7.81 ms 7.81 ms • Timer measurement error Because the Timer error is the following range: +0 /-1 cycle time of the selected source clock, the Timer's set time falls into the (Timer's set time - source clock cycle) to (Timer's set time) Timer's set time = source clock cycle x value of the split cycle of Reg-D Also, the actual time of the Timer is the above time, plus the communication duration of the serial data transfer clock • Timer start timing In the data write mode, the Timer starts counting from the fall edge of the CLK for the TE bit in the following time chart. Address C CLK pin DATA pin TD0 TD1 * TE Internal timer /TIRQ pin Timer operation • How to use At the cycle (source clock) specified at the Timer interrupt setup register, countdown starts from the value of the Timer counter register. When the data becomes zero, the /TIRQ pin becomes "L" and interrupt occurs. It can be used as an interval Timer between a minimum of 1/4096 second to a maximum of 255 minutes. To avoid unintended hardware interrupt during the Timer setup, it is recommended that initially both the TF bit and the TIE bit be set to 0. If no regular interrupt is desired to be used, set the TIE bit to 0, and monitor the TF bit with software as required. Page - 15 MQ312-03 4. FOE start function When the FOES(FOE Start Mode) bit of control register 3 is set to 1, the additional counter function triggered by FOE starts. While this mode is selected, the additional counter does not starts when 1 is written to the ACE (Additional Counter Enable) bit of control register 3. With the ACE bit being 1, the additional counter starts when the FOE input pin changes from the "H" level to the "L" level (fall edge). After the additional counter starts, regardless of the state of the FOE pin, as long as it is not stopped by the register operation (ACE bit being 0), it will continue even if RTC is in the non-selected state. When the power is supplied initially, the FOES bit is reset to 0. FOE pin Calculation counter Counter starts Software process Counter starts ACE:"1" ACE:"0" ACE:"1" External connection example D1 Note 4.7 µF VDD SCI7701 or SCI7721 VDD Schottky Barrier Diode + RTC4701 VO VSS Voltage Detector VDD CE DATA CLK 0.1 µF / TIRQ / AIRQ FOUT FOE GND D1: 1SS108 or Equivalent Vf = 0.1 V Note : It uses the secondary battery or a lithium battery. When using the secondary battery, the diode is not required. When using the lithium battery, the diode is required. For detailed value on the resistance, please consult a battery manufacturer. Page - 16 MQ312-03 VDD and CE timing * When the power is turned to ON, use with CE="L "(VCL[V] in the diagram) as illustrated in the following timing chart. Terminal maintaining "L" is good with either one of CE0 and CE1. 1.6 V VDD tCL CE1 or VCL CE0 Item Symb ol Remark CE voltage when power is VCL CE impressed VDD=1.6 V tCL Time to maintain CE=VCL[V] until VDD=1.6 V voltage until Specificati on Unit 0.3 (Max.) V 10 (Min.) µs turned to ON CE=VCL[V] time when power is turned to ON Power Down / power Up Timing. VDD VCLK tCD tF tR tCU CE VIL VIL Backup Parameter CE time before power drop Power drop time Power rise time CE time after power rise Symbol tCD tF tR tCU Condition - Min. 0 2 1 0 Typ. Max. Unit µs µs / V µs / V µs * When main power souce input to VDD from backup condition, CE should be definitely LOW. Page - 17 MQ312-03 External dimension RTC-4701JE ( VSOJ 20-pin ) 7.0 0.3 * 5.4 6.0 0.2 1.3 1.5 Max. 0.22 0.65 0 Min. (0.75) 0.12 (0.75) 0.1 *In this area, (front, back) the crystal oscillator's cylinder may be visible. This has no influence on the characteristics of the device. Marking layout RTC-4701JE ( VSOJ 20-pin ) Type R4701 E 9146A Symbol mark Production lot Note: The above indication shows the markings and outlines their general positions. It is not a specification of the type faces, sizes, and positions of the characters. Page - 18 MQ312-03 Reference data (1) Frequency temperature characteristics example Finding the frequency stability (clock accuracy) θT = 25 °C Typ. 1. The frequency temperature characteristics can be approximated by using the following formula: ∆fT = α(θT-θX)2 ∆fT :Frequency deviation at target temperature 2 Frequency ∆ fT -6 α = -0.035 × 10 /C2 Typ. × 10-6 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 α(1/ °C ) θ T (°C) θ X (°C) :Secondary temperature coefficient 2 (-0.035±0.005 × 10-6/ ° C ) :Peak temperature (25±5 °C) :Target temperature 2. To determine the overall clock accuracy, add the frequency precision and the voltage characteristics: ∆f/f = ∆f/f0 + ∆fT + ∆fv ∆f /f ∆f /f 0 ∆f T ∆f v -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature [°C] (2) Example of the frequency/voltage characteristics Frequency ( ×10-6 ) : Clock accuracy at a given temperature and voltage (frequency stability) : Frequency precision : Temperature dependent frequency deviation : Voltage dependent frequency deviation 3. Finding the monthly deviation: -6 2 Monthly deviation = ∆f/f x 10 x 60 x 24 x 30 (seconds) -6 The clock error is 30 second per month at 11.574 x 10 (3) Example of the current consumption/voltage characteristics Condition:3 V standard and Ta=+25 ° C + 10 Current consumption (µA) Condition: During clock movement and Ta=+25 °C 10 +5 2 3 5 0 -5 5 4 Supply Voltage VDD(V) FOUT=32.768 kHz CL=30 pF FOUT=0 Hz - 10 2 3 4 5 Supply Voltage VDD[v] Page - 19 MQ312-03 Application notes 1. Notes on handling In order to enable this module to operate at low power level, the C-MOS circuitry was used in the design of the chip. Note the following cautions when handling it: ( 1 ) Static electricity While this module has built-in circuitry designed to protect it against electrostatic discharge, the chip could still be damaged by a large discharge of static electricity. Containers used for packing and transport should be constructed of conductive materials. In addition, only soldering irons, measurement circuits, and other such devices which do not leak high voltage should be used with this module, which should also be grounded when such devices are being used. ( 2 ) Noise If a signal with excessive external noise is applied to the power supply or input pins, the device may malfunction or "latch up." In order to ensure stable operation, connect a filter capacitor (preferably ceramic) of greater that 0.1 µF as close as possible to the power supply pins (between VDD and GNDs). Also, avoid placing any device that generates high level of electronic noise near this module. * Do not connect signal lines to the shaded area in the figure shown on the right and, if possible, embed this area in a GND land. ( 3 ) Voltage levels of input pins When the input pins are at the mid-level , this will cause increased current consumption and a reduced noise margin, and can impair the functioning of the device. Therefore, try as much as possible to apply the voltage level close to VDD or GND. ( 4 ) Handling unused input pins Since the input impedance of the input pins is extremely high, operating the device with these pins in the open circuit state can lead to unstable voltage level and malfunctions due to noise. Therefore, pull-up or pull-down resistors should be provided for all unused input pins. 2. Notes on packaging (1) Soldering temperature conditions If the temperature within the package exceeds 260 °C, the characteristics of the crystal oscillator will be degraded and it may be damaged. Therefore, always check the mounting temperature before mounting this device. Also, check again if the mounting conditions are later changed. * Soldering conditions of SMD products: Not higher than 260 °C for no more than twice at 10 seconds, or not higher than 230 °C for no more than 3 minutes Infrared reflow or air reflow Temperature[°C] 240 °C Max. 10 ± 1 s 250 235 ± 5 °C 200 °C 200 150 150 ± 10 °C Preliminary heating 90 ± 30 s Greater than 200 °C 30 ± 10 s 0 Time ( 2 ) Mounting equipment While this module can be used with general-purpose mounting equipment, the internal crystal oscillator may be damaged in some circumstances, depending on the equipment and conditions. Therefore, be sure to check this. In addition, if the mounting conditions are later changed, the same check should be performed again. ( 3 ) Ultrasonic cleaning Depending on the usage conditions, there is a possibility that the crystal oscillator will be damaged by resonance during ultrasonic cleaning. Since the conditions under which ultrasonic cleaning is carried out (the type of cleaner, power level, time, state of the inside of the cleaning vessel, etc.) vary widely, this device is not warranted against damage during ultrasonic cleaning. ( 4 ) Mounting orientation This device can be damaged if it is mounted in the wrong orientation. Always confirm the orientation of the device before mounting. ( 5 ) Leakage between pins Leakage between pins may occur if the power is turned on while the device has condensation or dirt on it. Make sure the device is dry and clean before supplying power to it. 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