SSI 34P3402A 8 to 53 Mbit/s Read Channel w/Adaptive Threshold Qualifier June 1998 • CMOS RDIO signal output for servo timing support The SSI 34P3402A device is a high performance BiCMOS single chip read channel IC that contains all the functions necessary to implement an adaptive threshold read channel. Functional blocks include a pulse detector with adaptive threshold qualifier, programmable filter, and data synchronizer. Raw data rates from 8 to 53 Mbit/s can be programmed by digital commands. • Internal LOW-Z and fast decay timing for rapid transient recovery and AGC acquisition • Fast decay mode is self-timed for optimal AGC recovery • 0.5 ns maximum pulse pairing with sine wave input • Independent qualification thresholds for data and timing extraction • • • 8 to 53 Mbit/s raw data rate Programmable boost of 0 to 13 dB Programmable group delay equalization (up to 38% change in group delay) Matched normal and differentiated outputs • Low power operation (<TBD mW typical @ RRC = 53 MHz and 5 V) • Programmable power management (sleep mode <1 mW ) CO N Power supply range (4.5 to 5.5 V) Small footprint 48-Pin TQFP package • Fast attack/decay modes for rapid AGC recovery • Dual rate charge pump for fast transient recovery • • • • Low drift AGC hold circuitry • Programmable pulse qualification threshold level LI Temperature compensated, exponential control AGC Less than 1% total harmonic distortion • Fully integrated data synchronizer - No external delay lines or active components required - No external active PLL components required • Selectable PLL input from adaptive threshold qualifier or traditional window qualifier • Selectable data synchronizer input from adaptive threshold qualifier or traditional window qualifier • Fast PLL acquisition phase lock loop - Zero phase restart technique - Programmable phase detector gain gear shift • Programmable decode window symmetry - Window shift control ±15% of decode window - Includes delayed read data and VCO reference monitor points PULSE DETECTOR • ±10% Fc accuracy from 10 to 16 MHz DATA SYNCHRONIZER Bi-directional serial port for access to internal registers Programmable AGC fixed gain mode SI Adaptive threshold qualifier for data extraction Traditional window qualifier for timing extraction 06/04/98 -rev. Programmable cutoff frequency of 2 to 16 MHz SY • • • • • • • ST PROGRAMMABLE FILTER The SSI 34P3402A utilizes an advanced BiCMOS process technology along with advanced circuit design techniques which result in a high performance device with low power consumption. FEATURES EM The SSI 34P3402A allows complete flexibility in read channel configuration. All critical parameters can be programmed by a microprocessor via a bi-directional serial port and a bank of internal registers. S DESCRIPTION 1 2 POWER DOWN REGISTER DT REG TDAC 4-BIT DC REG PK - PK DETECT PKP FROM S-PORT DATA REG PKN VPA AV VT REG VTH DAC 7-BIT VITERBI QUALIFIER DAC SWN SWP RESET Q R D C C R D Q R Q D C R Q C D COUT ONE SHOT RD QN RD QP SWNIN ONE SHOT MUX + PDREF MUX MUX S QN MUX SYREFP QP RD RD MUX MUX MUX ONE SWPIN SHOT + ONE SHOT EM ST SY DN CONTROL LOGIC AGC CHARGE PUMP GD REG FB REG CDAC (7-BIT) DP FULL WAVE RECTIFIER GDAC (8-BIT) CN HOLD RX BDAC (7-BIT) CP FIXED GAIN DAC FDP PROGRAMMABLE EQUALIZER FILTER DIFFERENTIATOR WINDOW QUALIFIER + SET RDIO BYPD FDN CO N FNP AIN FNN AIP LI SI SSI 34P3402A 8 to 53 Mbit/s Read Channel w/Adaptive Threshold Qualifier BLOCK DIAGRAM A LEVEL2 LEVEL RP PWRON RR IREF 3 SURVIVAL SEQUENCE REGISTER (10-BIT) CLOCK GENERATOR DVRGND2 DVRGND1 SDO RG RRC DVRVCC S EM MUX DEGLITCH ST VCO VPG DIGITAL DELAY CONTROLLER DFLN SYNCH DFLP SY CHARGE PUMP FTBG SRD VPB WS REG PHASE DETECTOR COUT MUX VPC DIGITAL DELAY RD MUX VPD SYREFP/N MUX MUX DACOUT SERIAL PORT 1/2 SYMBOL DELAY QN QP VPA PDREF MTP3 (TP) CO N MCTR MTP2 (TP) DACI 7-BIT SET MTP1 (TP) MUX MTP4 (TP) RESET SYREFP/N LI SI SSI 34P3402A 8 to 53 Mbit/s Read Channel w/Adaptive Threshold Qualifier BLOCK DIAGRAM B VNG VND VNC VNA VNB SDATA SCLK SDEN FREF