STA003T ® MPEG 2.5 LAYER III AUDIO DECODER SINGLE CHIP MPEG2 LAYER 3 DECODER SUPPORTING: - All features specified for Layer III in ISO/IEC 11172-3 (MPEG 1 Audio) except 44.1KHz Audio - All features specified for Layer III 2 channels in ISO/IEC13818-3.2 (MPEG 2 Audio) except 22.05KHz Audio - Lower sampling frequencies syntax extension, (not specified by ISO) called MPEG 2.5 except 11.025KHz Audio DECODES LAYER III STEREO CHANNELS, DUAL CHANNEL, SINGLE CHANNEL (MONO) SUPPORTING THE MPEG 1 & 2 SAMPLING FREQUENCIES AND THE EXTENSION TO MPEG 2.5: 48, 32, 24, 16, 12, 8 KHz ACCEPTS MPEG 2.5 LAYER III ELEMENTARY COMPRESSED BITSTREAM WITH DATA RATE FROM 8 Kbit/s UP TO 128 Kbit/s DIGITAL VOLUME CONTROL DIGITAL BASS & TREBLE CONTROL SERIAL BITSTREAM INPUT INTERFACE ANCILLARY DATA EXTRACTION VIA I2C INTERFACE. SERIAL PCM OUTPUT INTERFACE (I2S AND OTHER FORMATS) PLL FOR INTERNAL CLOCK AND FOR OUTPUT PCM CLOCK GENERATION LOW POWER DATA ELABORATION FOR POWER CONSUMPTION OPTIMISATION CRC CHECK AND SYNCHRONISATION ERROR DETECTION WITH SOFTWARE INDICATORS I2C CONTROL BUS LOW POWER 3.3V CMOS TECHNOLOGY 14.72MHz EXTERNAL INPUT CLOCK OR BUILT-IN XTAL OSCILLATOR January 2002 SO28 APPLICATIONS STARMAN SATELLITE RADIO RECEIVER DESCRIPTION The STA003T is a fully integrated high flexibility MPEG Layer III Audio Decoder, capable of decoding Layer III compressed elementary streams, as specified in MPEG 1 and MPEG 2 ISO standards. The device decodes also elementary streams compressed by using low sampling rates, as specified by MPEG 2.5. STA003T receives the input data through a Serial Input Interface. The decoded signal is a stereo, mono, or dual channel digital output that can be sent directly to a D/A converter, by the PCM Output Interface. This interface is software programmable to adapt the STA003T digital output to the most common DACs architectures used on the market. The functional STA003T chip partitioning is described in Fig.1. 1/32 STA003T Figure 1. BLOCK DIAGRAM: MPEG 2.5 Layer III Decoder Hardware Partitioning. SDA RESET 26 SCL 3 4 2 I C CONTROL SDI SCKR BIT_EN 5 6 7 9 SERIAL INPUT INTERFACE BUFFER PARSER CHANNEL CONFIG. & VOLUME CONTROL MPEG 2.5 LAYER III DECODER CORE SYSTEM & AUDIO CLOCKS 8 SRC_INT 28 21 VDD_5/CLK_OUT 20 XTI 10 11 SDO SCKT LRCKT TEST INTERFACE 12 XTO OUTPUT BUFFER PCM OUTPUT INTERFACE OCLK 24 25 TESTEN SCANEN D99AU1005 Figure 2. PIN CONNECTION VDD_1 1 28 VDD_5/CLK_OUT VSS_1 2 27 VSS_5 SDA 3 26 RESET SCL 4 25 SCANEN SDI 5 24 TESTEN SCKR 6 23 VDD_4 BIT_EN 7 22 VSS_4 SRC_INT 8 21 XTI SDO 9 20 XTO SCKT 10 19 FILT LRCKT 11 18 PVSS OCLK 12 17 PVDD VSS_2 13 16 VDD_3 VDD_2 14 15 VSS_3 D99AU1003 Fig. 2 describes the STA003T pinout in SO28 package THERMAL DATA Symbol Rth j-amb 2/32 Parameter Thermal resistance Junction to Ambient Value 85 Unit °C/W STA003T PIN DESCRIPTION Type 1 2 3 Pin Name VDD_1 VSS_1 SDA Type 4 5 6 7 8 9 SCL SDI SCKR BIT_EN SRC_INT SDO I I I I I O 10 11 12 SCKT LRCLKT OCLK O O I/O 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS_2 VDD_2 VSS_3 VDD_3 PVDD PVSS FILT XTO XTI VSS_4 VDD_4 TESTEN SCANEN RESET VSS_5 VDD_5/CLK_OUT I/O O O I I I I Function Supply Voltage Ground I2C Serial Data + Acknowledge I2C Serial Clock Receiver Serial Data Receiver Serial Clock Bit Enable Interrupt Line For S.R. Control Transmitter Serial Data (PCM Data) Transmitter Serial Clock Transmitter Left/Right Clock Oversampling Clock for DAC Ground Supply Voltage Ground Supply Voltage PLL Power PLL Ground PLL Filter Ext. Capacitor Conn. Crystal Output Crystal Input (Clock Input) Ground Supply Voltage Test Enable Scan Enable System Reset Ground Power/14.72MHz Buffered Output Clock PAD Description CMOS Input Pad Buffer CMOS 4mA Output Drive CMOS Input Pad Buffer CMOS Input Pad Buffer CMOS Input Pad Buffer CMOS Input Pad Buffer with pull up CMOS Input Pad Buffer CMOS 4mA Output Drive CMOS 4mA Output Drive CMOS 4mA Output Drive CMOS Input Pad Buffer CMOS 4mA Output Drive CMOS 4mA Output Drive Specific Level Input Pad (see paragraph 2.1) CMOS Input Pad Buffer with pull up CMOS Input Pad Buffer CMOS Input Pad Buffer with pull up CMOS 4mA Output Drive Note: In functional mode TESTEN must be connected to VDD, SCANEN to ground. ABSOLUTE MAXIMUM RATINGS Symbol VDD Vi VO Tstg Toper Parameter Power Supply Voltage on Input pins Voltage on output pins Storage Temperature Operative ambient temp Value -0.3 to 4 Unit V -0.3 to VDD +0.3 -0.3 to VDD +0.3 -40 to +150 -20 to +85 V V °C °C 3/32 STA003T 1. ELECTRICAL CHARACTERISTICS: VDD = 3.3V ±0.3V; Tamb = 0 to 70°C; Rg = 50Ω unless otherwise specified DC OPERATING CONDITIONS Symbol VDD Tj Parameter Value 2.7 to 3.6V Power Supply Voltage Operating Junction Temperature -20 to 125°C GENERAL INTERFACE ELECTRICAL CHARACTERISTICS Symbol Max. Unit Note IIL Low Level Input Current Without pull-up device Parameter Vi = 0V Test Condition Min. -10 Typ. 10 µA 1 IIH High Level Input Current Without pull-up device Vi = VDD -10 10 µA 1 Vesd Electrostatic Protection Leakage < 1µA V 2 2000 Note 1: The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic stress on the pin. Note 2: Human Body Model. DC ELECTRICAL CHARACTERISTICS Symbol VIL VIH Vol Voh Parameter Test Condition Min. Typ. Low Level Input Voltage High Level Input Voltage Low Level Output Voltage High Level Output Voltage Max. Unit 0.2*VDD V 0.4V V V V 0.8*VDD Iol = Xma 0.85*VDD Note 1, 2 1, 2 Note 1: Takes into account 200mV voltage drop in both supply lines. Note 2: X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability. Symbol Ipu Rpu Parameter Pull-up current Equivalent Pull-up Resistance Test Condition Vi = 0V; pin numbers 7, 24 and 26 Min. -25 Typ. -66 50 Max. -125 Unit µA kΩ Note 1 Min. Typ. 120 125 135 Max. Unit mW mW mW Note Note 1: Min. condition: VDD = 2.7V, 125°C Min process Max. condition: VDD = 3.6V, -20°C Max. POWER DISSIPATION Symbol PD 4/32 Parameter Power Dissipation @ VDD = 3V Test Condition Sampling_freq ≤24 kHz Sampling_freq ≤32 kHz Sampling_freq ≤48 kHz STA003T Figure 3. Test Circuit VDD_5/CLK_OUT 28 VDD 3 1 4 100nF 9 2 VSS VDD 10 11 14 12 100nF 5 13 VSS VDD 6 16 7 100nF VSS VDD 15 8 23 21 20 100nF 22 VSS VDD 4.7µF 18 27 100nF 26 25 RESET SDO SCKT LRCKT OCLK SDI SCKR BIT_EN SCR_INT XTI XTO 10K 24 SCANEN 4.7µF PVDD VSS SCL 19 17 PVDD SDA 1K TESTEN 470pF 4.7nF PVSS D99AU1004 PVSS PVSS Test Load Circuit Test Load VDD Output SDA IOL Other Outputs OUTPUT IOL 1mA IOH CL 100pF VREF 3.6V 100µA 100µA 100pF 1.5V VREF CL IOH D98AU967 2. FUNCTIONAL DESCRIPTION 2.1 - Clock Signal The STA003T input clock is derivated from an external source or from a 14.72 MHz crystal. Symbol VIL VIH Parameter Low Level Input Voltage High Level Input Voltage XTI is an input Pad with specific levels. Test Condition Min. VDD-0.8 Typ. Max. Unit VDD-1.8 V V CMOS compatibility The XTI pad low and high levels are CMOS compatible; XTI pad noise margin is better than typical CMOS pads. TTL compatibility The XTI pad low level is compatible with TTL while the high level is not compatible (for example if VDD = 3V TTL min high level = 2.0V while XTI min high level = 2.2V) 5/32 STA003T Figure 4. MPEG Decoder Interfaces. µP FILT XTO IIC MASTER CLK XTI SCL SRC-INT PLL SDA IIC SDI CHANNEL DECODER SDO MPEG DECODER SCKR SCKT BIT_EN DAC LRCKT SERIAL AUDIO INTERFACE RX TX OCLK D97AU665A Figure 5. Serial Input Interface Clocks DATA SDI IGNORED SCKR SCLK_POL=0 SCKR SCLK_POL=2 BIT_EN D98AU968 2.2 - Serial Input Interface STA003T receives the input data thought the Serial Input Interface (Fig.4). It is a serial communication interface connected to the SDI (Serial Data Input) and SCKR (Receiver Serial Clock). The interface can be configured to receive data sampled on both rising and falling edge of the SCKR clock.The BIT_EN pin, when set to low, forces the bitstream input interface to ignore the incoming data. The possible configurations are described in Fig. 5. The bitstream must be sent MSB first to STA003T. 2.3 - PLL & Clocks Generation System The STA003T has a clock generation system that is used by the device core to adjust the core speed, for power saving, adapting the processing speed to the needs of the decoded audio program. The clocks generation system is even used to generate all the PCM output interface clocks: SCKT, LRCKT, and OCLK. The block diagram in Fig. 6 is a description of STA003T clocks generation system. The input of 6/32 STA003T clocks system is a 14.72MHz input clock. Internally it is composed by a PLL loop, and the VCO output is fed into a divider stage, used to program the Core speed and the PCM interface clocks. Several registers are programmed by the Layer III decoder core, and by the user, when a specific interface configuration is required. The PLL can be programmed by a set of registers, as described in the I2C Registers section, The particularity of the STA003T clocks generation system is the possibility to modify the Audio Sampling Frequency (LRCKT) in steps of few ppm to compensate dynamically the audio sampling rate offset between the receiver and the broadcasting station. The compensation is done by the STA003T core without requiring interaction with the application controller and the sampling rate compensation produces a jittering effect outside the audible range. The device implements a sampling rate offset control receiving by STA002 (WorldSpace Channel Decoder) a dedicated signal every decoded Broadcast Channel Frame (432ms). STA003T Figure 6. PLL and Clocks Generation System PLLCTL_N reg XTI N PFD CP R C C PLLCTL_M reg M VCO Disable PLL OCLK Switching Circuit PLLFRAC reg MFSDF(X) reg X XTI2OCLK PLLFRAC DCLK S XTI2DSPCLK This signal is used as interrupt signal inside STA003T. Within a WorldSpace Broadcast Frame, there are a fixed number of PCM samples, depending on the nominal audio sampling rate (Fig. 7). Using this information, with the SRC_INT signal as external timer source, STA003T performs the compensation of the audio sampling rate. The sampling rate control is done by the STA003T core, by setting PLLFRAC internal register. The PLLFRAC value is updated, in steps of few ppms, by Update PLLFRAC signal. Figure 7. WorldSpace BC Framing tLOW tINT SRC_INT BC Frame Time Lenght: 432 ms MPEG Frames into 1 BC Frame: 18 for 48 & 24 KHz 12 for 32 & 16 KHz 9 for 12 KHz 6 for 8 KHz PCM Samples into 1 BC Frame: 20736 for 48 KHz 10368 for 24 KHz 13824 for 32 KHz 6912 for 16 KHz 5184 for 12 KHz 3456 for 8 KHz 7/32 STA003T 16 to 24 bits/word, by setting the output precision (16, 18, 20 and 24 bits) with PCMCONF register. Data can be output either with the most significant bit first (MS) or least significant bit first (LS), selected by writing into a flag of the PCMCONF register. Figure 8 gives a description of the STA003T PCM Output Formats. The sample rates set decoded by STA003T is described in Table 1. 2.4 - PCM Output Interface The decoded audio data are output in serial PCM format. The interface consists of the following signals: SDO PCM Serial Data Output SCKT PCM Serial Clock Output LRCLK Left/Right Channel Selection Clock The output samples precision is selectable from Figure 8. PCM Output Formats 16 SCLK Cycles LRCKT 16 SCLK Cycles 16 SCLK Cycles 16 SCLK Cycles 16 SCLK Cycles SDO M S L S M S L S M S L S M S L S PCM_ORD = 0 PCM_PREC is 16 bit mode SDO L S M S L S M S L S M S L S M S PCM_ORD = 1 PCM_PREC is 16 bit mode 32 SCLK Cycles LRCKT SDO M S SDO SDO SDO 32 SCLK Cycles 32 SCLK Cycles 32 SCLK Cycles 0 L S 0 M S M S L S MSB M S 0 M S L S L S L S 0 M S 0 L S M S MSB L S M S 0 M S 0 32 SCLK Cycles L S 0 0 0 L S M S MSB M S 0 L S M S L S M S L S 0 0 0 L S M S L S L S M S MSB PCM_FORMAT = 1 PCM_DIFF = 1 0 PCM_FORMAT = 0 PCM_DIFF = 1 0 M S PCM_FORMAT = 0 PCM_DIFF = 0 L S PCM_FORMAT = 1 PCM_DIFF = 1 Table 1: MPEG Sampling Rates (KHz) MPEG 1 48 MPEG 2 24 MPEG 2.5 12 32 16 8 2.5 - STA003T Decoding States There are three different decoder states: Idle, Init, and Decode. Commands to change the decoding states are described in the STA003T I2C registers description. Idle Mode In this mode the decoder is waiting for the RUN command. This mode should be used to initialise the configuration register of the device. The DAC connected to STA003T can be initialised during this mode (set MUTE to 1). PLAY X MUTE 0 Clock State Not Running PCM Output 0 X 1 Running 0 8/32 Init Mode "PLAY" and "MUTE" changes are ignored in this mode. The internal state of the decoder will be updated only when the decoder changes from the state "init" to the state "decode". The "init" phase ends when the first decoded samples are at the output stage of the device. Decode Mode This mode is completely described by the following table: PLAY MUTE 0 0 1 0 1 0 1 1 PCM Decoding Output Not Running 0 No Running 0 No Running Decoded Yes Samples Running 0 Yes Clock State STA003T 3 - I2C BUS SPECIFICATION The STA003T supports the I2C protocol. This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the others as the slave. The master always starts the transfer and provides the serial clock for synchronisation. The STA003T is always a slave device in all its communications. 3. 1 - COMMUNICATION PROTOCOL 3.1.0 - Data transition or change Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high are used to identify START or STOP condition. 3.1.1 - Start condition START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer. 3.1.2 - Stop condition STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communications between STA003T and the bus master. 3.1.3 - Acknowledge bit An acknowledge bit is used to indicate a successful data transfer. The bus transmitter, either master or slave, releases the SDA bus after sending 8 bit of data. During the 9th clock pulse the receiver pulls the SDA bus low to acknowledge the receipt of 8 bits of data. 3.1.4 - Data input During the data input the STA003T samples the SDA signal on the rising edge of the clock SCL. For correct device operation the SDA signal has to be stable during the rising edge of the clock and the data can change only when the SCL line is low. 3.2 - DEVICE ADDRESSING To start communication between the master and the STA003T, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8 bits (MSB first) corresponding to the device select address and read or write mode. The 7 most significant bits are the device address identifier, corresponding to the I2C bus definition. For the STA003T these are fixed as 1000011. The 8th bit (LSB) is the read or write operation RW, this bit is set to 1 in read mode and 0 for write mode. After a START condition the STA003T identifies on the bus the device address and, if a match is found, it acknowledges the identification on SDA bus during the 9th bit time. The following byte after the device identification byte is the internal space address. 3.3 - WRITE OPERATION (see fig. 9) Following a START condition the master sends a device select code with the RW bit set to 0. The STA003T acknowledges this and waits for the byte of internal address. After receiving the internal bytes address the STA003T again responds with an acknowledge. 3.3.1 - Byte write In the byte write mode the master sends one data byte, this is acknowledged by STA003T. The master then terminates the transfer by generating a STOP condition. 3.3.2 - Multibyte write The multibyte write mode can start from any internal address. The transfer is terminated by the master generating a STOP condition. Figure 9. Write Mode Sequence ACK DEV-ADDR BYTE WRITE START ACK SUB-ADDR RW STOP ACK DEV-ADDR MULTIBYTE WRITE START ACK DATA IN ACK SUB-ADDR RW ACK ACK DATA IN DATA IN D98AU825B STOP 9/32 STA003T Figure 10. Read Mode Sequence ACK CURRENT ADDRESS READ DEV-ADDR NO ACK DATA RW START STOP ACK ACK RANDOM ADDRESS READ DEV-ADDR SUB-ADDR RW START START RW= ACK HIGH SEQUENTIAL CURRENT READ DEV-ADDR ACK STOP RW ACK DATA NO ACK DATA DEV-ADDR ACK NO ACK DATA DATA STOP START ACK SEQUENTIAL RANDOM READ DEV-ADDR ACK START RW 3.4 - READ OPERATION (see Fig. 10) 3.4.1 - Current byte address read The STA003T has an internal byte address counter. Each time a byte is written or read, this counter is incremented. For the current byte address read mode, following a START condition the master sends the device address with the RW bit set to 1. The STA003T acknowledges this and outputs the byte addressed by the internal byte address counter. The master does not acknowledge the received byte, but terminates the transfer with a STOP condition. 3.4.2 - Sequential address read This mode can be initiated with either a current address read or a random address read. However in this case the master does acknowledge the data byte output and the STA003T continues to output the next byte in sequence. To terminate the streams of bytes the master ACK ACK DATA DEV-ADDR SUB-ADDR RW START ACK DATA NO ACK DATA D98AU826A STOP does not acknowledge the last received byte, but terminates the transfer with a STOP condition. The output data stream is from consecutive byte addresses, with the internal byte address counter automatically incremented after one byte output. 4 - I2C REGISTERS The following table gives a description of the MPEG Source Decoder (STA003T) register list. The first column (HEX_COD) is the hexadecimal code for the sub-address. The second column (DEC_COD) is the decimal code. The third column (DESCRIPTION) is the description of the information contained in the register. The fourth column (RESET) inidicate the reset value if any. When no reset value is specifyed, the default is "undefined". The fifth column (R/W) is the flag to distinguish register "read only" and "read and write", and the useful size of the register itself. Each register is 8 bit wide. The master shall operate reading or writing on 8 bits only. I2C REGISTERS HEX_COD 0x00 0x01 0x05 0x06 0x07 0x0B 0x0C 0x0D 0x0F 10/32 DEC_COD 0 1 5 6 7 11 12 13 15 DESCRIPTION RESET R/W R (8) 0xAC 0x21 0x0C 0x00 R (8) R/W (8) R/W (8) R/W (8) 0x04 0x00 R/W (8) R (8) VERSION IDENT PLLCTL [7:0] PLLCTL_M PLLCTL_N reserved reserved SCLK_POL ERROR_CODE STA003T I2C REGISTERS (continued) HEX_COD 0x10 0x13 DEC_COD 16 19 DESCRIPTION SOFT_RESET PLAY RESET 0x00 0x01 R/W W (8) R/W(8) 0x14 20 MUTE 0x00 R/W(8) 0x16 22 CMD_INTERRUPT 0x00 R/W(8) 0x18 0x40 24 64 reserved SYNCSTATUS 0x00 R (8) 0x41 65 ANCCOUNT_L 0x00 R (8) 0x42 0x43 66 67 ANCCOUNT_H HEAD_H[23:16] 0x00 0x00 R (8) R(8) 0x44 68 HEAD_M[15:8] 0x00 R(8) 0x45 69 HEAD_L[7:0] 0x00 R(8) 0x46 0x47 0x48 70 71 72 DLA DLB DRA 0x00 0xFF 0x00 R/W (8) R/W (8) R/W (8) 0x49 0x54 0x55 73 84 85 DRB PCMDIVIDER PCMCONF 0xFF 0x01 0x21 R/W (8) R/W (8) R/W (8) 0x56 86 PCMCROSS 0x00 R/W (8) 0x59 0x5A 89 90 ANC_DATA_1 [7:0] ANC_DATA_2 [15:8] 0x00 0x00 R (8) R (8) 0x5B 91 ANC_DATA_3 [23:16] 0x00 R (8) 0x5C 0x5D 0x61 92 93 97 ANC_DATA_4 [31:24] ANC_DATA_5 [39:32] MFSDF (X) 0x00 0x00 0x0F R (8) R (8) R/W (8) 0x63 99 DAC_CLK_MODE 0x00 R/W (8) 0x64 0x65 100 101 PLLFRAC_L PLLFRAC_H 0xC8 0x59 R/W (8) R/W (8) 0x67 0x68 0x69 0x6A 0x71 0x72 103 104 105 106 113 114 FRAME_CNT_L FRAME_CNT_M FRAME_CNT_H AVERAGE_BITRATE SOFTVERSION RUN 0x00 0x00 0x00 0x00 0x00 R (8) R (8) R (8) R (8) R (8) R/W (8) 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 119 120 121 122 123 124 125 TREBLE_FREQUENCY_LOW TREBLE_FREQUENCY_HIGH BASS_FREQUENCY_LOW BASS_FREQUENCY_HIGH TREBLE_ENHANCE BASS_ENHANCE TONE_ATTEN 0x00 0x00 0x00 0x00 0x00 0x00 0x00 R/W (8) R/W (8) R/W (8) R/W (8) R/W (8) R/W (8) R/W (8) Note: 1) The HEX_COD is the hexadecimal adress that the microcontroller has to generate to access the information. 2) RESERVED: register used for production test only, or for future use. 11/32 STA003T 4.1 - STA003T REGISTERS DESCRIPTION The STA003T device includes 128 I2C registers. In this document, only the user-oriented registers are described. The undocumented registers are reserved. These registers must never be accessed (in Read or in Write mode). The ReadOnly registers must never be written. The following table describes the meaning of the abbreviations used in the I2C registers description: Symbol Comment NA Not Applicable UND NC Undefined No Charge RO Read Only WO Write Only R/W R/WS Read and Write Read, Write in specific mode VERSION Address: 0x00 Type: RO MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 V8 V7 V6 V5 V4 V3 V2 V1 The VERSION register is read-only and it is used to identify the IC on the application board. IDENT Address: 0x01 Type: RO Software Reset: 0xAC Hardware Reset: 0xAC MSB b7 1 LSB b6 0 b5 1 b4 0 b3 1 b2 1 b1 0 b0 0 IDENT is a read-only register and is used to identify the IC on an application board. IDENT always has the value "0xAC" PLLCTL Address: 0x05 Type: R/W 12/32 Software Reset: 0x21 Hardware Reset: 0x21 MSB b7 LSB b6 b5 b4 b3 b2 b1 b0 XTO_ XTOD OCLK SYS2O PPLD XTI2DS XTI2O UPD_F BUF IS EN CLK IS PCLK CLK RAC UPD_FRAC: when is set to 1, updates FRAC in the switching circuit. It is set to 1 after autoboot. XTI2OCLK: when is set to 1, uses the XTI as input of the divider X instead of VCO output. It is set to 0 on HW reset. XTI2DSPCLK: when is set to 1, uses the XTI as input of the divider S instead of VCO output. It is set to 0 on HW reset. PLLDIS: when set to 1, the VCO output is disabled. It is set to 0 on HW reset. SYS2OCLK: when is set to 1, the OCLK frequency is equal to the system frequency. It is useful for testing. It is set to 0 on HW reset. OCLKEN: when is set to 1, the OCLK pad is enable as output pad. It is set to 1 on HW reset. XTODIS: when is set to 1, the XTO pad is disabled. It is set to 0 on HW reset. XTO_BUF: when this bit is set, the pin nr. 28 (VDD_5/CLK_OUT) is enabled as buffered (4mA) master clock output (CLK_OUT). It is set to 0 after autoboot. PLLCTL_M Address: 0x06 Type: R/W Software Reset: 0x0C Hardware Reset: 0x0C PLLCTL_N Address: 0x07 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 The M and N registers are used to configure the STA003T PLL by DSP embedded software. M and N registers are R/W type but they are completely controlled, on STA003T, by DSP software. STA003T SCKL_POL Address: 0x0D Type: R/W Software Reset: 0x04 Hardware Reset: 0x04 SOFT_RESET Address: 0x10 Type: WO Software Reset: 0x00 Hardware Reset: 0x00 MSB b7 X LSB b6 X b5 X b4 X b3 X MSB b2 0 b1 0 b0 0 (1) 1 0 0 (2) b7 X LSB b6 X b5 X b4 X b3 X b2 X b1 X b0 0 1 X = don’t care X = don’t care; 0 = normal operation; 1 = reset SCKL_POL is used to select the working polarity of the Input Serial Clock (SCKR). (1) If SCKL_POL is set to 0x00, the data (SDI) are sent with the falling edge of SCKR and sampled on the rising edge. (2) If SCKL_POL is set to 0x04, the data (SDI) are sent with the rising edge of SCKR and sampled on the falling edge. ERROR_CODE Address: 0x0F Type: RO Software Reset: 0x00 Hardware Reset: 0x00 MSB LSB When this register is written, a soft reset occours. The STA003T core command register and the interrupt register are cleared. The decoder goes in to idle mode. PLAY Address: 0x13 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB b7 b6 b5 b4 b3 b2 b1 X X X X X X X LSB b0 0 1 b7 b6 b5 b4 b3 b2 b1 b0 X X X X 0 0 0 0 0 0 0 1 (1) (2) X = don’t care; 0 = normal operation; 1 = play 0 0 1 0 (3) The PLAY command is handled according to the state of the decoder, as described in section 2.5. PLAY only becomes active when the decoder is in DECODE mode. X = don’t care ERROR_CODE register contains the last error occourred if any. The codes can be as follows: Code Description (1) 0x00 No error since the last SW or HW Reset (2) 0x01 CRC Failure (3) 0x02 DATA not available 13/32 STA003T MUTE Address: 0x14 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 CMD_INTERRUPT Address: 0x16 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB b7 b6 b5 b4 b3 b2 b1 X X X X X X X LSB MSB b0 b7 b6 b5 b4 b3 b2 b1 LSB 0 X X X X X X X 1 0 1 X = don’t care; 0 = normal operation; 1 = mute The MUTE command is handled according to the state of the decoder, as described in section 2.5. MUTE sets the clock running. X = don’t care; 0 = normal operation; 1 = write into I2C/Ancillary Data The INTERRUPT is used to give STA003T the command to write into the I2C/Ancillary Data Buffer (Registers: 0x59 ... 0x5D). Every time the Master has to extract the new buffer content (5 bytes) it writes into this register, setting it to a non-zero value. SYNCSTATUS Address: 0x40 Type: RO Software Reset: 0x00 Hardware Reset: 0x00 MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 Description X X X X X X SS1 0 0 SS0 0 1 Research of sync word Wait for Confirmation 1 0 Synchronised 1 1 not used 14/32 b0 STA003T HEAD_M[15:8] ANCCOUNT_L Address: 0x41 Type: RO Software Reset: 0x00 Hardware Reset: 0x00 MSB b7 H15 MSB b7 AC7 LSB b6 AC6 b5 AC5 b4 AC4 b3 AC3 b2 AC2 b1 AC1 b0 AC0 ANCCOUNT_H Address: 0x42 Type: RO Software Reset: 0x00 Hardware Reset: 0x00 ANCCOUNT_H MSB b7 b6 b5 b4 b3 b2 b1 AC15 AC14 AC13 AC12 AC11 AC10 AC9 LSB b0 AC8 ANCCOUNT registers are logically concatenated and indicate the number of Ancillary Data bits available at every correctly decoded MPEG frame. HEAD_H[23:16] MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 X X X H20 H19 H18 H17 H16 x = don’t care LSB b6 H14 b5 H13 b4 H12 b3 H1‘1 b2 H10 b1 H9 b0 H8 HEAD_L[7:0] MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 H7 H6 H5 H4 H3 H2 H1 H0 Address: 0x43, 0x44, 0x45 Type: RO Software Reset: 0x00 Hardware Reset: 0x00 Head[1:0] emphasis Head[2] original/copy Head[3] copyrightHead [5:4] mode extension Head[7:6] mode Head[8] private bit Head[9] padding bit Head[11:10] sampling frequency index Head[15:12] bitrate index Head[16] protection bit Head[18:17] layer Head[19] ID Head[20] ID_ex The HEAD registers can be viewed as logically concatenated to store the MPEG Layer III Header content. The set of three registers is updated every time the synchronisation to the new MPEG frame is achieved . 15/32 STA003T The meaning of the flags are shown in the following tables: MPEG IDs IDex 0 0 ID 0 1 MPEG 2.5 reserved 1 0 MPEG 2 1 1 MPEG 1 Layer in Layer III these two flags must be set always to "01". Protection_bit It equals "1" if no redundancy has been added and "0" if redundancy has been added. Bitrate_index indicates the bitrate (Kbit/sec) depending on the MPEG ID. bitrate index ’0000’ ’0001’ ’0010’ ’0011’ ’0100’ ’0101’ ’0110’ ’0111’ ’1000’ ’1001’ ’1010’ ’1011’ ’1100’ ’1101’ ’1110’ ’1111’ ID = 1 free 32 40 48 56 64 80 96 112 128 not supported not supported not supported not supported not supported forbidden ID = 0 free 8 16 24 32 40 48 56 64 80 96 112 128 not supported not supported forbidden Sampling Frequency indicates the sampling frequency of the encoded audio signal (KHz) depending on the MPEG ID Sampling MPEG1 MPEG2 MPEG2.5 Frequency ’00’ not supported not supported not supported ’01’ 48 24 12 ’10’ 32 16 8 ’11’ reserved reserved reserved 16/32 Padding bit if this bit equals ’1’, the frame contains an additional slot to adjust the mean bitrate to the sampling frequency, otherwise this bit is set to ’0’. Private bit Bit for private use. This bit will not be used in the future by ISO/IEC. Mode Indicates the mode according to the following table. The joint stereo mode is intensity_stereo and/or ms_stereo. mode mode specified ’00’ stereo ’01’ joint stereo (intensity_stereo and/or ms_stereo) ’10’ dual_channel ’11’ single_channel (mono) Mode extension These bits are used in joint stereo mode. They indicates which type of joint stereo coding method is applied. The frequency ranges, over which the intensity_stereo and ms_stereo modes are applied, are implicit in the algorithm. Copyright If this bit is equal to ’0’, there is no copyright on the bitstream, ’1’ means copyright protected. Original/Copy This bit equals ’0’ if the bitstream is a copy, ’1’ if it is original. Emphasis Indicates the type of de-emphasis that shall be used. emphasis ’00’ ’01’ ’10’ ’11’ emphasis specified none 50/15 microseconds reserved CCITT J,17 STA003T DLA Address: 0x46 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 Description DLA7 DLA6 DLA5 DLA4 DLA3 DLA2 DLA1 DLA0 OUTPUT ATTENUATION 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 NO ATTENUATION -1dB 0 : 0 : 0 : 0 : 0 : 0 : 1 : 0 : -2dB : 0 1 1 0 0 0 0 0 -96dB DLA register is used to attenuate the level of audio output at the Left Channel using the butterfly shown in Fig. 11. When the register is set to 255 (0xFF), the maximum attenuation is achieved. A decimal unit correspond to an attenuation step of 1 dB. Figure 11. Volume Control and Output Setup DSP Left Channel DLA X Output Left Channel + DLB X DRB X DRA DSP Right Channel X Output Right Channel + D97AU667 DLB Address: 0x47 Type: R/W Software Reset: 0xFF Hardware Reset: 0xFF MSB b7 DLB7 0 b1 DLB1 0 LSB b0 DLB0 0 b6 DLB6 0 b5 DLB5 0 b4 DLB4 0 b3 DLB3 0 b2 DLB2 0 Description OUTPUT ATTENUATION NO ATTENUATION 0 0 : 0 0 : 0 0 : 0 0 : 0 0 : 0 0 : 0 1 : 1 0 : -1dB -2dB : 0 1 1 0 0 0 0 0 -96dB DLB register is used to re-direct the Left Channel on the Right, or to mix both the Channels. Default value is 0x00, corresponding at the maximum attenuation in the re-direction channel. 17/32 STA003T DRA Address: 0x48 Type: R/W Software Reset: 0X00 Hardware Reset: 0X00 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 Description DRA7 DRA6 DRA5 DRA4 DRA3 DRA2 DRA1 DRA0 OUTPUT ATTENUATION 0 0 0 0 0 0 0 0 NO ATTENUATION 0 0 0 0 0 0 0 1 -1dB 0 : 0 : 0 : 0 : 0 : 0 : 1 : 0 : -2dB : 0 1 1 0 0 0 0 0 -96dB DRA register is used to attenuate the level of audio output at the Right Channel using the butterfly shown in Fig. 11. When the register is set to 255 (0xFF), the maximum attenuation is achieved. A decimal unit correspond to an attenuation step of 1 dB. DRB Address: 0x49 Type: R/W Software Reset: 0xFF Hardware Reset: 0xFF MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 Description DRB7 0 0 DRB6 0 0 DRB5 0 0 DRB4 0 0 DRB3 0 0 DRB2 0 0 DRB1 0 0 DRB0 0 1 OUTPUT ATTENUATION NO ATTENUATION -1dB 0 0 0 0 0 0 1 0 -2dB : : : : : : : : : 0 1 1 0 0 0 0 0 -96dB DRB register is used to re-direct the Right Channel on the Left, or to mix both the Channels. Default value is 0x00, corresponding at the maximum attenuation in the re-direction channel. PCMDIVIDER Address: 0x54 Type: RW Software Reset: 0x01 Hardware Reset: 0x01 DACs), and the SCKT (Serial Audio Transmitter Clock). The relation is the following: 7 PD7 6 PD6 5 PD5 4 PD4 3 PD3 2 PD2 1 PD1 0 PD0 PCMDIVIDER is used to set the frequency ratio between the OCLK (Oversampling Clock for 18/32 SCKT_freq = OCLK_freq 2 (1 + PCMDIVIDER) STA003T The Oversampling Factor (O_FAC) is related to OCLK and SCKT by the following expression: 1) OCLK_freq = O_FAC * LRCKT_ Freq (DAC relation) 2) OCLK_ Freq = 2 * (1+PCMDIVIDER) * 32* LRCKT_Freq (when 16 bit PCM mode is used) 3) OCLK_ Freq = 2 * (1+PCMDIVIDER) * 64* LRCKT_Freq (when 32 bit PCM mode is used) 4) PCMDIVIDER = (O_FAC/64) - 1 in 16 bit mode 5) PCMDIVIDER = (O_FAC/128) - 1 in 32 bit mode Example for setting: MSB b7 PD7 0 0 0 0 0 0 LSB b6 PD6 0 0 0 0 0 0 b5 PD5 0 0 0 0 0 0 b4 PD4 0 0 0 0 0 0 for 16 bit PCM Mode O_FAC = 512 ; PCMDIVIDER = 7 O_FAC = 256 ; PCMDIVIDER = 3 O_FAC = 384 ; PCMDIVIDER = 5 b3 PD3 0 0 0 0 0 0 b2 PD2 1 1 0 0 0 0 b1 PD1 1 0 1 1 1 0 b0 PD0 1 1 1 1 0 1 Description 16 bit mode 16 bit mode 16 bit mode 32 bit mode 32 bit mode 32 bit mode 512 x Fs 384 x Fs 256 x Fs 512 x Fs 384 x Fs 256 x Fs for 32 bit PCM Mode O_FAC = 512 ; PCMDIVIDER = 3 O_FAC = 256 ; PCMDIVIDER = 1 O_FAC = 384 ; PCMDIVIDER = 2 19/32 STA003T PCMCONF Address: 0x55 Type: R/W Software Reset: 0x21 Hardware Reset: 0x21 MSB b7 X X X X X X X X X X X X X X X b6 ORD 1 0 b5 DIF b4 INV b3 FOR b2 SCL LSB b1 b0 PREC [1] PREC ([0] 0 1 1 0 0 1 1 0 0 0 1 1 PCMCONF is used to set the PCM Output Interface configuration: ORD: PCM order. If this bit is set to’1’, the LS Bit is transmitted first, otherwise MS Bit is transmiited first. DIF: PCM_DIFF. It is used to select the position of the valid data into the transmitted word. This setting is significant only in 18/20/24 bit/word mode.If it is set to ’0’ the word is right-padded, otherwise it is left-padded. INV (fig.12): It is used to select the LRCKT clock polarity. If it is set to ’1’ the polarity is compliant to I2S format (low -> left , high -> right), otherwise the LRCKT is inverted. The default value is ’0’. (if I2S have to be selected, must be set to ’1’ in the STA003T configuration phase). Figure 12. LRCKT Polarity Selection left LRCKT left INV_LRCLK=0 right right LRCKT left left INV_LRCLK=1 FOR: FORMAT is used to select the PCM Output Interface format. After hw and sw reset the value is set to 0 corresponding to I2S format. SCL (fig.13): used to select the Transmitter Serial Clock polarity. If set to ’1’ the data are sent on the 20/32 0 1 0 1 Description PCM order the LS bit is transmitted First PCM order the MS bit is transmitted First The word is right padded The word is left padded LRCKT Polarity compliant to I2S format LRCKT Polarity inverted I2S format Different formats Data are sent on the rising edge of SCKT Data are sent on the falling edge of SCKT 16 bit mode (32 slots transmitted per LRCKT period) 18 bit mode (64 slots transmitted per LRCKT period) 20 bit mode (64 slots transmitted per LRCKT period) 24 bit mode (64 slots transmitted per LRCKT period) rising edge of SCKT and sampled on the falling. If set to ’0’ , the data are sent on the falling edge and sampled on the rising. This last option is the most commonly used by the commercial DACs. The default configuration for this flag is ’0’. Figure 13. SCKT Polarity Selection SCKT SDO INV_SCLK=0 SCKT SDO INV_SCLK=1 PREC [1:0]: PCM PRECISION It is used to select the PCM samples precision, as follows: ’00’: 16 bit (16 slots transmitted per LCKT period) ’01’: 18 bit (32 slots transmitted per LCKT period) ’10’: 20 bit (32 slots transmitted per LCKT period) ’11’: 24 bit (32 slots transmitted per LCKT period) The PCM samples precision in STA003T can be 16 or 18-20-24 bits. When STA003T operates with a 16 (18-20-24) bits precision, the number of bits transmitted during a LRCKT period is 32 (64). STA003T PCMCROSS Address: 0x56 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB LSB b7 X b6 X b5 X b4 X b3 X b2 X b1 0 b0 0 X X X X X X 0 1 Description Left channel is mapped on the left output. Right channel is mapped on the Right output Left channel is duplicated on both Output channels. X X X X X X X X X X X X 1 1 0 1 Right channel is duplicated on both Output channels Right and Left channels are toggled The default configuration for this register is ’0x00’. The value is changed by the internal STA003T Core, to set the clock frequencies, according to the incoming bitstream. This value can be even set by the user to select the PCM interface configuration. The VCO output frequency is divided by (X+1). ANCILLARY DATA BUFFER Address: 0x59 - 0x5D Type: RO Software Reset: 0x00 Hardware Reset: 0x00 STA003T can extract max 56 bytes/MPEG frame. To know the number of A.D. bits available every MPEG frame, the ANCCOUNT_L and ANCCOUNT_H registers (0x41 and 0x42) have to be read. The buffer dimension is 5 bytes, written by STA003T core in sequential order. The timing information to read the buffer can be obtained by reading the FRAME_CNT registers (0x67 - 0x69). To fill up the buffer with a new 5-bytes slot, the STA003T waits until a CMD_INTERRUPT register is written by the master. MFSDF (X) Address: 0x61 Type: R/W Software Reset: 0x0F Hardware Reset: 0x0F MSB b7 X b6 X b5 X b4 M4 b3 M3 b2 M2 b1 M1 LSB b0 M0 DAC_CLK_MODE Address: 0x63 Type: RW Software Reset: 0x00 Hardware Reset: 0x00 MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 X X X X X X X MODE This register is used to select the operating mode for OCLK clock signal. If it is set to ’1’, the OCLK frequency is fixed, and it is mantained to the value fixed by the user even if the sampling frequency of the incoming bitstream changes. If the MODE flag is set to ’0’, the OCLK frequency changes, and can be set to (512, 384, 256) * Fs. The default configuration for this mode is 256 * Fs. When this mode is selected, the default OCLK frequency is 12.288 MHz. The register contains the values for PLL X divider (see Fig. 6). 21/32 STA003T PLLFRAC_L ([7:0]) MSB b7 PF7 LSB b6 PF6 b5 PF5 b4 PF4 b3 PF3 b2 PF2 b1 PF1 b0 PF0 FRAME_CNT_H MSB b7 LSB b6 b5 b4 b3 b2 b1 b0 FC23 FC22 FC21 FC20 FC19 FC18 FC17 FC016 PLLFRAC_H ([15:8]) MSB LSB b7 b6 b5 b4 b3 b2 PF15 PF14 PF13 PF12 PF11 PF10 b1 PF9 b0 PF8 Address: 0x64 - 0x65 Type: R/W Software Reset: 0xC8-0x59 Hardware Reset: 0xC8-0x59 The registers are considered logically concatenated and contain the fractional values for the PLL, used to select the internal configuration. After Reset, the values are NA, and the operational setting are done when the MPEG synchronisation is achieved. The following formula describes the relationships among all the STA003T fractional PLL parameters: 1 MCLK_freq OCLK_Freq = ⋅ PLLTL_N + 1 ⋅ MFSDF(X) 1 + PLLFRAC ⋅ PLLCTL_M + 1 + 65536 where: PLLFRAC=256 x FRAC_H + PLLFRAC_L (decimal) Address: 0x67, 0x68, 0x69 Type: RO Software Reset: 0x00 Hardware Reset: 0x00 The three registers are considered logically concatenated and compose the Global Frame Counter. They are updated at every decoded MPEG Frame. The registers are reset on both hardware and software reset. AVERAGE_BITRATE Address: 0x6A Type: RO Software Reset: 0x00 Hardware Reset: 0x00 MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0 AVERAGE_BITRATE is a read-only register and it contains the average bitrate of the incoming bitstream. The value is rounded with an accuracy of 1 Kbit/sec. SOFTVERSION FRAME_CNT_L MSB b7 FC7 b6 FC6 b5 FC5 b4 FC4 b3 FC3 b2 FC2 b1 FC1 LSB b0 FC0 FRAME_CNT_M MSB b7 b6 b5 b4 b3 b2 FC15 FC14 FC13 FC12 FC11 FC10 22/32 LSB b1 FC9 b0 FC8 Address: 0x71 Type: RO MSB b7 SV7 b6 SV6 b5 SV5 b4 SV4 b3 SV3 b2 SV2 b1 SV1 LSB b0 SV0 After the STA003T boot, this register contains the version code of the embedded software. STA003T RUN BASS_FREQUENCY_LOW Address: 0x72 Type: RW Software Reset: 0x00 Hardware Reset: 0x00 Address: 0x79 Software Reset: 0x00 Hardware Reset: 0x00 MSB MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 X X X X X X X RUN b7 BF7 LSB b6 BF6 b5 BF5 b4 BF4 b3 BF3 b2 BF2 b1 BF1 b0 BF0 b2 b1 LSB b0 BF9 BF8 BASS_FREQUENCY_HIGH Setting this register to 1, STA003T leaves the idle state, starting the decoding process. The Microcontroller is allowed to set the RUN flag, once all the control registers have been initialized. Address: 0x7A Software Reset: 0x00 Hardware Reset: 0x00 MSB b7 TREBLE_FREQUENCY_LOW b6 b5 b4 b3 BF15 BF14 BF13 BF12 BF11 BF10 Address: 0x77 Type: RW Software Reset: 0x00 Hardware Reset: 0x00 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 TF7 TF6 TF5 TF4 TF3 TF2 TF1 TF0 The registers BASS_FREQUENCY_HIGH and BASS_FREQUENCY_LOW, logically concatenated as a 16 bit wide register, are used to select the frequency, in Hz, where the selected frequency is -12dB respect to the pass-band. By setting the BASS_FREQUENCY registers, the following rules must be kept: Bass_Freq <= Treble_Freq TREBLE_FREQUENCY_HIGH Bass_Freq > 0 (suggested range: 20 Hz < Bass_Freq < 750 Hz) Example: Bass = 200Hz Treble = 3kHz Address: 0x78 Type: RW Software Reset: 0x00 Hardware Reset: 0x00 MSB b7 b6 b5 b4 b3 b2 TF15 TF14 TF13 TF12 TF11 TF10 b1 LSB b0 TF9 TF8 The registers TREBLE_FREQUENCY_HIGH and TREBLE_FREQUENCY_LOW, logically concatenated as a 16 bit wide register, are used to select the frequency, in Hz, where the selected frequency is +12dB respect to the stop band. By setting these registers, the following rule must be kept: Treble_Freq < Fs/2 TFS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 1 0 1 1 1 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 0 1 0 0 0 0 0 0 1 0 BFS 0 0 0 0 0 0 23/32 STA003T Signed number (2 complement) This register is used to select the enhancement or attenuation STA003T has to perform on Treble Frequency range at the digital signal. A decrement (increment) of a decimal unit corresponds to a step of attenuation (enhancement) of 1.5dB. The allowed Attenuation/Enhancement range is [-18dB, +18dB]. TREBLE_ENHANCE Address: 0x7B Software Reset: 0x00 Hardware Reset: 0x00 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 TE7 TE6 TE5 TE4 TE3 TE2 TE1 TE0 MSB LSB ENHANCE/ATTENUATION b7 b6 b5 b4 b3 b2 b1 b0 1.5dB step 0 0 0 0 1 1 0 0 +18 0 0 0 0 1 0 1 1 +16.5 0 0 0 0 1 0 1 0 +15 0 0 0 0 1 0 0 1 +13.5 . . . 0 0 0 0 0 0 0 1 +1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 -1 . . . 1 1 1 1 0 1 1 1 -13.5 1 1 1 1 0 1 1 0 -15 1 1 1 1 0 1 0 0 -16.5 1 1 1 1 0 1 0 0 -18 24/32 STA003T Signed number (2 complement) This register is used to select the enhancement or attenuation STA003T has to perform on Bass Frequency range at the digital signal. A decrement (increment) of a decimal unit corresponds to a step of attenuation (enhancement) of 1.5dB. The allowed Attenuation/Enhancement range is [-18dB, +18dB]. BASS_ENHANCE Address: 0x7C Software Reset: 0x00 Hardware Reset: 0x00 MSB b7 BE7 LSB b6 BE6 b5 BE5 b4 BE4 b3 BE3 b2 BE2 b1 BE1 b0 BE0 MSB LSB ENHANCE/ATTENUATION b7 b6 b5 b4 b3 b2 b1 b0 1.5dB step 0 0 0 0 1 1 0 0 +18 0 0 0 0 1 0 1 1 +16.5 0 0 0 0 1 0 1 0 +15 0 0 0 0 1 0 0 1 +13.5 . . . 0 0 0 0 0 0 0 1 +1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 -1 . . . 1 1 1 1 0 1 1 1 -13.5 1 1 1 1 0 1 1 0 -15 1 1 1 1 0 1 0 0 -16.5 1 1 1 1 0 1 0 0 -18 25/32 STA003T In the digital output audio, the full signal is achieved with 0 dB of attenuation. For this reason, before applying Bass & Treble Control, the user has to set the TONE_ATTEN register to the maximum value of enhancement is going to perform. For example, in case of a 0 dB signal (max. level) only attenuation would be possible. If enhancement is desired, the signal has to be attenuated accordingly before in order to reserve a margin in dB. An increment of a decimal unit corresponds to a Tone Attenuation step of 1.5dB. TONE_ATTEN Address: 0x7D Type: RW Software Reset: 0x00 Hardware Reset: 0x00 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0 MSB b7 0 0 0 0 b6 0 0 0 0 b5 0 0 0 0 b4 0 0 0 0 b3 0 0 1 0 b2 0 0 0 0 b1 0 0 1 1 LSB b0 0 1 0 1 ATTENUATION -1.5dB step 0dB -1.5dB -3dB -4.5dB . . . 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0 0 1 0 -15dB -16.5dB -18dB 5. GENERAL INFORMATION 5.1. MPEG 2.5 Layer III Algorithm. DEMULTIPLEXING & ERROR CHECK INVERSE QUANTISATION & DESCALING HUFFMAN DECODING INVERSE FILTERBANK IMDCT STEREOPHONIC AUDIO SIGNAL (2*768Kbit/s) SIDE INFORMATION DECODING ANCILLARY DATA D98AU903 ENCODED AUDIO BITSTREAM (8Kbit/s ... 128Kbit/s) 5.2 - MPEG Ancillary Data Description: As specifyed in the ISO standard, the MPEG Layer III frames have a variable bit lenght, and are constant in time depending on the audio sam- pling frequencies. The time duration of the Layer III frames is shown in Tab 2. Table2: MPEG Layer III Frames Time Duration Sampling Frequency (KHz) MPEG Frame Lenght (ms) 26/32 48 24 32 36 24 24 16 36 12 48 8 72 STA003T The Ancillary Data extraction on STA003T can be described as follow: STA003T has a specific 5 bytes Ancillary Data buffer, mapped into the I2C registers: 0x59 0x5A 0x5B 0x5C 0x5D ANC_DATA_1 ANC_DATA_2 ANC_DATA_3 ANC_DATA_4 ANC_DATA_5 Frame is max. 56 bytes, a specific register, to require new 5 bytes, is needed. This register is: 0x16 CMD_INTERRUPT The interrupt register, is sensitive to any non-zero value written by the Microcontroller. When this register is updated the Ancillary Data buffer is filled up with new values and the registers 0x41 0x42 Since the content of Ancillary Data into an MPEG ANCCOUNT_L ANCCOUNT_H are updated (decremented) accordingly. 5.3. I/O CELL DESCRIPTION 1) CMOS Tristate Output Pad Buffer, 4mA, with Slew Rate Control / Pin numbers 9, 10, 11, 20, 28 EN OUTPUT PIN Z Z A MAX LOAD 100pF D98AU904 2) CMOS Bidir Pad Buffer, 4mA, with Slew Rate Control / Pin numbers 3, 12 EN OUTPUT PIN IO IO A ZI CAPACITANCE 5pF OUTPUT PIN IO MAX LOAD 100pF D98AU905 3) CMOS Inpud Pad Buffer / Pin numbers 4, 5, 6, 8, 21, 25 A Z INPUT PIN A CAPACITANCE 3.5pF D98AU906 4) CMOS Inpud Pad Buffer with Active Pull-Up / Pin numbers 7, 24, 26 A Z INPUT PIN A CAPACITANCE 3.5pF D98AU907 27/32 STA003T 5.4. TIMING DIAGRAMS 5.4.1. Audio DAC Interface a) OCLK in output. The audio PLL is used to clock the DAC OCLK (OUTPUT) SDO tsdo SCKT tsckt LRCLK tlrclk D98AU969 tsdo = 3.5 + pad_timing (Cload_SDO) - pad_timing (Cload_ OCLK) tsckt = 4 + pad_timing (Cload_SCKT) - pad_timing (Cload_ OCLK) tlrckt = 3.5 + pad_timing (Cload_LRCCKT) pad_timing (Cload_ OCLK) Pad-timing versus load Load (pF) 25 Pad_timing 2.90ns 50 3.82ns 75 100 4.68ns 5.52ns Cload_XXX is the load in pF on the XXX output. pad_timing (Cload_XXX) is the propagation delay added to the XXX pad due to the load. b) OCLK in input. OCLK (INPUT) thi tlo SDO tsdo SCKT tsckt LRCLK tlrclk toclk Thi min = 3ns Tlo min = 3ns Toclk min = 25ns tsdo = 5.5 + pad_timing (Cload_SDO) ns tsckt = 6 + pad_timing (Cload_SCKT) ns tlrckt = 5.5 + pad_timing (Cload_LRCKT) ns 28/32 D98AU970 STA003T 5.4.2. Bitstream input interface (SDI, SCKR, BIT_EN) BIT_EN t_biten t_biten SCKR(SCLK_POL=2) tsckr_min_hi tsckr_min_hi tlo tsckr_min_period SCKR(SCLK_POL=0) SDI tsdi_setup D98AU971 tsdi_hold tsdi_setup_min = 2ns tsdi_hold_min = 3ns tsckr_min_hi = 10ns tsckr_min_low = 10ns tsckr_min_lperiod = 50ns t_biten (min) = 2ns 5.4.3. SRC_INT This is an asynchronous input used in "broadcast’ mode. SRC_INT is active low t_src_hi SRC_INT t_src_low D98AU972 t_src_low min duration is 50ns (1DSP clock period) t_src_high min duration is 50ns (1DSP clock period) 5.4.4. XTI,XTO and CLK_OUT timings thi XTI (INPUT) tlo XTO txto CLK_OUT tclk_out D98AU973 txto = 1.40 + pad_timing (Cload_XTO) ns 5.4.5. RESET The Reset min duration (t_reset_low_min) is 100ns RESET treset_low_min D98AU974 29/32 STA003T 5.5 DAC RELATED REGISTERS CONFIGURATION The different DAC registers must be configured for 48kHz audio frequency: this is the reference frequency. The STA003T will use these parameters to derivate the register configurations for the other audio frequencies (32, 24, 16, 12, 8 KHz) according to the bistream informations. The STA003T DAC and PLL register must be configured according to the following steps: 1) OCLK_Freq determination from the DAC oversampling factor O_FAC. As all STA003T registers must be configured for 48KHz reference frequency, the OCLK frquency is: OCLK_Freq = O_FAC ⋅ 48KHz ex: O_FAC = 384, OCLK_Freq = 18.432MHz 2) PCMDIVIDER (0 x 54) register configuration. The PCMDIVIDER register is used to configure the frequency ratio between OCLK_Freq and SCKT_Freq: OCLK_Freq SCKT_Freq = (2 ⋅ (1 + PCMDIVIDER)) The SCKT signal is the bit clock for the DAC serial output. The SCKT frequency depends on the number of bits to be transmitted to the DAC during one LRCKT (Left/Right clock) clock period. These number of bit depends on the DAC precision (16, 18, 20 or 24bits) and on the mode that is used to transmit the data to the DAC (see figure 8). Once the PCMCONF register is set according to the DAC requirements, the number of SCKT clock periods per LRCKT clock period is 16x2 or 32x2. a) LRCKT_period = 16x2 SCKT_periods SCKT_Freq = LRCKT_Freq ⋅ 32 = OCLK_Freq = (2 ⋅ (1+PCMDIVIDER)) As the reference audio frequency is 48 KHz, the previous relation becomes: 48KHz ⋅ 32 = 48kHz ⋅ O_FAC (2 ⋅ (1+ PCMDIVIDER)) O_FAC 128 256 384 30/32 OCLK_Freq at 48KHz 6.144MHz 12.288MHz 18.432MHz Consequently: PCMDIVIDER = (O_FAC/64)-1 ex: O_FAC = 384, PCMCONF[1:0] = 00, PCMDIVIDER = 5 b) LRCKT_period = 32x2 SCKT_periods SCKT_Freq = LRCKT_Freq ⋅ 64 = OCLK_Freq = (2 ⋅ (1+PCMDIVIDER)) Consequently: PCMDIVIDER = (O_FAC/128)-1 3) Configuration of the PLL registers to set OCLK_FREQ to the desired value computed in step 1. The PLL configuration in direct relation with the XTI input clock frequency (14.72 MHz). 1 OCLK_freq = ⋅ 1 + MFSDF(X) PLLFRAC 14.72MHz ⋅ ⋅ PLLCTL_M +1 + 65536 1 + PLLCTL_N * MFSDF(X) is the value of the MFSDF(X)(0x61) register. * PLLCTL_N is the value of the PLLCTL_N (0x07) register. * PLLCTL_M is the value of the PLLCTL_N (0x07) register. * PLLFRAC (decimal) is the value of the PLLFRAC_H and PLLFRAC_L registers as PLLFRAC = 256 ⋅ PLLFRAC_H + PLLFRAC_L. The following table gives the possible values for these registers according to different OCLK_Freq values. Other values can be supported on request to STMicroelectronics. PLLCTL_N PLLCTL_M PLLFRAC MFSDF 0 0 0 12 12 11 23365 23365 34193 31 15 9 STA003T mm DIM. MIN. TYP. A inch MAX. MIN. TYP. 2.65 MAX. 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 C 0.5 c1 0.020 45° (typ.) D 17.7 18.1 0.697 0.713 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 F 7.4 7.6 0.291 0.299 L 0.4 1.27 0.016 0.050 S OUTLINE AND MECHANICAL DATA SO28 8 ° (max.) 31/32 STA003T Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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