STEL-1172B
Data Sheet
STEL-1172B
(50 MHz)
32-Bit Resolution
CMOS Numerically
Controlled Oscillator
R
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FEATURES
CIRCUIT DESCRIPTION
■ 32 BIT FREQUENCY RESOLUTION
■ PARALLEL SINE AND COSINE
The STEL-1172B Numerically Controlled Oscillator
(NCO) generates digital sine and cosine signals of very
precise frequency to be used directly in digital signal
processing applications or in conjunction with a D/A
converter in analog frequency generation applications.
The device, implemented with low power CMOS, can
operate with clock frequencies as high as 50 MHz.
(40 MHz over the military temperature range, 55° C to
+125° C). The NCO is designed to interface with an
eight bit microprocessor bus.
OUTPUTS
■ 50 MHz CLOCK FREQUENCY (0° TO
70°C)
■ 8-BIT INTERNAL SINE AND COSINE
AMPLITUDE RESOLUTION
■ 10-BIT INTERNAL SINE AND COSINE
PHASE RESOLUTION
■ 12-BIT PHASE OUTPUT AVAILABLE
■ MILITARY AND COMMERCIAL
The NCO maintains a record of phase which is accurate
to 32 bits of resolution. At each clock cycle, the number
stored in the 32 bit ∆-phase register is added to the
previous value of the phase accumulator. The number
in the phase accumulator represents the current phase of
the synthesized sine and cosine functions. The number in
the ∆-phase register represents the change of phase for
each cycle of the clock. This number is directly related
to the output frequency by the following:
TEMPERATURE RANGES AVAILABLE
■ MICROPROCESSOR BUS COMPATIBLE
■ PIN COMPATIBLE WITH ST-1172A
■ CASCADABLE FOR ULTRA HIGH
RESOLUTION
■ LOW POWER CMOS
APPLICATIONS
■ FREQUENCY SYNTHESIZERS
■ HI-SPEED FREQUENCY HOPPED
■
■
■
fo=
SOURCES
SINGLE SIDEBAND CONVERTERS
BASEBAND RECEIVERS
DIGITAL SIGNAL PROCESSORS
fc x ∆-Phase
232
where: fo is the frequency of the output signal
and: fc is the clock frequency.
BLOCK DIAGRAM
SYNC
CARRY OUT
LDSTB
Data7-0
32
2
PHASE3-2
8
WRN
COSINE7-0
ADDR.
SELECT
LOGIC
BLOCK
BUFFER
REGISTER
BLOCK
-PHASE
REGISTER
BLOCK
32
32-BIT
PHASE
ACCUMULATOR
BLOCK
10
(PHASE1-0)
8
MUX
BLOCK
2
PHASE11-4
ADDR1-0
8
SINE7-0
CARRY IN
RESET
10
CLOCK
SELECT A,B
COSINE
LOOKUP
TABLE
BLOCK
SINE
LOOKUP
TABLE
BLOCK
8
(PHASE11-4)
2
TCP 54836.c
STEL-1172B
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FUNCTIONAL DESCRIPTION
The phase noise of the NCO output signal may
be determined by knowing the phase noise of the
clock signal input and the ratio of the output frequency to the clock frequency. This ratio squared
times the phase noise power of the clock specified in a
given bandwidth is the phase noise power that may
be expected in that same bandwidth relative to the
output frequency.
The sine and cosine signals are generated from
the 10 most significant bits of the phase accumulator.
The frequency of the NCO is determined by the
number stored in the ∆−phase register which may be
programmed by an eight-bit microprocessor.
The STEL-1172B NCO generates digitized
sampled sine and cosine signals where the sampling
function is the clock. If the output frequency is very
low with respect to the clock (<fc/1024), then the
NCO output will sequence through each of the 1024
states of the sine function stored in the lookup table.
As the output frequency is increased with respect to
the clock, the sine function appears more discontinuous as there are fewer samples in each cycle. At the
Nyquist limit, when the output frequency is exactly half
the clock, the output waveform reduces to a square
wave. The practical upper limit of the NCO output
frequency is about 40% of the clock frequency
because spurious components created by sampling,
which are at a frequency greater than half the clock
frequency, become difficult to remove by filtering.
The NCO achieves its high operating frequency
by making extensive use of pipelining in its architecture. The pipeline delays within the NCO represent
34 clock cycles. This effectively limits the minimum
possible frequency switching period of the NCO.
After new frequency data is entered the load command is given. After the 34 cycle pipeline delay the
output will instantaneously switch frequency while
maintaining phase coherence. After this the next new
frequency may be entered. If a 50 MHz clock were
utilized the NCO could be continuously switched
between programmed frequencies with a minimum
practical average switching time of about 1 µsec.
PIN CONFIGURATION
ADDR 1
COS 5
1
40
2
39
COS 6
3
38
CLOCK
V SS
4
37
5
36
6
35
COS 2
ADDR 0
WRN
LDSTB
CARRY IN
DATA
0
DATA
5
6
COS 1
COS 0
7
34
DATA
8
33
DATA
2
SIN 1
9
32
DATA
4
SIN 2
SIN 3
10
31
DATA
3
11
30
SYNC
SIN 4
12
29
DATA
1
SIN 5
SIN 7
13
28
DATA
7
14
27
RESET
COS 7
15
26
COS 4
V SS
16
25
SEL B
17
24
23
V DD
COS 3
CARRY OUT
PHASE
2
18
PHASE
3
19
22
20
21
SEL A
Seating
plane
0.15" typ.
0.13" typ.
0.1" ± 0.01"
Note: tolerance not cumulative
0.55"
typ.
2.00 max.
0.6"
(at seating plane)
Package: 40 pin plastic DIP
Thermal coefficient, θjc = 15°/W
Note: pin spacing for Ceramic
DIP is the same
SIN 6
SIN 0
3
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0.2"
max.
STEL-1172B
INPUT SIGNALS
FUNCTION BLOCK
DESCRIPTION
RESET
The RESET input is synchronous with the CLOCK input.
When RESET goes to a logic high level all registers except the
32 bit input buffer and ∆-Phase register are cleared within 20
nsecs. of the next rising edge of the CLOCK. The output data
and Phase Accumulator are cleared to zero. After the RESET
returns to a logic zero the chip requires 37 rising clock edges to
resume normal operation. For the first two of these cycles the
output data will be 00H and then 80H, respectively. For the
remaining 35 clock cycles the SIN and COS outputs remain at the
value corresponding to zero phase, i.e. 129, or 81H. Normal
operation will then commence, starting at zero phase
ADDRESS SELECT LOGIC BLOCK
This block controls the writing of data into the device via the
DATA7-0 inputs. The data is written into the device on the falling
edge of the WRN input, and the register into which the data is
written is selected by the ADDR1-0 inputs.
BUFFER REGISTER BLOCK
The Buffer Register is used to temporarily store the ∆-Phase data
written into the device. This allows the data to be written
asynchronously as four bytes per 32-bit ∆-Phase word. The data
is transferred from this register into the ∆-Phase Register after a
rising edge on the LDSTB input.
CLOCK
All synchronous functions performed within the NCO are
referenced to the rising edge of the CLOCK input. The CLOCK
signal should be nominally a square wave at a maximum
frequency of 50 MHz. A non-repetitive CLOCK waveform is
permissible as long as the minimum duration positive or
negative pulse on the waveform is always greater than 8
nanoseconds. At each rising edge of the CLOCK signal the
contents of the phase accumulator are added to the number
stored in the ∆-Phase register, and the result is placed in the Phase
Accumulator.
∆-PHASE REGISTER BLOCK
This block controls the updating of the ∆-Phase word used in
the Accumulator. The frequency data from the Mux Block is
loaded into this block after a rising edge on the LDSTB input.
The SYNC output, which indicates the instant of frequency
change at the output at the end of the pipeline delay, is generated
in this block.
PHASE ACCUMULATOR BLOCK
This block forms the core of the NCO function. It is a high-speed,
pipelined, 32-bit parallel accumulator, generating a new sum in
every clock cycle. A carry input (the CARRY IN input) allows the
resolution of the accumulator to be expanded by means of an
auxiliary NCO or phase accumulator. The overflow signal is
discarded (and is available at the CARRY OUT pin), since the
required output is the modulo (232) sum only. This represents
the modulo (2π) phase angle.
WRN
The information on the 8-bit data bus is transferred to the buffer
register selected by ADDR1 and ADDR0 on the falling edge of
the WRN input.
LDSTB
On the rising edge of the clock following the rising edge of the
LDSTB input the information in the four buffer registers is
transferred to the ∆-Phase Register. The frequency at the NCO
output will change 34 clock cycles after the LDSTB command due
to pipelining delays.
SINE AND COSINE LOOKUP TABLE BLOCKS
These blocks are the sine and cosine memories. The 10 most
significant bits from the Phase Accumulator are used to address
this memory to generate the 8-bit SIN7-0 and COS7-0 outputs.
ADDR1 and ADDR0
The ADDR1 and ADDR0 signals control the use of the DATA7-0 bus
according to the table:
MUX BLOCK
The twelve most significant bits from the Phase Accumulator
Block are available at the output via the MUX Blocks as
alternatives to the SIN7-0 and COS7-0 outputs. The MUX Blocks
are controlled by the SELECT A and SELECT B inputs.
STEL-1172B
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ADDR0
4
ADDR1
∆-Phase Register Field
1
1
Bits 0 (LSB) through 7
0
1
Bits 8 through 15
1
0
Bits 16 through 23
0
0
Bits 24 through 31 (MSB)
OUTPUT SIGNALS
CARRY OUT
Each time the contents of the phase accumulator exceeds the
maximum value that can be represented by a 32 bit number the
CARRY OUT signal goes high for one clock cycle. When two
NCOs are cascaded to obtain 64 bit frequency resolution the
CARRY OUT of the lower order NCO must be connected to
the CARRY IN of the higher order NCO.
The least significant bit of the input data bus always maps into
the least significant bit of the ∆-Phase Register field.
DATA7 through DATA0
The eight bit DATA7-0 bus is used to program the 32 bit ∆-Phase
Register. DATA0 is the least significant bit of the bus. To change
all 32 bits of the ∆-Phase Register, the DATA7-0 bus must be
sequentially used four times in conjunction with the WRN,
ADDR0 and ADDR1 signals.
SIN7-0 and COS7-0
The sine and cosine functions which are presented on the SIN7-0
and COS7-0 buses are derived from the 10 most significant bits of
the phase accumulator. The 8-bit sine and cosine functions
are presented in offset binary format with a minimum value of
00H and a maximum value of FFH. SIN7/COS7 are the MSBs.
When the phase accumulator is zero, the decimal value of the SIN
output is 81H. The nominal phase (in degrees) of the sine and
cosine outputs may be determined by multiplying the decimal
equivalent of the ten most significant bits of the phase
accumulator by (360/1024) and adding (360/2048). The average
amplitude over a full cycle is 127.5 decimal. See the description
of SELECT A/B and PHASE for the alternate use of the SIN70 and COS7-0 buses.
SELECT A
When SELECT A is a logic 0, the sine function appears on the
SIN7-0 bus. When SELECT A is a logic 1, the eight most
significant bits of the phase accumulator appear on this bus. The
twelve most significant bits of the 32 bit Phase Accumulator are
available externally. The eight most significant bits appear on the
SIN bus and are labeled PHASE11 (MSB) through PHASE 4.
Output
Pin
Pin
Name
Function:
SELECT A =0
Function:
SELECT A =1
14
SIN7
SIN7 (MSB)
PHASE4
22
SIN6
SIN6
PHASE5
13
SIN5
SIN5
PHASE6
12
SIN4
SIN4
PHASE7
11
SIN3
SIN3
PHASE8
10
SIN2
SIN2
PHASE9
9
SIN1
SIN1
PHASE10
21
SIN0
SIN0 (LSB)
PHASE11 (MSB)
PHASE11-0
The twelve most significant bits of the 32 bit phase accumulator
are available as outputs of the NCO. PHASE11 is the most
significant bit of the 32 bit phase accumulator. The eight most
significant PHASE bits are multiplexed on the SIN bus (see
description of SELECT A input). The next two significant bits
(PHASE2 and PHASE3) are available continuously on pins 18
and 19 respectively. The two least significant bits (PHASE1 and
PHASE0) are multiplexed on the COS bus (see description of
SELECT B input).
SELECT B
When SELECT B is a logic 1 the two most significant bits of
the cosine function appear on output pins 3 and 15. When Select
B is a logic 0 pin 15 provides the signal PHASE1 and pin 3
provides the signal PHASE0. PHASE1 and PHASE0 are the
eleventh and twelfth most significant bits of the phase
accumulator, with PHASE0 being the least significant accessible
bit.
SYNC
The normally high SYNC output goes low for one clock cycle 35
rising clock edges after a RESET and 34 rising clock edges after
a LDSTB command. If two NCOs are cascaded for higher
frequency resolution the SYNC output of the lower order NCO
must be connected to the LDSTB input of the higher order
NCO to insure a phase continuous frequency transition.
CARRY IN
Normal operation of the NCO requires that the CARRY IN be
set at a logic 0. When CARRY IN is a logic 1 the effective value
of the ∆-phase register is increased by one. If two NCOs are
cascaded together to obtain 64 bits of frequency resolution the
CARRY OUT of the lower order NCO is connected to the
CARRY IN of the higher order NCO.
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STEL-1172B
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Warning: Stresses greater than those shown below may cause permanent damage to the device.
Exposure of the device to these conditions for extended periods may also affect device reliability. All
voltages are referenced to VSS.
Symbol
Tstg
Parameter
Range
Units
to +125
{ 40
65 to +150
Storage Temperature
°C (Plastic package)
°C (Ceramic package)
VDDmax
Supply voltage on VDD
0.3 to + 7
volts
VI(max)
Input voltage
0.3 to VDD + 0.3
volts
Ii
DC input current
± 10
mA
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
Ta
Parameter
Range Units
Supply Voltage
Operating Temperature (Ambient)
D.C. CHARACTERISTICS
+5 ± 5%
{ +5
± 10%
0 to +70
{ 55
to +125
(Operating Conditions:
Volts
(Commercial)
Volts
(Military)
°C
(Commercial)
°C
(Military)
VDD= 5.0 V ±5%, VSS = 0 V, Ta= 0° to 70° C, Commercial
VDD= 5.0 V ±10%, VSS = 0 V, Ta = 55° to 125° C, Military)
Symbol
Parameter
Min.
Typ.
Max.
Units
IDD(Q)
Supply Current, Quiescent
1.0
mA
IDD
Supply Current, Operational
3.0 mA/MHz
VIH(min)
High Level Input Voltage
Conditions
Static, no clock
Standard Operating Conditions
2.0
volts
Logic '1'
Extended Operating Conditions
2.25
volts
Logic '1'
VIL(max)
Low Level Input Voltage
0.8
volts
Logic '0'
IIH(min)
High Level Input Current
10
µA
VIN = VDD
IIL(max)
Low Level Input Current
130
µA
VIN = VSS
VOH(min)
High Level Output Voltage
volts
IO = 4.0 mA
VOL(max)
Low Level Output Voltage
IOS
Output Short Circuit Current
CIN
COUT
15
45
2.4
4.5
0.2
0.4
volts
IO = +4.0 mA
20
65
130
mA
VOUT = VDD, VDD = max
10
45
130
mA
VOUT = VSS, VDD = max
pF
pF
All inputs
All outputs
Input Capacitance
Output Capacitance
STEL-1172B
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4
6
A.C. CHARACTERISTICS
(Operating Conditions: VDD= 5.0 V ±5%, VSS = 0 V, Ta= 0° to 70° C, Commercial
VDD= 5.0 V ±10%, VSS = 0 V, Ta = 55° to 125° C, Military)
(Commercial)
Max.
(Military)
Symbol
Parameter
Min.
Min.
Max.
Units Conditions
t RS
RESET pulse width
30
35
nsec.
t SR
RESET to CLOCK Setup
10
10
nsec.
t SU
DATA or ADDR
5
6
nsec.
5
6
nsec.
to WRN Setup, and
LDSTB to CLOCK Setup
t HD
DATA or ADDR
to WRN Hold, and
LDSTB to CLOCK Hold
t CH
CLOCK high
8
10
nsec.
fCLK = max.
t CL
CLOCK low
8
10
nsec.
fCLK = max.
tW
WRN or FRLD pulse width
20
25
nsec.
t CD
CLOCK to output delay
t SD
SEL A/B to SIN/COS delay
5
10
3
20
13
nsec.
Load = 15 pF
25
nsec.
Load = 15 pF
NCO RESET SEQUENCE
t RS
t SR
RESET
35 CLOCK EDGES
CLOCK
1
2
3
4
32
33
34
35
36
37
SYNC
SIN 7-0
00 H
80 H
81 H
VALID
COS 7-0
00 H
80 H
FF H
VALID
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STEL-1172B
NCO FREQUENCY CHANGE
ADDR
1-0
DON'T CARE
DON'T CARE
t SU
WRN
t HD
t WR
DATA
7-0
DON'T CARE
DON'T CARE
35 CLOCK
EDGES
CLOCK
t LS 1
t CH
2
3
34
35
36
37
t CL
LDSTB
SYNC
SELECT A
SELECT B
t SO
PHASE
t CD
SIN/COS
SIN 7-0, COS 7-0
STEL-1172B
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OLD
FREQUENCY
NEW
FREQUENCY
TYPICAL APPLICATION
HIGH-SPEED HOPPING 66-74 MHz SYNTHESIZER
Data7-0
ADDR1-0
8
2
STEL-1172B
NCO
SINE
8
LDSTB
RESET
BPF
2-10
MHz
D/A
CLK
BPF
66-74
MHz
66-74 MHz
CLK
64 MHz
OSCILLATOR
CLOCK
If the STEL-1172B is combined with a high-speed 8-bit video DAC, signals with spectral purity of better
than 55 dBc can be generated up to 10 MHz. In this way a signal can be generated in the 66 to 74 MHz
band after filtering and upconversion. Because of the phase continuous frequency switching
characteristics of the STEL-1172B this architecture is suitable for Frequency Hopping Spread Spectrum
applications.
SPECTRAL PURITY
spurious levels which are theoretically about -60 dBc.
The highest output frequency the NCO can generate is
half the clock frequency (f c /2), and the spurious
components at frequencies greater than f c/2 can be
removed by filtering. As the output frequency fo of the
NCO approaches fc/2 the "image" spur at fc fo also
approaches f c/ 2 from above. If the programmed
output frequency is very close to fc/2 it will be virtually
impossible to remove this "image" spur by filtering.
For this reason, the maximum practical output
frequency of the NCO should be limited to about 40%
of the clock frequency.
In many applications the NCO is used with a digital to
analog converter (DAC) to generate an analog
wavefor m which approximates an ideal sinewave.
The spectral purity of this synthesized waveform is a
function of many variables including the phase and
amplitude quantization, the ratio of the clock
frequency to output frequency, and the dynamic
characteristics of the DAC.
The sine and cosine signals generated by the
STEL-1172B have eight bits of amplitude resolution
and ten bits of phase resolution which results in
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STEL-1172B
when the output frequency is a significant fraction of
the clock frequency.
The higher the resolution of the NCO outputs the
greater the spectral purity. Each additional bit used in
quantizing the phase and amplitude of the sine function (assuming equal resolution for each) provides 6
dB improvement in spectral purity. For this reason, 12
bits of phase information are brought to the STEL1172B outputs. It is possible to use these signals with
an external sine ROM to generate sine waves which
have spurious levels as low as -72 dBc.
A spectral plot of the NCO output after conversion
with a DAC (AD9703) is shown below. In this case the
clock frequency is 50 MHz and the output frequency is
programmed to 5.6789 MHz. The maximum spur level
obser ved over the entire useful output frequency
range in this case is 55 dBc. Under other conditions
the spurious levels may be greater than this due to
DAC limitations or clock feedthrough problems
relating to grounding on the PC board. At higher
output frequencies the waveform produced by the
DAC will have large output changes from sample to
sample. For this reason the settling time of the DAC
should be short in comparison to the clock period . As
a general rule the DAC used should have the lowest
possible glitch energy as well as the shortest possible
settling time.
In some applications the NCO is used with two DACs
to generate analog sine and cosine signals to drive a
single sideband mixer. If the sine and cosine functions
were ideal a typical single sideband mixer would
provide 20 to 30 dB of LO and image suppression. This
performance can be significantly degraded if an NCO
is used to generate these signals near the maximum
NCO frequency. It is recommended that care be taken
when designing the STEL-1172B into such systems
TYPICAL SPECTRUM
Output frequency:
5.6789 MHz
Clock frequency:
50.0 MHz
Frequency Span:
0 to 20 MHz
Reference Level:
0 dBm
Resolution Bandwidth: 1 kHz
Video Bandwidth:
3 kHz
Scale:
Log, 10 dB/div
STEL-1172B
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whatsoever, and Intel disclaims any express or implied
warranty, relating to sale and/or use of Intel® products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent,
copyright or other intellectual property right. Intel products
are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
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