3.3V/5V 2.5GHz PECL/ECL 1:4 FANOUT BUFFER WITH 2:1 INPUT MUX Micrel ECL Pro™ ECL Pro™ SY100EP15V SY100EP15V FINAL FEATURES ■ High-speed 1:4 PECL/ECL fanout buffer ■ 2:1 multiplexer input ■ Guaranteed AC parameters over temp/voltage: • > 2.5GHz fMAX (toggle) • < 225ps rise/fall times • < 25ps within device skew • < 425ps propagation delay (CLK-to-Q) ■ Low jitter design: • < 1ps (rms) cycle-to-cycle jitter • < 1ps (pk-pk) total jitter ■ Flexible power supply: 3.3V/5V ■ Wide operating temperature range: –40°C to +85°C ■ VBB reference for AC-coupled or single-ended applications ■ Output enable/disable function ■ 100K PECL/ECL compatible logic ■ Input accepts PECL/LVPECL/ECL/HSTL logic levels ■ Available in a 16-Pin TSSOP package ECL Pro™ DESCRIPTION The SY100EP15V is a high-speed, low-skew, PECL/ECL 1:4 precision fanout buffer with a 2:1 mux front end in a small 16-pin TSSOP package. The 2:1 mux input accepts a single-ended PECL/ECL source (CLK1) and a differential PECL/ECL/HSTL source (CLK0). All I/O pins are 100K EP PECL/ECL logic compatible. AC performance is guaranteed over the industrial –40°C to +85°C temperature range and 3.3V to 5V supply voltage. This device will operate in PECL/LVPECL or ECL/LVECL mode. For clock applications, the high-speed design combined with an extremely fast rise/fall time of less than 225ps produces a toggle frequency as high as 2.5GHz (~400mVPP swing). A VBB output reference pin is available for AC–coupled and single-ended input applications. In addition, a synchronous output enable function is provided. The SY100EP15V is part of Micrel’s high-speed, precision edge timing and distribution family. For applications that require a different I/O combination, consult Micrel's website at www.micrel.com, and choose from a comprehensive product line of high-speed, low-skew fanout buffers, translators, and clock dividers. PIN CONFIGURATION/BLOCK DIAGRAM Q0 1 /Q0 2 16 VCC Q D Q1 3 /Q1 4 Q2 5 15 /EN 14 CLK1 1 0 13 VBB 12 /CLK0 /Q2 6 11 CLK0 Q3 7 10 SEL /Q3 8 9 VEE ECL Pro is a trademark of Micrel, Inc. 1 Rev.: C Amendment: /0 Issue Date: March 2003 ECL Pro™ SY100EP15V Micrel PIN DESCRIPTION Pin Pin Number Function 1, 2, 3, 4 5, 6, 7, 8 Q0 – Q3 /Q0 – /Q3 9 VEE Negative Power Supply: For PECL/LVPECL applications, connect to GND. 10 SEL 100KEP (LV)PECL/(LV)ECL Compatible 2:1 Mux Input Select Control. See “Truth Table.” The select (SEL) pin includes an internal 75kΩ pull-down resistor. Default condition when left floating is LOW, and CLK0 input is selected. 11, 12 CLK0, /CLK0 Differential (LV)PECL/(LV)ECL/HSTL Compatible Input: The inputs include an internal 75kΩ pull-down resistor on CLK0 and internal 75kΩ pull-up and pull-down on /CLK0. Default condition for CLK0 is LOW when left floating and VCC/2 for /CLK0 when left floating. 13 VBB Reference Output Voltage: This reference is typically used to bias the unused inverting input for single-ended input applications, or as the termination point for AC-coupled differential input applications. VBB reference value is approximately VCC–1.3V, and tracks Vcc 1:1. Maximum sink/source capability for VBB is 0.50mA. For single ended inputs, connect to the unused input through a 50Ω resistor. Decouple the VBB pin with a 0.01µF capacitor to VCC. 14 CLK1 Single-Ended (LV)PECL/(LV)ECL Compatible Input: This pin includes an internal 75kΩ pull-down resistor. Default condition is LOW when left floating. 15 /EN 100KEP (LV)PECL/(LV)ECL Compatible Input: This synchronous pin controls the output state. See “Truth Table.” To ensure proper synchronous operation, adhere to the Set-up and Hold times, as described in the AC electrical table. When /EN pin goes HIGH, Q outputs go LOW, and /Q outputs go HIGH on the next falling clock transition. This synchronous operation avoids any chance of generating a runt pulse. 16 VCC Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors. Outputs 0 through 3: 100KEP (LV)PECL/(LV)ECL compatible differential outputs. Terminate with 50Ω to VCC–2V. Unused output pairs may be left floating, or pulled-down with a 2kΩ resistor to the most negative supply. Unused single-ended outputs must have a balanced load. For AC-coupled applications, the output stage emitter follower must have a DC current path to ground. See “Termination” section. TRUTH TABLE(1) CLK0 CLK1 SEL /EN Q L X L L L H X L L H X L H L L X H H L H X L H L H H L X Note 1. = Negative edge. 2 ECL Pro™ SY100EP15V Micrel ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating Value Unit 6.0 V –6.0 to 0 +6.0 to 0 V 50 100 mA ±0.5 mA VCC – VEE Power Supply Voltage VIN Input Voltage (VCC = 0V, VIN not more negative than VEE) Input Voltage (VEE = 0V, VIN not more positive than VCC) IOUT Output Current IBB VBB Sink/Source Current(2) TA Operating Temperature Range –40 to +85 °C TSTORE Storage Temperature Range –65 to +150 °C θJA Package Thermal Resistance (Junction-to-Ambient) 115 75 65 °C/W θJC Package Thermal Resistance (Junction-to-Case) 21 °C/W –Continuous –Surge –Still-Air (single-layer PCB) –Still-Air (multi-layer PCB) –500lfpm (multi-layer PCB) Note 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability. Note 2. Due to the limited drive capability, use for inputs of same package only. DC ELECTRICAL CHARACTERISTICS(1) TA = –40°C Symbol VCC TA = +25°C TA = +85°C Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Power Supply Voltage (PECL) (LVPECL) (ECL) (LVECL) 4.5 2.97 –5.5 –3.63 5.0 3.3 –5.0 –3.3 5.5 3.63 –4.5 –2.97 4.5 2.97 –5.5 –3.63 5.0 3.3 –5.0 –3.3 5.5 3.63 –4.5 –2.97 4.5 2.97 –5.5 –3.63 5.0 3.3 –5.0 –3.3 5.5 3.63 –4.5 –2.97 Unit Condition V ICC Power Supply Current — — 70 — 52 72 — — 75 mA IIH Input HIGH Current — — 150 — — 150 — — 150 µA VIN = VIH IIL Input LOW Current CLK0, CLK1 /CLK0 0.5 –150 — — — — 0.5 –150 — — — — 0.5 –150 — — — — µA µA VIN = VIL VIN = VIL Input Capacitance (TSSOP) — — — — 1.0 — — — — pF CIN Note 1. 100KEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. 3 ECL Pro™ SY100EP15V Micrel (100KEP) LVPECL DC ELECTRICAL CHARACTERISTICS(1) VCC = 3.0V ±10%, VEE = 0V TA = –40°C Symbol Parameter TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition VIL Input LOW Voltage (Single-Ended) 1355 — 1675 1355 — 1675 1355 — 1675 mV VCC = 3.3V VIH Input HIGH Voltage (Single-Ended) 2075 — 2420 2075 — 2420 2075 — 2420 mV VCC = 3.3V VOL Output LOW Voltage 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV VCC = 3.3V VOH Output HIGH Voltage 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VCC = 3.3V VBB Reference Voltage(2) 1775 1875 1975 1775 1875 1975 1775 1875 1975 mV VCC = 3.3V VIHCMR Input HIGH Voltage Common Mode Range(3) 1.2 — VCC 1.2 — VCC 1.2 — VCC V Note 1. 100KEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. Input and output parameters varies 1:1 with VCC. Output load is 50Ω to VCC–2V. Note 2. VBB varies 1:1 with VCC. Note 3. The VIHCMR range is referenced to the most positive side of the differential input signal. (100KEP) PECL DC ELECTRICAL CHARACTERISTICS(1) VCC = 5.0V ±10%, VEE = 0V TA = –40°C Symbol TA = +25°C TA = +85°C Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition VIL Input LOW Voltage (Single-Ended) 3055 — 3375 3055 — 3375 3055 — 3375 mV VCC = 5V VIH Input HIGH Voltage (Single-Ended) 3775 — 4120 3775 — 4120 3775 — 4120 mV VCC = 5V VOL Output LOW Voltage 3055 3180 3305 3055 3180 3305 3055 3180 3305 mV VCC = 5V VOH Output HIGH Voltage 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV VCC = 5V 3475 3575 3675 3475 3575 3675 3475 3575 3675 mV VCC = 5V 1.2 — VCC 1.2 — VCC 1.2 — VCC V VBB VIHCMR Note 1. Output Voltage Reference(2) Voltage(3) Input HIGH Common Mode Range 100KEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. Input and output parameters varies 1:1 with VCC. Output load is 50Ω to VCC–2V. Note 2. VBB varies 1:1 with VCC. Note 3. The VIHCMR range is referenced to the most positive side of the differential input signal. 4 ECL Pro™ SY100EP15V Micrel (100KEP) LVECL DC ELECTRICAL CHARACTERISTICS(1) VCC = 0V, VEE = –2.97V to –3.63V TA = –40°C Symbol Parameter Min. Typ. TA = +25°C Max. Min. Typ. TA = +85°C Max. Min. Typ. Max. Unit Condition VIL Input LOW Voltage (Single-ended) –1945 — –1625 –1945 — –1625 –1945 — –1625 mV VIH Input HIGH Voltage (Single-ended) –1165 — –880 — –880 — –880 mV VOL Output LOW Voltage –1945 –1820 –1695 –1945 –1820 –1695 –1945 –1820 –1695 mV 50Ω to VCC–2V VOH Output HIGH Voltage –1145 –1020 mV 50Ω to VCC–2V VBB Output Reference Voltage –1525 –1425 –1325 –1525 –1425 –1325 –1525 –1425 –1325 VIHCMR Input HIGH Voltage Common Mode Range(2) VEE +1.2 –895 — 0.0 –1165 –1145 –1020 VEE +1.2 –895 — 0.0 –1165 –1145 –1020 VEE +1.2 –895 — 0.0 mV V Note 1. 100KEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. Note 2. The VIHCMR range is referenced to the most positive side of the differential input signal. (100K) ECL DC ELECTRICAL CHARACTERISTICS(1) VCC = 0V, VEE = –4.5V to –5.5V TA = –40°C Symbol Parameter Min. Typ. TA = +25°C Max. Min. Typ. TA = +85°C Max. Min. Typ. Max. Unit Condition VIL Input LOW Voltage –1945 — –1625 –1945 — –1625 –1945 — –1625 mV VIH Input HIGH Voltage –1225 — –880 — –880 — –880 mV VOL Output LOW Voltage –1945 –1820 –1695 –1945 –1820 –1695 –1945 –1820 –1695 mV 50Ω to VCC–2V VOH Output HIGH Voltage –1145 –1020 mV 50Ω to VCC–2V VBB Output Reference Voltage –1525 –1425 –1325 –1525 –1425 –1325 –1525 –1425 –1325 VIHCMR Input HIGH Voltage Common Mode Range(2) VEE +1.2 –895 — 0.0 –1225 –1145 –1020 VEE +1.2 — –895 0.0 –1225 –1145 –1020 VEE +1.2 — –895 0.0 mV V Note 1. 100KEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. Note 2. The VIHCMR range is referenced to the most positive side of the differential input signal. HSTL INPUT DC ELECTRICAL CHARACTERISTICS VCC = 2.97V to 3.63V, VEE = 0V TA = –40°C Symbol Parameter TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit VIH Input HIGH Voltage 1200 — — 1200 — — 1200 — — mV VIL Input LOW Voltage — — 400 — — 400 — — 400 mV 5 ECL Pro™ SY100EP15V Micrel AC ELECTRICAL CHARACTERISTICS LVPECL: VCC = 2.97V to 3.63V, VEE = 0V; PECL: VCC = 4.5V to 5.5V, VEE = 0V ECL: VCC = 0V, VEE = –4.5V to –5.5V; LVECL: VCC = 0V, VEE = –2.97V to –3.63V TA = –40°C Symbol Parameter TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit fMAX(1) Maximum Frequency 2.5 — — 2.5 — — 2.5 — — GHz tPD PropagationDelay to Output PECL/ECL Diff. IN-to-Q IN (Single-Ended)-to-Q SEL-to-Q 275 250 250 — — — 425 450 450 275 250 250 375 400 400 425 450 450 275 250 250 — — — 425 450 450 ps ps ps 275 250 250 — — — 425 450 450 275 250 250 375 400 400 425 450 450 275 250 250 — — — 425 450 450 ps ps ps — — — — 25 150 — — 15 100 25 150 — — — — 25 150 ps ps /EN to CLK 100 0 — 100 0 — 100 0 — ps /EN to CLK 200 50 — 200 50 — 200 50 — ps — — 0.2 <1 1 — — — 0.2 <1 1 — — — 0.2 <1 1 — ps(rms) ps(pk-pk) LVPECL/LVECL Diff. IN-to-Q IN (Single-Ended)-to-Q SEL-to-Q tSKEW(2) Within-Device Skew Part-to-Part Skew tS(3) Set-Up Time tH(3) Hold Time (Diff.) (Diff.) Jitter(4) tJITTER Cycle-to-Cycle Total Jitter (622MHz clock)(5) VID Input Voltage Range 150 800 1200 150 800 1200 150 800 1200 mV t r, t f Output Rise/Fall Times (20% to 80%) 75 — 225 75 130 225 85 — 225 ps Note 1. fMAX is defined as the maximum toggle frequency. Measured with 750mV input signal, 50% duty cycle, output swing ≥ 400mV(diff), all loading with 50W to VCC–2V. Note 2. Skew is measured between outputs under identical transitions. Note 3. Set-up and hold times apply to synchronous applications that intend to enable/disable before then ext clock cycle. For asynchronous applications, set-up and hold time does not apply. Note 4. Cycle-to-cycle jitter definition: The variation in period between adjacent cycles over a random sample of adjacent cycle pairs. TJITTER_CC = Tn– Tn+1 where T is the time between rising edges of the output signal. Note 5. Total jitter definition: with an ideal clock input, no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value. PRODUCT ORDERING CODE Ordering Code Package Type Operating Range Marking Code SY100EP15VK4C K4-16-1 Commercial XEP15V SY100EP15VK4CTR(1) K4-16-1 Commercial XEP15V SY100EP15VK4I(2) K4-16-1 Industrial XEP15V SY100EP15VK4ITR(1, 2) K4-16-1 Industrial XEP15V Note 1. Tape and Reel. Note 2. Recommended for new designs. 6 ECL Pro™ SY100EP15V Micrel TERMINATION RECOMMENDATIONS +3.3V +3.3V ZO = 50Ω R1 130Ω R1 130Ω +3.3V R2 82Ω R2 82Ω Vt = VCC –2V ZO = 50Ω Figure 1. Parallel Termination–Thevenin Equivalent Note 1. Note 2. For +2.5V systems: R1 = 250Ω, R2 = 62.5Ω For +5.0V systems: R1 = 82Ω, R2 = 130Ω +3.3V +3.3V Z = 50Ω Z = 50Ω 50Ω 50Ω “source” 50Ω Rb “destination” (Optional) C1 0.01µF Figure 2. Three-Resistor “Y–Termination” Note 1. Note 2. Note 3. Note 4. Power-saving alternative to Thevenin termination. Place termination resistors as close to destination inputs as possible. Rb resistor sets the DC bias voltage, equal to Vt. For +3.3V systems Rb = 46Ω to 50Ω. For +5V systems, Rb = 110Ω. C1 is an optional bypass capacitor intended to compensate for any tr/tf mismatches. +3.3V +3.3V Q +3.3V R1 130Ω R1 130Ω ZO = 50Ω +3.3V 50Ω /Q VBB Vt = VCC –2V R2 82Ω R2 82Ω 0.01µF +3.3V Figure 3. Terminating Unused I/O Note 1. Unused output (/Q) must be terminated to balance the output. Note 2. Micrel's differential I/O logic devices include a VBB reference pin . Note 3. Note 4. Connect unused input through 50Ω to VBB. Bypass with a 0.01µF capacitor to VCC, not GND. For +2.5V systems: R1 = 250Ω, R2 = 62.5Ω. 7 ECL Pro™ SY100EP15V Micrel 16 LEAD TSSOP (K4-16-1) Rev. 01 MICREL, INC. TEL 1849 FORTUNE DRIVE SAN JOSE, CA 95131 + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB USA http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2003 Micrel, Incorporated. 8