3.3V/5V 3.2Gbps CML LOW POWER LIMITING POST AMPLIFIER w/TTL SD DESCRIPTION FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ Single 3.3V or 5V power supply Up to 3.2Gbps operation Low noise 50Ω CML data outputs; 60ps edge rates 1ps(p-p) max DJ, 1ps(rms) max RJ OC-TTL SD output with internal 5kΩ pull-up resistor TTL EN input Internal input 50Ω termination at inputs and outputs Programmable SD level set Available in a tiny 10-pin (3mm) MSOP and 16-pin MLF™ (3mm x 3mm) packages The SY88983V low-power limiting post amplifier is designed for use in fiber optic receivers. The device connects to typical transimpedance amplifiers (TIAs). The linear signal output from TIAs can contain significant amounts of noise and may vary in amplitude over time. The SY88983V quantizes these signals and outputs typically 800mVp-p voltage-limited waveforms. The SY88983V operates from a single +3.3V or +5V power supply, over temperatures ranging from –40°C to +85°C. With its wide bandwidth and high gain, signals with data rates up to 3.2Gbps and as small as 5mVp-p can be amplified to drive devices with CML inputs or AC-coupled PECL inputs. The SY88983V generates a signal detect (SD) opencollector TTL output with internal 5kΩ pull-up resistor. A programmable signal detect level set pin (SDLVL) sets the sensitivity of the input amplitude detection. SD asserts high if the input amplitude rises above the threshold set by SDLVL and deasserts low otherwise. SD can be fed back to the enable (EN) input to maintain output stability under a loss of signal condition. EN deasserts the true output signal without removing the input signal. Typically 4.6dB SD hysteresis is provided to prevent chattering. APPLICATIONS ■ ■ ■ ■ ■ ■ ■ SY88983V FINAL 1.25Gbps and 2.5Gbps Gigabit Ethernet 1062Mbps and 2Gbps Fibre Channel 155Mbps, 622Mbps and 2.5Gbps SONET/SDH Gigabit interface converter (GBIC) Small form factor transceivers Parallel 10G Ethernet High-gain line driver and line receiver TYPICAL APPLICATIONS CIRCUIT VCC SD EN 0.1µF DIN From Transimpedance Amp. DOUT SY88983V /DIN 0.1µF SDLVL GND VCC 0.1µF To CDR /DOUT VREF 200kΩ 0.1µF 0.1µF MLF™ and Micro LeadFrame are trademarks of Amkor Technology, Inc. Rev.: A 1 Amendment: /0 Issue Date: December 2002 Micrel SY88983V VCC EN SDLVL VCC PACKAGE/ORDERING INFORMATION 16 15 14 13 DIN 1 12 DOUT GND 2 11 GND /DIN 3 4 10 9 GND GND /DOUT EN 1 5 6 7 8 9 DOUT /DIN 3 8 /DOUT VREF 4 VCC VREF SD VCC 10 VCC DIN 2 SDLVL 5 7 SD 6 GND 10-Pin MSOP (K10-1) 16-Pin MLF™ (MLF-16) Ordering Information Part Number Package Type Operating Range Package Marking SY88983VKI K10-1 Industrial 983V SY88983VKITR* K10-1 Industrial 983V SY88983VMI MLF-16 Industrial 983V SY88983VMITR* MLF-16 Industrial 983V *Tape and Reel PIN DESCRIPTION Pin Number (MSOP) Pin Number (MLF™) Pin Name Type 1 15 EN TTL Input: Default is high. 2 1 DIN Data Input True data input w/50Ω termination to VREF. 3 4 /DIN Data Input Complementary data input w/50Ω termination to VREF. 4 6 VREF 5 14 SDLVL Input: Default is maximum sensitivity. 6 2, 3, 10, 11, EP GND Ground 7 7 SD Open Collector TTL Output with internal 5kΩ pullup resistor 8 9 /DOUT CML Output Complementary data output. 9 12 DOUT CML Output True data output. 10 5, 8, 13, 16 VCC Power Supply Pin Function Enable: Deasserts true data output when low. Reference Voltage: Placing a capacitor from VREF to VCC helps stablize SDLVL. Signal Detect Level Set: A resistor from this pin to VCC sets the threshold for the data input amplitude at which the SD output will be asserted. Device ground. Signal Detect: Asserts high when the data input amplitude rises above the threshold set by SDLVL. Positive power supply. 2 Micrel SY88983V Absolute Maximum Ratings(Note 1) Operating Ratings(Note 2) Supply Voltage (VCC) ....................................... 0V to +7.0V Enable Voltage (EN) ..............................................0 to VCC Signal Detect Level Set Voltage (SDLVL) ............................................. (VCC –1.3V) to VCC Data Input Continuous Current (DIN, /DIN) ................... 1mA Data Output Current (DOUT, /DOUT) ........................... 13mA Signal Detect Current (SD) .......................................... 5mA VREF Current (VREF) .................................................... 1mA Storage Temperature (TS) ....................... –55°C to +125°C Supply Voltage (VCC) .............................. +3.0V to +3.6V or ............................................................ +4.5V to +5.5V Ambient Temperature (TA) ......................... –40°C to +85°C Junction Temperature (TJ) ....................... –40°C to +120°C Package Thermal Resistance MLF™ (θJA) Still-Air .................................................... 59°C/W (ψJB) Still-Air .................................................... 32°C/W MSOP (θJA) Still-Air .................................................. 113°C/W (ψJB) Still-Air .................................................... 74°C/W Note 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability. Note 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. DC ELECTRICAL CHARACTERISTICS VCC = 3.0V to 3.6V or 4.5V to 5.5V; RLOAD = 50Ω to VCC; TA = –40°C to +85°C; typical values at VCC = 3.3V, TA = 25°C Symbol Parameter Condition Min Typ Max Units ICC Power Supply Current, Note 1 3.3V range 5V range 19 21 28 31 mA mA ICC Power Supply Current, Note 2 3.3V range 5V range 32 38 47 48 mA mA VREF VREF Voltage SDLVL SDLVL Level VOH SD Output HIGH Level Sourcing 100µA VOL SD Output LOW Level Sinking 2mA VIH EN Input HIGH Voltage VIL EN Input LOW Voltage IIH EN Input HIGH Current VIN = 2.7V VIN = VCC IIL EN Input LOW Current VIN = 0.5V VOH Output HIGH Voltage Note 3 VOL Output LOW Voltage Note 3 VOFFSET Differential Output Offset ZO Single-Ended Output Impedance VCC –1.3 V VCC –1.3 VCC V 2.4 VCC V 0.5 V 2.0 V 0.8 V 20 100 µA µA –0.3 mA VCC–0.020 VCC–0.005 VCC VCC–0.400 VCC–0.275 40 50 Note 1. Excludes current of CML output stage. See “Detailed Description.” Note 2. Total device current with no output load. Note 3. Output levels are based on a 50Ω to VCC load impedance. If the load impedance is different, the output level will be changed. 3 V V ±80 mV 60 Ω Micrel SY88983V AC ELECTRICAL CHARACTERISTICS VCC = 3.0V to 3.6V or 4.5V to 5.5V; RLOAD = 50Ω to VCC; TA = –40°C to +85°C; typical values at VCC = 3.3V, TA = 25°C. Symbol Parameter Condition Min Typ Max Units HYS SD Hysteresis Note 1 2 4.6 8 dB tOFF SD Release Time 0.1 0.5 µs tON SD Assert Time 0.2 0.5 µs tr,tf Differential Output Rise/Fall Time (20% to 80%) 60 120 ps 1 1 ps ps Note 2 tJITTER Deterministic (p-p) Random (rms) VID Differential Input Voltage Swing 5 1800 mVp-p VIS Single-Ended Input Voltage Swing 5 900 mVp-p VOD Differential Output Voltage Swing VSR SD Sensitivity Range AV(Diff) Differential Voltage Gain 38 dB B–3dB 3dB Bandwidth 2.2 GHz S21 Single-Ended Small Signal-Gain 32 dB Note 3 Note 4 550 800 10 26 Note 1. Electrical signal. Note 2. With input signal VID > 50mVp-p and 50Ω load. Note 3. Measured using K28.5 pattern at 2.488Gbps, VID = 100mVp-p Note 4. Input is a 200MHz square wave, tr < 300ps, 50Ω load. VID > 10mVp-p TYPICAL OPERATING CHARACTERISTICS 90 SD Assert/Deassert Level vs. RSDLVL 80 VID (mVP-P) 70 ASSERT 60 50 40 30 20 DEASSERT 10 0 10 100 1000 10000 100000 RSDLVL 4 mVp-p 50 mVp-p Micrel SY88983V DETAILED DESCRIPTION Signal Detect The SY88983V generates a chatter-free signal detect (SD) open-collector TTL output with internal 5kΩ pull-up resistor as shown in Figure 5. SD is used to determine that the input amplitude large enough to be considered a valid input. SD asserts high if the input amplitude rises above the threshold set by SDLVL and deasserts low otherwise. SD can be fed back to the enable (EN) input to maintain output stability under a loss of signal condition. EN deasserts low the true output signal without removing the input signals. Typically 4.6dB SD hysteresis is provided to prevent chattering. Signal Detect-Level Set A programmable signal detect-level set pin (SDLVL) sets the threshold of the input amplitude detection. Connecting an external resistor between VCC and SDLVL sets the voltage at SD LVL . This voltage ranges from V CC to VCC –1.3V. The external resistor creates a voltage divider between VCC and VCC –1.3V as shown in Figure 6. If desired, an appropriate external voltage may be applied rather than using a resistor. The smaller the external resistor, implying a smaller voltage difference from SDLVL to VCC, lowers the SD sensitivity. Hence, larger input amplitude is required to assert SD. Typical Operating Characteristics shows the relationship between the input amplitude detection sensitivity and the SDLVL setting resistor. Hysteresis The SY88983V provides typically 4.6dB SD electrical hysteresis. By definition, a power ratio measured in dB is 10log(power ratio). Power is calculated as V2IN/R for an electrical signal. Hence the same ratio can be stated as 20log(voltage ratio). While in linear mode, the electrical voltage input changes linearly with the optical power and hence the ratios change linearly. Therefore, the optical hysteresis in dB is half the electrical hysteresis in dB given in the datasheet. The SY88983V provides typically 2.3dB SD optical hysteresis. As the SY88983V is an electrical device, this datasheet refers to hysteresis in electrical terms. With 4.6dB SD hysteresis, a voltage factor of 1.7 is required to assert or deassert SD. The SY88983V low power limiting post amplifier operates from a single +3.3V or +5V power supply, over temperatures from –40°C to +85°C. Signals with data rates up to 3.2Gbps and as small as 4mVp-p can be amplified. Figure 1 shows the allowed input voltage swing. The SY88983V generates an SD output, allowing feedback to EN for output stability. SDLVL sets the sensitivity of the input amplitude detection. Input Amplifier/Buffer The SY88983V’s inputs are internally terminated with 50Ω to VCC –1.3V. Unless they are not affected by this internal termination scheme, upstream devices need to be ACcoupled to the SY88983V’s inputs. Figure 2 shows a simplified schematic of the input stage. The high sensitivity of the input amplifier allows signals as small as 5mVp-p to be detected and amplified. The input amplifier allows input signals as large as 1800mVp-p. Input signals are linearly amplified with a typically 38dB differential voltage gain. Since it is a limiting amplifier, the SY88983V outputs typically 800mVp-p voltage-limited waveforms for input signals that are greater than 10mVp-p. Applications requiring the SY88983V to operate with high-gain should have the upstream TIA placed as close as possible to the SY88983V’s input pins to ensure the best performance of the device. Output Buffer The SY88983V’s CML output buffer is designed to drive 50Ω lines. The output buffer requires appropriate termination for proper operation. An external 50Ω resistor to VCC or equivalent for each output pin provides this. Figure 3 shows a simplified schematic of the output stage and includes an appropriate termination method. Of course, driving a downstream device with a CML input that is internally terminated with 50Ω to VCC eliminates the need for external termination. As noted in the previous section, the amplifier outputs typically 800mVp-p waveforms across 25Ω total loads. The output buffer thus switches typically 16mA tailcurrent. Figure 4 shows the power supply current measurement which excludes the 16mA tail-current. 5 Micrel SY88983V DATA+ 2.5mV (Min.) DATA— 900mV (Max.) VIS(mVp-p) (DATA+) — (DATA—) 5mVp-p (Min.) VID(mVp-p) 1800mVp-p (Max.) Figure 1. Input Peak-to-Peak (VIS) vs. Input Differential Voltage (VID) VCC 0.1µF VREF VCC VCC VCC 50Ω 50Ω 50Ω 50Ω DOUT 50Ω 50Ω Z0 = 50Ω 0.1µF /DOUT Z0 = 50Ω 0.1µF D IN AC-Coupling Capacitors 0.1µF AC-Coupling Capacitors /DIN 16mA ESD STRUCTURE ESD STRUCTURE GND GND Figure 2. Input Structure Figure 3. Output Structure VCC VCC 5kΩ ICC 50Ω SD 16mA 50Ω Figure 5. SD Output Structure ESD STRUCTURE VCC RSDLVL SDLVL 16mA 3kΩ VCC –1.3V GND Figure 6. SDLVL Setting Circuit Figure 4. Power Supply Current Measurement 6 Micrel SY88983V FUNCTIONAL BLOCK DIAGRAM DIN Limiting Amplifer DOUT CML Buffer /DIN /DOUT VREF Enable VCC EN Level Detect GND SD SDLVL DESIGN PROCEDURE Layout and PCB Design Since the SY88983V is a high-frequency component, performance can be largely determined by the board layout and design. A common problem with high-gain amplifiers is the feedback from the large swing outputs to the input via the power supply. The SY88983V’s ground pins should be connected to the circuit board ground. Use multiple PCB vias close to the part to connect to ground. Avoid long, inductive runs which can degrade performance. 7 Micrel SY88983V 10 LEAD MSOP (K10-1) Rev. 00 8 Micrel SY88983V 16 LEAD MicroLEAD FRAME™ (MLF-16) 0.85 0.42 +0.18 —0.18 0.23 +0.07 —0.05 +0.15 —0.65 0.01 +0.04 —0.01 3.00BSC 1.60 +0.10 —0.10 0.65 +0.15 —0.65 0.20 REF. 2.75BSC 0.42 N 16 1 1 0.50 DIA PIN 1 ID +0.18 —0.18 2 2 2.75BSC 3.00BSC 3 3 1.60 +0.10 —0.10 4 4 12¡ max 0.42 +0.18 —0.18 SEATING PLANE 1.5 REF BOTTOM VIEW TOP VIEW CC 0.23 +0.07 —0.05 CL 4 0.01 +0.04 —0.01 SECTION "C-C" SCALE: NONE 0.5BSC 0.5 BSC 1. 2. 3. 4. DIMENSIONS ARE IN mm. DIE THICKNESS ALLOWABLE IS 0.305mm MAX. PACKAGE WARPAGE MAX 0.05mm. THIS DIMENSION APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.20mm AND 0.25mm FROM TIP. 5. APPLIES ONLY FOR TERMINALS FOR EVEN TERMINAL/SIDE Rev. 02 MICREL, INC. TEL 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel, Inc. © 2002 Micrel, Incorporated. 9