DATA SHEET MOS INTEGRATED CIRCUIT µPD442002-X 2M-BIT CMOS STATIC RAM 128K-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION Description The µPD442002-X is a high speed, low power, 2,097,152 bits (131,072 words by 16 bits) CMOS static RAM. The µPD442002-X is packed in 48-pin TAPE FBGA. Features • 131,072 words by 16 bits organization ★ • Fast access time : 50, 55, 70, 85, 100, 120 ns (MAX.) • Byte data control : /LB (I/O1 - I/O8), /UB (I/O9 - I/O16) • Low voltage operation (BB version : VCC = 2.7 to 3.6 V, BC version : VCC = 2.2 to 3.6 V, DD version : VCC = 1.8 to 2.2 V) • Low VCC data retention : 1.0 V (MIN.) • Operating ambient temperature : TA = –25 to +85 °C • Output Enable input for easy application Part number Access time Operating supply Operating ambient ns (MAX.) ★ ★ ★ µPD442002-BBxxX 50 Note 1 , 55, 70, 85 Supply current voltage temperature At operating At standby At data retention V °C mA (MAX.) µA (MAX.) µA (MAX.) 2.7 to 3.6 −25 to +85 4 2 30 Note 2 35 Note 3 40 Note 4 µPD442002-BCxxX 70, 85, 100 2.2 to 3.6 30 µPD442002-DDxxX 85, 100, 120 1.8 to 2.2 15 3 Notes 1. VCC ≥ 3.0 V ★ 2. Cycle time ≥ 70 ns ★ 3. Cycle time = 55 ns ★ 4. Cycle time = 50 ns The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M14670EJ6V0DS00 (6th edition) Date Published July 2001 NS CP (K) Printed in Japan The mark ★ shows major revised points. © 2000 µPD442002-X Ordering Information Part number ★ ★ µPD442002F9-BB55X-BC1 Package 48-pin TAPE FBGA (6×8) Access time Operating Operating ns (MAX.) supply voltage temperature V °C 2.7 to 3.6 −25 to +85 55, 50 Note µPD442002F9-BB70X-BC1 70 µPD442002F9-BB85X-BC1 85 µPD442002F9-BC70X-BC1 70 µPD442002F9-BC85X-BC1 85 µPD442002F9-BC10X-BC1 100 µPD442002F9-DD85X-BC1 85 µPD442002F9-DD10X-BC1 100 µPD442002F9-DD12X-BC1 120 BC version 1.8 to 2.2 DD version Marking Image Marking (XX) µPD442002F9-BB55X-BC1 B1 µPD442002F9-BB70X-BC1 B2 µPD442002F9-BB85X-BC1 B3 µPD442002F9-BC70X-BC1 C2 µPD442002F9-BC85X-BC1 C3 µPD442002F9-BC10X-BC1 C4 µPD442002F9-DD85X-BC1 D3 µPD442002F9-DD10X-BC1 D4 µPD442002F9-DD12X-BC1 D5 2 J S2M0-XX INDEX MARK Data Sheet M14670EJ6V0DS BB version 2.2 to 3.6 Note VCC ≥ 3.0 V Part number Remark Lot No. µPD442002-X Pin Configuration /xxx indicates active low signal. ×8) 48-pin TAPE FBGA (6× [ µPD442002F9-BBxxX-BC1 ] [ µPD442002F9-BCxxX-BC1 ] [ µPD442002F9-DDxxX-BC1 ] Top View Bottom View A B C D E F G H 1 A 2 3 4 5 6 6 1 2 3 4 5 6 /LB /OE A0 A1 A2 NC 5 A 4 3 2 1 6 5 4 3 2 1 NC A2 A1 A0 /OE /LB B I/O9 /UB A3 A4 /CS I/O1 B I/O1 /CS A4 A3 /UB I/O9 C I/O10 I/O11 A5 A6 I/O2 I/O3 C I/O3 I/O2 A6 A5 I/O11 I/O10 D GND I/O12 NC A7 I/O4 VCC D VCC I/O4 A7 NC I/O12 GND E VCC I/O13 NC A16 I/O5 GND E GND I/O5 A16 NC I/O13 VCC F I/O15 I/O14 A14 A15 I/O6 I/O7 F I/O7 I/O6 A15 A14 I/O14 I/O15 G I/O16 NC A12 A13 /WE I/O8 G I/O8 /WE A13 A12 NC I/O16 H NC A8 A9 A10 A11 NC H NC A11 A10 A9 A8 NC A0 - A16 : Address inputs I/O1 - I/O16 : Data inputs / outputs /CS : Chip Select /WE : Write Enable /OE : Output Enable /LB, /UB : Byte data select VCC : Power supply GND : Ground NC : No Connection Remark Refer to Package Drawing for the index mark. Data Sheet M14670EJ6V0DS 3 µPD442002-X Block Diagram VCC GND A0 A16 Address buffer Row decoder I/O1 - I/O8 I/O9 - I/O16 Input data controller Memory cell array 2,097,152 bits Sense amplifier / Switching circuit Column decoder Address buffer /CS /LB /UB /WE /OE 4 Data Sheet M14670EJ6V0DS Output data controller µPD442002-X Truth Table /CS /OE /WE /LB /UB Mode I/O Supply current I/O1 - I/O8 I/O9 - I/O16 H × × × × Not selected High impedance High impedance × × × H H Not selected High impedance High impedance L H H L × Output disable High impedance High impedance × L Output disable High impedance High impedance L L Word read DOUT DOUT L H Lower byte read DOUT High impedance H L Upper byte read High impedance DOUT L L Word write DIN DIN L H Lower byte write DIN High impedance H L Upper byte write High impedance DIN L × H L ISB ICCA Remark × : VIH or VIL Data Sheet M14670EJ6V0DS 5 µPD442002-X Electrical Specifications Absolute Maximum Ratings Parameter Symbol Supply voltage Product Rating µPD442002-BBxxX, µPD442002-BCxxX VCC µPD442002-DDxxX Input / Output voltage µPD442002-BBxxX, µPD442002-BCxxX VT µPD442002-DDxxX Unit –0.5 Note to +4.0 –0.5 Note to +2.7 V –0.5 Note to VCC+0.4 (4.0 V MAX.) –0.5 Note to VCC+0.4 (2.7 V MAX.) V Operating ambient temperature TA –25 to +85 °C Storage temperature Tstg –55 to +125 °C Note –3.0 V (MIN.) (Pulse width : 30 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Supply voltage VCC High level input voltage VIH Low level input voltage VIL Operating ambient TA µPD442002-BBxxX Condition µPD442002-BCxxX µPD442002-DDxxX Unit MIN. MAX. MIN. MAX. MIN. MAX. 2.7 3.6 2.2 3.6 1.8 2.2 V 2.7 V ≤ VCC ≤ 3.6 V 2.4 VCC+0.4 2.4 VCC+0.4 – – V 2.2 V ≤ VCC < 2.7 V – – 2.0 VCC+0.3 – – 1.8 V ≤ VCC < 2.2 V – – – – 1.6 –0.3 Note –25 +0.5 +85 –0.3 Note –25 +0.4 +85 –0.2 Note –25 VCC+0.2 +0.2 V +85 °C temperature Note –1.0 V (MIN.) (Pulse width : 20 ns) Capacitance (TA = 25°°C, f = 1 MHz) Parameter Symbol Test condition MIN. TYP. MAX. Unit Input capacitance CIN VIN = 0 V 8 pF Input / Output capacitance CI/O VI/O = 0 V 10 pF Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are not 100% tested. 6 Data Sheet M14670EJ6V0DS µPD442002-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2) Parameter Symbol µPD442002-BBxxX Test condition MIN. TYP. Unit MAX. Input leakage current ILI VIN = 0 V to VCC –1.0 +1.0 µA I/O leakage current ILO VI/O = 0 V to VCC, /CS = VIH or –1.0 +1.0 µA mA /WE = VIL or /OE = VIH ★ Operating supply current ICCA1 /CS = VIL, Cycle time = 50 ns – 40 II/O = 0 mA, Cycle time = 55 ns – 35 Minimum cycle time Cycle time ≥ 70 ns – 30 ★ ICCA2 /CS = VIL, II/O = 0 mA, Cycle time = ∞ – 4 ★ ICCA3 /CS ≤ 0.2 V, Cycle time = 1 µs, II/O = 0 mA, – 4 – 0.6 mA µA VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V Standby supply current ISB /CS = VIH or /LB = /UB = VIH ISB1 /CS ≥ VCC – 0.2 V 0.3 4 ISB2 /LB = /UB ≥ VCC – 0.2 V, /CS ≤ 0.2 V 0.3 4 High level output voltage VOH IOH = –0.5 mA Low level output voltage VOL IOL = 1.0 mA 2.4 V 0.4 V Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of product classification. Data Sheet M14670EJ6V0DS 7 µPD442002-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2) Parameter Symbol µPD442002-BCxxX Test condition MIN. TYP. µPD442002-DDxxX MAX. MIN. TYP. Unit MAX. Input leakage current ILI VIN = 0 V to VCC –1.0 +1.0 –1.0 +1.0 µA I/O leakage current ILO VI/O = 0 V to VCC, /CS = VIH or –1.0 +1.0 –1.0 +1.0 µA mA /WE = VIL or /OE = VIH Operating supply current ICCA1 – 30 – – VCC ≤ 2.7 V – 25 – – VCC ≤ 2.2 V – – – 15 – 4 – – VCC ≤ 2.7 V – 2 – – VCC ≤ 2.2 V – – – 1 /CS ≤ 0.2 V, Cycle time = 1 µs, – 4 – – ★ II/O = 0 mA, VIL ≤ 0.2 V, VCC ≤ 2.7 V – 3 – – ★ VIH ≥ VCC – 0.2 V VCC ≤ 2.2 V – – – 3 – 0.6 – – VCC ≤ 2.7 V – 0.6 – – VCC ≤ 2.2 V – – – 0.6 0.3 4 – – VCC ≤ 2.7 V 0.25 3.5 – – VCC ≤ 2.2 V – – 0.2 3 0.3 4 – – VCC ≤ 2.7 V 0.25 3.5 – – VCC ≤ 2.2 V – – 0.2 3 ★ /CS = VIL, II/O = 0 mA, Minimum cycle time ★ ★ ICCA2 /CS = VIL, II/O = 0 mA, Cycle time = ∞ ★ ★ ★ ICCA3 Standby supply current ISB ISB1 ISB2 /CS = VIH or /LB = /UB = VIH /CS ≥ VCC – 0.2 V /LB = /UB ≥ VCC – 0.2 V, /CS ≤ 0.2 V High level output voltage Low level output voltage VOH VOL IOH = –0.5 mA 2.4 – VCC ≤ 2.7 V 1.8 – VCC ≤ 2.2 V – 1.5 IOL = 1.0 mA – VCC ≤ 2.7 V 0.4 – VCC ≤ 2.2 V – 0.4 VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of product classification. 8 Data Sheet M14670EJ6V0DS µA V 0.4 Remarks 1. VIN : Input voltage mA V µPD442002-X AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions [ µPD442002-BB55X, µPD442002-BB70X, µPD442002-BB85X ] Input Waveform (Rise and Fall Time ≤ 5 ns) 0.9 VCC VCC/2 Test points VCC/2 VCC/2 Test points VCC/2 0.1 VCC Output Waveform Output Load 1TTL + 50 pF [ µPD442002-BC70X, µPD442002-BC85X, µPD442002-BC10X ] Input Waveform (Rise and Fall Time ≤ 5 ns) 0.9 VCC VCC/2 Test points VCC/2 VCC/2 Test points VCC/2 0.1 VCC Output Waveform Output Load 1TTL + 30 pF [ µPD442002-DD85X, µPD442002-DD10X, µPD442002-DD12X ] Input Waveform (Rise and Fall Time ≤ 5 ns) 0.9 VCC VCC/2 Test points VCC/2 VCC/2 Test points VCC/2 0.1 VCC Output Waveform Output Load 1TTL + 30 pF Data Sheet M14670EJ6V0DS 9 µPD442002-X ★ Read Cycle (1/3) (BB version) Parameter µPD442002-BB55X Symbol µPD442002 µPD442002 -BB70X -BB85X VCC ≥ 3.0 V MIN. MAX. MIN. 50 MAX. 55 MIN. MAX. MIN. 70 Unit Condition MAX. Read cycle time tRC 85 ns Address access time tAA 50 55 70 85 ns /CS access time tACS 50 55 70 85 ns /OE to output valid tOE 30 30 35 40 ns /LB, /UB to output valid tBA 50 55 70 85 ns Output hold from address change tOH 10 10 10 10 ns /CS to output in low impedance tLZ 10 10 10 10 ns /OE to output in low impedance tOLZ 5 5 5 5 ns /LB, /UB to output in low impedance tBLZ 10 10 10 10 ns /CS to output in high impedance tHZ 20 20 25 30 ns /OE to output in high impedance tOHZ 20 20 25 30 ns /LB, /UB to output in high impedance tBHZ 20 20 25 30 ns Note 1 Note 2 Notes 1. The output load is 1TTL + 50 pF. 2. The output load is 1TTL + 5 pF. Read Cycle (2/3) (BC version) Parameter Symbol µPD442002 µPD442002 µPD442002 -BC70X -BC85X -BC10X MIN. MAX. 70 MIN. MAX. 85 MIN. Unit MAX. Read cycle time tRC Address access time tAA 70 85 100 ns /CS access time tACS 70 85 100 ns /OE to output valid tOE 35 40 50 ns /LB, /UB to output valid tBA 70 85 100 ns Output hold from address change tOH 10 10 10 ns /CS to output in low impedance tLZ 10 10 10 ns /OE to output in low impedance tOLZ 5 5 5 ns /LB, /UB to output in low impedance tBLZ 10 10 10 ns /CS to output in high impedance tHZ 25 30 35 ns /OE to output in high impedance tOHZ 25 30 35 ns /LB, /UB to output in high impedance tBHZ 25 30 35 ns Notes 1. The output load is 1TTL + 30 pF. 2. The output load is 1TTL + 5 pF. 10 Data Sheet M14670EJ6V0DS Condition 100 ns Note 1 Note 2 µPD442002-X Read Cycle (3/3) (DD version) Parameter Symbol µPD442002 µPD442002 µPD442002 -DD85X -DD10X -DD12X MIN. MAX. 85 MIN. MAX. 100 MIN. Unit Condition MAX. Read cycle time tRC 120 ns Address access time tAA 85 100 120 ns /CS access time tACS 85 100 120 ns /OE to output valid tOE 40 50 60 ns /LB, /UB to output valid tBA 85 100 120 ns Output hold from address change tOH 10 10 10 ns /CS to output in low impedance tLZ 10 10 10 ns /OE to output in low impedance tOLZ 5 5 5 ns /LB, /UB to output in low impedance tBLZ 10 10 10 ns /CS to output in high impedance tHZ 30 35 40 ns /OE to output in high impedance tOHZ 30 35 40 ns /LB, /UB to output in high impedance tBHZ 30 35 40 ns Note 1 Note 2 Notes 1. The output load is 1TTL + 30 pF. 2. The output load is 1TTL + 5 pF. Data Sheet M14670EJ6V0DS 11 µPD442002-X Read Cycle Timing Chart tRC Address (Input) tAA tOH /CS (Input) tHZ tACS tLZ /OE (Input) tOE tOHZ tOLZ /LB, /UB (Input) tBA tBHZ tBLZ I/O (Output) Remark 12 High impedance In read cycle, /WE should be fixed to high level. Data Sheet M14670EJ6V0DS Data out µPD442002-X ★ Write Cycle (1/3) (BB version) Parameter µPD442002-BB55X Symbol µPD442002 µPD442002 -BB70X -BB85X VCC ≥ 3.0 V MIN. MAX. MIN. MAX. MIN. MAX. MIN. Unit MAX. Write cycle time tWC 50 55 70 85 ns /CS to end of write tCW 45 50 55 70 ns /LB, /UB to end of write tBW 45 50 55 70 ns Address valid to end of write tAW 45 50 55 70 ns Address setup time tAS 0 0 0 0 ns Write pulse width tWP 40 45 50 55 ns Write recovery time tWR 0 0 0 0 ns Data valid to end of write tDW 25 25 30 35 ns Data hold time tDH 0 0 0 0 ns /WE to output in high impedance tWHZ Output active from end of write tOW 20 20 5 5 25 30 5 Condition 5 ns Note ns Note The output load is 1TTL + 5 pF. Write Cycle (2/3) (BC version) Parameter Symbol µPD442002 µPD442002 µPD442002 -BC70X -BC85X -BC10X MIN. MAX. MIN. MAX. MIN. Unit MAX. Write cycle time tWC 70 85 100 ns /CS to end of write tCW 55 70 80 ns /LB, /UB to end of write tBW 55 70 80 ns Address valid to end of write tAW 55 70 80 ns Address setup time tAS 0 0 0 ns Write pulse width tWP 50 55 60 ns Write recovery time tWR 0 0 0 ns Data valid to end of write tDW 30 35 40 ns Data hold time tDH 0 0 0 ns /WE to output in high impedance tWHZ Output active from end of write tOW 25 5 30 5 35 5 Condition ns Note ns Note The output load is 1TTL + 5 pF. Data Sheet M14670EJ6V0DS 13 µPD442002-X Write Cycle (3/3) (DD version) Parameter Symbol µPD442002 µPD442002 µPD442002 -DD85X -DD10X -DD12X MIN. MAX. MIN. MAX. MIN. Unit MAX. Write cycle time tWC 85 100 120 ns /CS to end of write tCW 70 80 100 ns /LB, /UB to end of write tBW 70 80 100 ns Address valid to end of write tAW 70 80 100 ns Address setup time tAS 0 0 0 ns Write pulse width tWP 55 60 85 ns Write recovery time tWR 0 0 0 ns Data valid to end of write tDW 35 40 60 ns Data hold time tDH 0 0 0 ns /WE to output in high impedance tWHZ Output active from end of write tOW 30 5 35 5 Note The output load is 1TTL + 5 pF. 14 Data Sheet M14670EJ6V0DS 40 5 Condition ns ns Note µPD442002-X Write Cycle Timing Chart 1 (/WE Controlled) tWC Address (Input) tCW /CS (Input) tAW tAS tWP tWR /WE (Input) tBW /LB, /UB (Input) tOW tWHZ I/O (Input / Output) Indefinite data out tDW High impedance tDH Data in High impedance Indefinite data out Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remarks 1. Write operation is done during the overlap time of a low level /CS, a low level /WE and a low level /LB (or low level /UB). 2. If /CS changes to low level at the same time or after the change of /WE to low level, the I/O pins will remain high impedance state. 3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance. Data Sheet M14670EJ6V0DS 15 µPD442002-X Write Cycle Timing Chart 2 (/CS Controlled) tWC Address (Input) tAS tCW /CS (Input) tAW tWP tWR /WE (Input) tBW /LB, /UB (Input) tDW tDH High impedance Data in I/O (Input) High impedance Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CS, a low level /WE and a low level /LB (or low level /UB). 16 Data Sheet M14670EJ6V0DS µPD442002-X Write Cycle Timing Chart 3 (/LB, /UB Controlled) tWC Address (Input) tCW /CS (Input) tAW tWP tWR /WE (Input) tAS tBW /LB, /UB (Input) tDW High impedance I/O (Input) tDH Data in High impedance Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CS, a low level /WE and a low level /LB (or low level /UB). Data Sheet M14670EJ6V0DS 17 µPD442002-X Low VCC Data Retention Characteristics (TA = –25 to +85°°C) Parameter Symbol Test Condition µPD442002 µPD442002 µPD442002 -BBxxX -BCxxX -DDxxX Unit MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. Data retention VCCDR1 /CS ≥ VCC − 0.2 V 1.0 3.6 1.0 3.6 1.0 2.2 supply voltage VCCDR2 /LB = /UB ≥ VCC − 0.2 V, 1.0 3.6 1.0 3.6 1.0 2.2 V /CS ≤ 0.2 V Data retention ICCDR1 VCC = 1.2 V, /CS ≥ VCC − 0.2 V 0.15 2 0.15 2 0.15 2 supply current ICCDR2 VCC = 1.2 V, /LB = /UB ≥ VCC − 0.2 V, 0.15 2 0.15 2 0.15 2 µA /CS ≤ 0.2 V Chip deselection tCDR 0 0 0 ns Note ns to data retention mode Operation tR tRC Note recovery time Note tRC : Read cycle time 18 Data Sheet M14670EJ6V0DS tRC Note tRC µPD442002-X Data Retention Timing Chart (1) /CS Controlled tCDR Data retention mode tR VCC Note VCC (MIN.) /CS VIH (MIN.) VCCDR (MIN.) /CS ≥ VCC – 0.2 V VIL (MAX.) GND Note BB version : 2.7 V, BC version : 2.2 V, DD version : 1.8 V Remark On the data retention mode by controlling /CS, the other pins (Address, I/O, /WE, /OE, /LB, /UB) can be in high impedance state. (2) /LB, /UB Controlled tCDR Data retention mode tR VCC VCC (MIN.) Note /LB, /UB VIH (MIN.) VCCDR (MIN.) /LB, /UB ≥ VCC – 0.2 V VIL (MAX.) GND Note BB version : 2.7 V, BC version : 2.2 V, DD version : 1.8 V Remark On the data retention mode by controlling /LB and /UB, the input level of /CS must be ≥ VCC − 0.2 V or ≤ 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state. Data Sheet M14670EJ6V0DS 19 µPD442002-X Package Drawing 48-PIN TAPE FBGA (6x8) w D S A E w S B A A2 y1 S S y e S A1 INDEX MARK φb φx M S AB B ITEM ZD A D E ZE w e A A1 A2 MILLIMETERS 8.0±0.1 6.0±0.1 0.2 0.75 0.96±0.10 0.25±0.05 0.71 b 0.35±0.05 x y 0.08 0.1 y1 0.1 ZD 1.375 ZE 1.125 P48F9-75-BC1-1 20 Data Sheet M14670EJ6V0DS µPD442002-X Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD442002-X. Types of Surface Mount Device µPD442002F9-BBxxX-BC1 : 48-pin TAPE FBGA (6x8) µPD442002F9-BCxxX-BC1 : 48-pin TAPE FBGA (6x8) µPD442002F9-DDxxX-BC1 : 48-pin TAPE FBGA (6x8) Data Sheet M14670EJ6V0DS 21 µPD442002-X [ MEMO ] 22 Data Sheet M14670EJ6V0DS µPD442002-X NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M14670EJ6V0DS 23 µPD442002-X • The information in this document is current as of July, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. 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