ETC 25LC040/SN

M 25AA040/25LC040/25C040
4K SPI™ Bus Serial EEPROM
PACKAGE TYPES
DEVICE SELECTION TABLE
Part
Number
Max Clock
Frequency
1.8-5.5V
1 MHz
Temp
Ranges
PDIP/SOIC
C,I
CS
1
25LC040
2.5-5.5V
2 MHz
C,I
SO
2
25C040
4.5-5.5V
3 MHz
C,I,E
WP
3
VSS
4
FEATURES
8
VCC
7
HOLD
6
SCK
5
SI
TSSOP
HOLD
VCC
CS
SO
1
2
3
4
25xx040
• Low power CMOS technology
- Write current: 3 mA typical
- Read current: 500 µA typical
- Standby current: 500 nA typical
• 512 x 8 bit organization
• 16 byte page
• Write cycle time: 5ms max.
• Self-timed ERASE and WRITE cycles
• Block write protection
- Protect none, 1/4, 1/2, or all of array
• Built-in write protection
- Power on/off data protection circuitry
- Write enable latch
- Write protect pin
• Sequential read
• High reliability
- Endurance: 1M cycles (guaranteed)
- Data retention: > 200 years
- ESD protection: > 4000 V
• 8-pin PDIP, SOIC, and TSSOP packages
• Temperature ranges supported:
- Commercial (C):
0°C to +70°C
- Industrial (I):
-40°C to +85°C
- Automotive (E) (25C040):
-40°C to +125°C
25xx040
25AA040
VCC
Range
8
7
6
5
SCK
SI
VSS
WP
BLOCK DIAGRAM
Status
Register
HV Generator
EEPROM
I/O Control
Logic
Memory
Control
Logic
X
Array
Dec
Page Latches
DESCRIPTION
The Microchip Technology Inc. 25AA040/25LC040/
25C040 (25xx040*) is a 4K bit serial Electrically Erasable PROM. The memory is accessed via a simple
Serial Peripheral Interface (SPI) compatible serial bus.
The bus signals required are a clock input (SCK) plus
separate data in (SI) and data out (SO) lines. Access to
the device is controlled through a chip select (CS)
input.
SI
Y Decoder
SO
CS
SCK
Sense Amp.
R/W Control
HOLD
WP
VCC
VSS
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of
chip select, allowing the host to service higher priority
interrupts. Also, write operations to the device can be
disabled via the write protect pin (WP).
*25xx040 is used in this document as a generic part number for the 25AA040/25LC040/25C040 devices.
SPI is a trademark of Motorola.
 1998 Microchip Technology Inc.
DS21204B-page 1
25AA040/25LC040/25C040
1.0
ELECTRICAL
CHARACTERISTICS
1.1
FIGURE 1-2:
AC TEST CIRCUIT
VCC
Maximum Ratings*
2.25 K
Vcc ...................................................................................7.0V
All inputs and outputs w.r.t. Vss.................. -0.6V to Vcc+1.0V
Storage temperature ....................................... -65˚C to 150˚C
Ambient temperature under bias..................... -65˚C to 125˚C
Soldering temperature of leads (10 seconds) ............. +300˚C
ESD protection on all pins.................................................4kV
SO
1.8 K
*Notice: Stresses above those listed under ‘Maximum ratings’ may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for an extended
period of time may affect device reliability
1.2
100 pF
AC Test Conditions
AC Waveform:
TABLE 1-1:
VLO = 0.2V
PIN FUNCTION TABLE
Name
Function
VH I = VCC - 0.2V
(Note 1)
VH I = 4.0V
(Note 2)
CS
Chip Select Input
SO
Serial Data Output
Input
0.5 VCC
SI
Serial Data Input
Output
0.5 VCC
SCK
Serial Clock Input
WP
Write Protect Pin
VSS
Ground
VCC
Supply Voltage
HOLD
Timing Measurement Reference Level
Note 1: For VCC ≤ 4.0V
2: For VCC > 4.0V
Hold Input
TABLE 1-3:
DC CHARACTERISTICS
All parameters apply over the
specified operating ranges
unless otherwise noted.
Parameter
High level input voltage
Low level input voltage
Commercial (C): TAMB = 0°C to +70°C
Industrial (I):
TAMB = -40°C to +85°C
Automotive (E): TAMB = -40°C to +125°C
Symbol
Min
VCC = 1.8V to 5.5V
VCC = 1.8V to 5.5V
VCC = 4.5V to 5.5V (25C040 only)
Max
Units
Test Conditions
VIH1
2.0
VCC+1
V
VCC ≥ 2.7V (Note)
VIH2
0.7 VCC
VCC+1
V
VCC< 2.7V (Note)
VIL1
-0.3
0.8
V
VCC ≥ 2.7V (Note)
VIL2
-0.3
0.3 VCC
V
VCC < 2.7V (Note)
VOL
—
0.4
V
IOL = 2.1 mA
VOL
—
0.2
V
IOL = 1.0 mA, VCC < 2.5V
VOH
VCC -0.5
—
V
IOH =-400 µA
ILI
-10
10
µA
CS = VCC, VIN = VSS TO VCC
Output leakage current
ILO
-10
10
µA
CS = VCC, VOUT = VSS TO VCC
Internal Capacitance
(all inputs and outputs)
CINT
—
7
pF
TAMB = 25˚C, CLK = 1.0 MHz,
VCC = 5.0V (Note)
ICC Read
—
—
1
500
mA
µA
VCC = 5.5V; FCLK=3.0 MHz; SO = Open
VCC = 2.5V; FCLK=2.0 MHz; SO = Open
ICC Write
—
—
5
3
mA
mA
VCC= 5.5V
VCC = 2.5V
ICCS
—
—
5
2
µA
µA
CS = Vcc = 5.5V, Inputs tied to VCC or VSS
CS = Vcc = 2.5V, Inputs tied to VCC or VSS
Low level output voltage
High level output voltage
Input leakage current
Operating Current
Standby Current
Note: This parameter is periodically sampled and not 100% tested.
DS21204B-page 2
 1998 Microchip Technology Inc.
25AA040/25LC040/25C040
TABLE 1-4:
AC CHARACTERISTICS
All parameters apply over the
specified operating ranges
unless otherwise noted.
Parameter
Commercial (C):
Industrial (I):
Automotive (E):
Tamb = 0°C to +70°C
Tamb = -40°C to +85°C
Tamb = -40°C to +125°C
VCC = 1.8V to 5.5V
VCC = 1.8V to 5.5V
VCC = 4.5V to 5.5V (25C040 only)
Symbol
Min
Max
Units
Clock Frequency
FCLK
—
—
—
3
2
1
MHz
MHz
MHz
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
Test Conditions
CS Setup Time
TCSS
100
250
500
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
CS Hold Time
TCSH
150
250
475
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
CS Disable Time
TCSD
500
—
ns
Data Setup Time
TSU
30
50
50
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
Data Hold Time
THD
50
100
100
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
(Note 1)
CLK Rise Time
TR
—
2
µs
CLK Fall Time
TF
—
2
µs
(Note 1)
Clock High Time
THI
150
250
475
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
Clock Low Time
TLO
150
250
475
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
Clock Delay Time
TCLD
50
—
ns
Clock Enable Time
TCLE
50
—
ns
TV
—
—
—
150
250
475
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
Output Valid from
Clock Low
Output Hold Time
THO
0
—
ns
(Note 1)
Output Disable Time
TDIS
—
—
—
200
250
500
ns
ns
ns
VCC = 4.5V to 5.5V (Note 1)
VCC = 2.5V to 4.5V (Note 1)
VCC = 1.8V to 2.5V (Note 1)
HOLD Setup Time
THS
100
100
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
HOLD Hold Time
THH
100
100
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
HOLD Low to Output High-Z
THZ
100
150
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V (Note 1)
VCC = 2.5V to 4.5V (Note 1)
VCC = 1.8V to 2.5V (Note 1)
HOLD High to Output Valid
THV
100
150
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
Internal Write Cycle Time
TWC
—
5
ms
—
1M
—
E/W Cycles
Endurance
Note 1:
2:
(Note 2)
This parameter is periodically sampled and not 100% tested.
This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please
consult the Total Endurance Model which can be obtained on our website.
 1998 Microchip Technology Inc.
DS21204B-page 3
25AA040/25LC040/25C040
FIGURE 1-5:
HOLD TIMING
CS
THS
THH
THS
THH
SCK
THZ
SO
n+2
n+1
n
THV
high impedance
n
n-1
TSU
n+2
SI
n+1
n
don’t care
n
n-1
HOLD
FIGURE 1-6:
SERIAL INPUT TIMING
TCSD
CS
TCLE
TCLD
TR
TCSS
TF
Mode 1,1
TCSH
SCK Mode 0,0
Tsu
THD
SI
MSB in
high impedance
SO
FIGURE 1-7:
LSB in
SERIAL OUTPUT TIMING
CS
TCSH
THI
TLO
Mode 1,1
SCK
Mode 0,0
TV
THC
SO
SI
DS21204B-page 4
MSB out
TDIS
ISB out
don’t care
 1998 Microchip Technology Inc.
25AA040/25LC040/25C040
2.0
PIN DESCRIPTIONS
2.5
2.1
Chip Select (CS)
This pin is a hardware write protect input pin. When
WP is low, all writes to the array or status register are
disabled, but any other operation functions normally.
When WP is high, all functions, including non-volatile
writes operate normally. WP going low at any time will
reset the write enable latch and inhibit programming,
except when an internal write has already begun. If an
internal write cycle has already begun, WP going low
will have no effect on the write. See Table 3-7 for Write
Protect Functionality Matrix.
A low level on this pin selects the device. A high level
deselects the device and forces it into standby mode.
However, a programming cycle which is already initiated or in progress will be completed, regardless of
the CS input signal. If CS is brought high during a program cycle, the device will go in standby mode as
soon as the programming cycle is complete. As soon
as the device is deselected, SO goes to the high
impedance state, allowing multiple parts to share the
same SPI bus. A low to high transition on CS after a
valid write sequence initiates an internal write cycle.
After power-up, a low level on CS is required prior to
any sequence being initiated.
2.2
Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses, and data. Data is
latched on the rising edge of the serial clock.
2.3
Serial Output (SO)
The SO pin is used to transfer data out of the 25xx040.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
2.4
Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 25xx040. Instructions,
addresses, or data present on the SI pin are latched
on the rising edge of the clock input, while data on the
SO pin is updated after the falling edge of the clock
input.
 1998 Microchip Technology Inc.
2.6
Write Protect (WP)
Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25xx040 while in the middle of a serial sequence without having to re-transmit the entire sequence over at a
later time. It must be held high any time this function is
not being used. Once the device is selected and a
serial sequence is underway, the HOLD pin may be
pulled low to pause further serial communication without resetting the serial sequence. The HOLD pin must
be brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high to
low transition. The 25xx040 must remain selected during this sequence. The SI, SCK, and SO pins are in a
high impedance state during the time the part is
paused and transitions on these pins will be ignored.
To resume serial communication, HOLD must be
brought high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
DS21204B-page 5
25AA040/25LC040/25C040
3.0
FUNCTIONAL DESCRIPTION
3.3
3.1
PRINCIPLES OF OPERATION
Prior to any attempt to write data to the 25xx040, the
write enable latch must be set by issuing the WREN
instruction (Figure 3-5). This is done by setting CS low
and then clocking out the proper instruction into the
25xx040. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write
enable latch. If the write operation is initiated immediately after the WREN instruction without CS being
brought high, the data will not be written to the array
because the write enable latch will not have been
properly set.
The 25xx040 is a 512 byte Serial EEPROM designed
to interface directly with the Serial Peripheral Interface
(SPI) port of many of today’s popular microcontroller
families, including Microchip’s PIC16C6X/7X microcontrollers. It may also interface with microcontrollers
that do not have a built-in SPI port by using discrete
I/O lines programmed properly with the software.
The 25xx040 contains an 8-bit instruction register. The
part is accessed via the SI pin, with data being clocked
in on the rising edge of SCK. The CS pin must be low
and the HOLD pin must be high for the entire operation. The WP pin must be held high to allow writing to
the memory array.
Table 3-1 contains a list of the possible instruction
bytes and format for device operation. The most significant address bit (A8) is located in the instruction byte.
All instructions, addresses, and data are transferred
MSB first, LSB last.
Data is sampled on the first rising edge of SCK after
CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25xx040 in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
3.2
Read Sequence
The part is selected by pulling CS low. The 8-bit read
instruction with the A8 address bit is transmitted to the
25xx040 followed by the lower 8-bit address (A7
through A0). After the correct read instruction and
address are sent, the data stored in the memory at the
selected address is shifted out on the SO pin. The data
stored in the memory at the next address can be read
sequentially by continuing to provide clock pulses. The
internal address pointer is automatically incremented
to the next higher address after each byte of data is
shifted out. When the highest address is reached
(01FFh), the address counter rolls over to address
0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the
CS pin (Figure 3-2).
TABLE 3-1:
Write Sequence
Once the write enable latch is set, the user may proceed by setting the CS low, issuing a write instruction,
followed by the address, and then the data to be written. Keep in mind that the most significant address bit
(A8) is included in the instruction byte. Up to 16 bytes
of data can be sent to the 25xx040 before a write cycle
is necessary. The only restriction is that all of the bytes
must reside in the same page. A page address begins
with XXXX 0000 and ends with XXXX 1111. If the
internal address counter reaches XXXX 1111 and the
clock continues, the counter will roll back to the first
address of the page and overwrite any data in the
page that may have been written.
For the data to be actually written to the array, the CS
must be brought high after the least significant bit (D0)
of the nth data byte has been clocked in. If CS is
brought high at any other time, the write operation will
not be completed. Refer to Figure 3-3 and Figure 3-4
for more detailed illustrations on the byte write
sequence and the page write sequence respectively.
While the write is in progress, the status register may
be read to check the status of the WIP, WEL, BP1, and
BP0 bits (Figure 3-8). A read attempt of a memory
array location will not be possible during a write cycle.
When the write cycle is completed, the write enable
latch is reset.
INSTRUCTION SET
Instruction Name
Instruction Format
READ
0000 A8011
Read data from memory array beginning at selected address
WRITE
0000 A8010
Write data to memory array beginning at selected address
WRDI
0000 0100
Reset the write enable latch (disable write operations)
WREN
0000 0110
Set the write enable latch (enable write operations)
RDSR
0000 0101
Read status register
WRSR
0000 0001
Write status register
Note: A8 is the
9th
DS21204B-page 6
Description
address bit necessary to fully address 512 bytes.
 1998 Microchip Technology Inc.
25AA040/25LC040/25C040
FIGURE 3-2:
READ SEQUENCE
CS
0
1
2
3
4
5
6
7
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
8
SCK
instruction
0
SI
0
0
0
lower address byte
A8
0
1
A7
1
6
5
3
4
2
1
A0
don’t care
data out
high impedance
7
SO
FIGURE 3-3:
6
5
4
3
2
1
0
BYTE WRITE SEQUENCE
CS
twc
0
1
2
3
4
5
6
7
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
8
SCK
instruction
SI
0
0
0
0
A8
data byte
lower address byte
0
1
0
A7
6
5
3
4
2
A0 7
1
6
5
4
3
2
1
0
high impedance
SO
FIGURE 3-4:
PAGE WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 13 14 15 16 17 18 19 20 21 22 23 24
SCK
instruction
SI
0
0
0
0 A8
lower address byte
0
1
0
A7 6
5
3
4
2
data byte 1
1
0
7
6
5
4
7
6
3
2
1
0
CS
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
SCK
data byte 2
SI
7
6
5
4
 1998 Microchip Technology Inc.
3
data byte 3
2
1
0
7
6
5
4
3
data byte n (16 max)
2
1
0
5
4
3
2
1
0
DS21204B-page 7
25AA040/25LC040/25C040
3.4
Write Enable (WREN) and Write
Disable (WRDI)
The following is a list of conditions under which the
write enable latch will be reset:
•
•
•
•
•
The 25xx040 contains a write enable latch.
See
Table 3-10 for the Write Protect Functionality Matrix.
This latch must be set before any write operation will
be completed internally. The WREN instruction will set
the latch, and the WRDI will reset the latch.
FIGURE 3-5:
Power-up
WRDI instruction successfully executed
WRSR instruction successfully executed
WRITE instruction successfully executed
WP line is low
WRITE ENABLE SEQUENCE
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
1
0
high impedance
SO
FIGURE 3-6:
WRITE DISABLE SEQUENCE
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
10
0
high impedance
SO
DS21204B-page 8
 1998 Microchip Technology Inc.
25AA040/25LC040/25C040
3.5
Read Status Register (RDSR)
3.6
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is formatted as follows:
7
X
6
X
5
X
4
X
3
BP1
2
BP0
1
WEL
Write Status Register(WRSR)
The WRSR instruction allows the user to select one of
four levels of protection for the array by writing to the
appropriate bits in the status register. The array is
divided up into four segments. The user has the ability
to write protect none, one, two, or all four of the segments of the array. The partitioning is controlled as
illustrated in Table 3-7.
0
WIP
The Write-In-Process (WIP) bit indicates whether the
25xx040 is busy with a write operation. When set to a
‘1’ a write is in progress, when set to a ‘0’ no write is in
progress. This bit is read only.
See Figure 3-9 for WRSR timing sequence
TABLE 3-7:
The Write Enable Latch (WEL) bit indicates the status of the write enable latch. When set to a ‘1’ the latch
allows writes to the array, when set to a ‘0’ the latch
prohibits writes to the array. The state of this bit can
always be updated via the WREN or WRDI commands
regardless of the state of write protection on the status
register. This bit is read only.
ARRAY PROTECTION
Array Addresses
Write Protected
BP1
BP0
0
0
none
0
1
upper 1/4
(0180h - 01FFh)
1
0
upper 1/2
(0100h - 01FFh)
1
1
all
(0000h - 01FFh)
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write protected. These bits
are set by the user issuing the WRSR instruction.
These bits are non-volatile.
See Figure 3-8 for RDSR timing sequence
FIGURE 3-8:
READ STATUS REGISTER SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
instruction
SI
0
0
0
0
0
1
0
1
data from status register
high impedance
7
SO
FIGURE 3-9:
6
5
4
3
2
1
0
WRITE STATUS REGISTER SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
instruction
SI
0
0
0
0
0
data to status register
0
0
1
7
6
5
4
3
2
high impedance
SO
 1998 Microchip Technology Inc.
DS21204B-page 9
25AA040/25LC040/25C040
3.7
Data Protection
3.8
The following protection has been implemented to prevent inadvertent writes to the array:
• The write enable latch is reset on power-up.
• A write enable instruction must be issued to set
the write enable latch.
• After a byte write, page write, or status register
write, the write enable latch is reset.
• CS must be set high after the proper number of
clock cycles to start an internal write cycle.
• Access to the array during an internal write cycle
is ignored and programming is continued.
• The write enable latch is reset when the WP pin is
low.
TABLE 3-10:
Power On State
The 25xx040 powers on in the following state:
• The device is in low power standby mode
(CS = 1).
• The write enable latch is reset.
• SO is in high impedance state.
• A low level on CS is required to enter active state.
.
WRITE PROTECT FUNCTIONALITY MATRIX
WP
WEL
Protected Blocks
Unprotected Blocks
Status Register
Low
X
Protected
Protected
Protected
High
0
Protected
Protected
Protected
High
1
Protected
Writable
Writable
DS21204B-page 10
 1998 Microchip Technology Inc.
25AA040/25LC040/25C040
25AA040/25LC040/25C040 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
25xx040
—
/P
Package:
Temperature
Range:
P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
ST = TSSOP, 8-lead
Blank = 0°C to +70°C
I = –40°C to +85°C
E = –40°C to +125°C
25AA040
25AA040T
25AA040X
25AA040XT
Devices:
25LC040
25LC040T
25LC040X
25LC040XT
25C040
25C040T
25C040X
25C040XT
4096 bit 1.8V SPI Serial EEPROM
4096 bit 1.8V SPI Serial EEPROM Tape and Reel
4096 bit 1.8V SPI Serial EEPROM
in alternate pinout (ST only)
4096 bit 1.8V SPI Serial EEPROM
in alternate pinout Tape and Reel (ST only)
4096 bit 2.5V SPI Serial EEPROM
4096 bit 2.5V SPI Serial EEPROM Tape and Reel
4096 bit 2.5V SPI Serial EEPROM
in alternate pinout (ST only)
4096 bit 2.5V SPI Serial EEPROM
in alternate pinout Tape and Reel (ST only)
4096 bit 5.0V SPI Serial EEPROM
4096 bit 5.0V SPI Serial EEPROM Tape and Reel
4096 bit 5.0V SPI Serial EEPROM
in alternate pinout (ST only)
4096 bit 5.0V SPI Serial EEPROM
in alternate pinout Tape and Reel (ST only)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip Worldwide Web Site (www.microchip.com)
 1998 Microchip Technology Inc.
DS21204B-page 11
WORLDWIDE SALES AND SERVICE
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ASIA/PACIFIC (continued)
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11/15/99
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
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 1999 Microchip Technology Inc.