January 2006 DS90C241/DS90C124 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description The DS90C241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. The DS90C241/124 incorporates LVDS signaling on the high-speed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range EMI is further reduced. In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects. Features n 5 MHz–35 MHz clock embedded and DC-Balancing 1:24 and 24:1 data transmissions n User defined pre-emphasis driving ability through external resistor on LVDS outputs and capable to drive up to 10 meters shielded twisted-pair cable n User selectable clock edge for parallel data on both TX and RX n Supports AC-coupling interface n Individual power-down controls for both TX and RX n Embedded clock CDR (clock and data recovery) on RX and no external source of reference clock needed n All codes RDL (random data lock) to support hot-pluggable applications n LOCK output flag to ensure data integrity at RX side n Balanced TSETUP/THOLD between RCLK and RDATA on RX side n PTO (progressive turn-on) LVTTL O/P to minimize the SSO effects n All LVTTL inputs and control pins have internal pulldown except PRE n On-chip filters for PLLs on TX and RX n 48 pin TQFP package for both TX and RX n Pure CMOS .35 µm process n Power supply range 3.3V ± 10% n Temperature range –40˚C to +105˚C n 8 kV HBM ESD structure Block Diagram 20171901 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2006 National Semiconductor Corporation DS201719 www.national.com DS90C241/DS90C124 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer PRELIMINARY DS90C241/DS90C124 Absolute Maximum Ratings (Note 1) θJC DS90C124 If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) 21.0˚C/W θJA 45.4 (4L*); 75.0 (2L*)˚C/W θJC 21.1˚C/W −0.3V to +4V LVCMOS/LVTTL Input Voltage *JEDEC −0.3V to (VCC +0.3V) LVCMOS/LVTTL Output Voltage > 8 kV ESD Rating (HBM) ESD Rating (ISO10605) −0.3V to (VCC +0.3V) LVDS Receiver Input Voltage −0.3V to 3.9V LVDS Driver Output Voltage −0.3V to 3.9V LVDS Output Short Circuit Duration +150˚C Storage Temperature −65˚C to +150˚C Lead Temperature (Soldering, 4 seconds) Air Discharge (DOUT+, DOUT-) to GND Recommended Operating Conditions +260˚C Maximum Package Power Dissipation Capacity Package De-rating: 48L TQFP ± 10 kV ± 30 kV Contact Discharge (DOUT+, DOUT-) to GND 10 ms Junction Temperature DS90C241 meets ISO 10605 Min Nom Max Units Supply Voltage (VCC) 3.0 3.3 3.6 V Operating Free Air Temperature (TA) −40 +25 +105 ˚C 35 MHz ± 100 mVP-P Clock Rate 1/θJA ˚CW above +25˚C 5 Supply Noise DS90C241 θJA 45.8 (4L*); 75.4 (2L*) ˚C/W Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units VCC V 0.8 V LVCMOS/LVTTL DC SPECIFICATIONS VIH High Level Voltage VIL Low Level Input Voltage VCL Input Clamp Voltage ICL = −18 mA IIN Input Current VIN = 0V or 3.6V Tx: DIN[0:23], TCLK, DEN, TRFB, DCAOFF, DCBOFF, VODSEL Rx: RRFB, REN Tx: TPWDNB Rx: RPWDNB VOH High Level Output Voltage IOH = −2 mA VOL Low Level Output Voltage IOL = +2 mA IOS Output Short Circuit Current VOUT = 0V IOZ TRI-STATE ® RPWRDN = 0.8V, VOUT = 0V or VCC ROUT[0:23], RCLK, LOCK VCM = +1.2V RIN+, RIN− Output Current ROUT[0:23], RCLK, LOCK 2.0 GND −0.7 −1.2 V −10 ±2 +10 µA −20 ±5 +20 µA 2.3 3.0 VCC V GND 0.33 0.5 V −110 mA +15 µA +100 mV −15 ± 0.4 LVDS DC SPECIFICATIONS VTH Differential Threshold High Voltage VTL Differential Threshold Low Voltage IIN Input Current www.national.com −100 mV VIN = 2.4V, VCC = 3.6V or 0V ± 100 µA VIN = 0V, VCC = 3.6V or 0V ± 100 µA 2 (Continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units LVDS DC SPECIFICATIONS VOD RL = 100Ω, w/o pre-emphasis Output Differential Voltage (DOUT+)–(DOUT−) (Figure 16) VODSEL = L (VODSEL = H) ∆VOD Output Differential Voltage Unbalance VOS Offset Voltage RL = 100Ω, w/o pre-emphasis ∆VOS Offset Voltage Unbalance RL = 100Ω, w/o pre-emphasis IOS Output Short Circuit Current DOUT = 0V, DIN = H, TPWRDND = 2.4V IOZ TRI-STATE Output Current TPWRDND = 0.8V, DOUT = 0V or VDD DOUT+, DOUT− 250 400 600 (500) (800) (1200) RL = 100Ω, w/o pre-emphasis mV 10 50 1.2 1.25 V 10 50 mV −35 −50 −70 mA −10 ±1 10 µA 1.05 mV SER/DES SUPPLY CURRENT (DVDD*, PVDD* and AVDD* pins) *Digital, PLL, and Analog VDDs ICCT Serializer (Tx) Total Supply Current (includes load current) Serializer (Tx) Total Supply Current (includes load current) RL = 100Ω Pre-emphasis = OFF Checker-board pattern VODSEL=L (Figure 1) f = 35 MHz RL = 100Ω RPRE = 6 kΩ Checker-board pattern VODSEL=L (Figure 1) f = 35 MHz RL = 100Ω RPRE = OFF Random pattern VODSEL=L f = 35 MHz RL = 100Ω RPRE = 6 kΩ Random pattern VODSEL=L f = 35 MHz ICCTZ Serializer (Tx) Supply Current Power-down TPWRDNB = 0.8V ICCR Deserializer (Rx) Total Supply Current (includes load current) CL = 8 pF Checker-board pattern LVTTL Output (Figure 2) f = 35 MHz Deserializer (Rx) Total Supply Current (includes load current) CL = 8 pF Random pattern LVTTL Output f = 35 MHz Deserializer (Rx) Supply Current Power-down RPWRDND = 0.8V ICCRZ 105 mA 120 mA 65 mA 80 mA 200 500 µA 180 mA 110 mA 500 750 µA Max Units Serializer Timing Requirements for TCLK Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Min Typ tTCP Transmit Clock Period Parameter Conditions 28.6 T 200 ns tTCIH Transmit Clock High Time 0.4T 0.5T 0.6T ns tTCIL Transmit Clock Low Time 0.4T 0.5T 0.6T ns tCLKT TCLK Input Transition Time 3 6 ns tJIT TCLK Input Jitter ± 200 ns (Note 9) 3 www.national.com DS90C241/DS90C124 Electrical Characteristics DS90C241/DS90C124 Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions tLLHT LVDS Low-to-High Transition Time tLHLT LVDS High-to-Low Transition Time tDIS DIN (0:23) Setup to TCLK tDIH DIN (0:23) Hold from TCLK RL = 100Ω, CL = 10 pF to GND (Note 8) tHZD DOUT ± HIGH to TRI-STATE Delay tLZD DOUT ± LOW to TRI-STATE Delay tZHD DOUT ± TRI-STATE to HIGH Delay tZLD DOUT ± TRI-STATE to LOW Delay tPLD tSD Min Typ RL = 100Ω, CL = 10 pF to GND VODSEL = L (Figure 3) Max Units 0.6 ns 0.6 ns 5 ns 5 ns RL = 100Ω, CL = 10 pF to GND (Note 4) (Figure 7) 5 ns 5 ns 5 ns 5 ns Serializer PLL Lock Time (Figure 8) RL = 100Ω 10 ms Serializer Delay (Figure 9) RL = 100Ω VODSEL = L, TRFB = H 3.5T + 2.85 ns RL = 100Ω VODSEL = L, TRFB = L 3.5T + 2.85 ns Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter tRCP Receiver out Clock Period (Note 8) tRDC RCLK Duty Cycle tCLH CMOS/TTL Low-to-High Transition Time tCHL CMOS/TTL High-to-Low Transition Time tROS ROUT (0:7) Setup Data to RCLK (Group 1) (Figure 11) tROH tROS tROH tROS tROH Pin/Freq. RCLK RCLK CL = 8 pF (lumped load) (Figure 4) ROUT [0:23], LOCK, RCLK ROUT (8:15) Setup Data to RCLK (Group 2) (Figure 11) ROUT [8:15], LOCK ROUT (9:15) Hold Data to RCLK (Group 2) (Figure 11) ROUT (16:23) Setup Data to RCLK (Group 3) (Figure 11) HIGH to TRI-STATE Delay LOW to TRI-STATE Delay tZHR tZLR Typ 28.6 45 (Figure 12) ROUT [0:23], RCLK, LOCK Max Units 200 ns 50 55 % 2.5 3.5 ns 2.5 3.5 ns (29/56)*tRCP (2/5)* tRCP ns (27/56)*tRCP (2/5)* tRCP ns 0.5*tRCP (2/5)* tRCP ns 0.5*tRCP (2/5)* tRCP ns (27/56)*tRCP (2/5)* tRCP ns (29/56)*tRCP (2/5)* tRCP ns ROUT [16:23] ROUT (16:23) Hold Data to RCLK (Group 3) (Figure 11) tLZR Min ROUT [0:7] ROUT (0:7) Hold Data to RCLK (Group 1) (Figure 11) tHZR www.national.com Conditions tRCP = tTCP 3 10 ns 3 10 ns TRI-STATE to HIGH Delay 3 10 ns TRI-STATE to LOW Delay 3 10 ns 4 (Continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol tDD tDRDL Parameter Conditions Pin/Freq. Deserializer Delay (Figure 10) Min Typ Max Units RCLK [4+(3/56)]T+ 5.9 5 MHz 817 825 ns 35 MHz 122 125 ns 5 MHz 5 12 ms 35 MHz 5 10 ms 0.25 UI 0.25 UI Deserializer PLL Lock Time from Powerdown (Notes 7, 8) RxIN_TOL_L Receiver INput TOLerance Left, (Figure 15) (Notes 6, 10) 5 MHz–35 MHz RxIN_TOL_R Receiver INput TOLerance Right, (Figure 15) (Notes 6, 10) 5 MHz–35 MHz ns Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Typical values are given for VCC = 3.3V and TA = +25˚C. Note 3: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ∆VOD, VTH and VTL which are differential voltages. Note 4: When the Serializer output is tri-stated, the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer. Note 5: tDRDL is the time required by the deserializer to obtain lock when exiting powerdown mode. tDRDL is specified with an external synchronization pattern. Note 6: RxIN_TOL is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It is a measurement in reference with the ideal bit position, please see National’s AN-1217 for detail. Note 7: The Deserializer PLL lock time may vary depending on input data patterns and the number of transitions within the pattern. Note 8: Guaranteed by Design (GBD) using statistical analysis. Note 9: Total Interconnect Jitter Budget (tJI) specifies the allowable jitter added by the interconnect assuming both transmitter and receiver are Auto SerDes circuits. Note 10: UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency. Note 11: Figures 1, 2, 9, 10, 13 show a falling edge data strobe (TCLK IN/RCLK OUT). Note 12: Figures 6, 11 show a rising edge data strobe (TCLK IN/RCLK OUT). 5 www.national.com DS90C241/DS90C124 Deserializer Switching Characteristics DS90C241/DS90C124 AC Timing Diagrams and Test Circuits 20171902 FIGURE 1. Serializer Input Checker-board Pattern 20171903 FIGURE 2. Deserializer Output Checker-board Pattern 20171904 FIGURE 3. Serializer LVDS Output Load and Transition Times 20171905 FIGURE 4. Deserializer LVCMOS/LVTTL Output Load and Transition Times www.national.com 6 DS90C241/DS90C124 AC Timing Diagrams and Test Circuits (Continued) 20171906 FIGURE 5. Serializer Input Clock Transition Times 20171907 FIGURE 6. Serializer Setup/Hold Times 7 www.national.com DS90C241/DS90C124 AC Timing Diagrams and Test Circuits (Continued) 20171908 FIGURE 7. Serializer TRI-STATE Test Circuit and Delay 20171909 FIGURE 8. Serializer PLL Lock Time, and TPWDNB TRI-STATE Delays www.national.com 8 DS90C241/DS90C124 AC Timing Diagrams and Test Circuits (Continued) 20171910 FIGURE 9. Serializer Delay 20171911 FIGURE 10. Deserializer Delay 9 www.national.com DS90C241/DS90C124 AC Timing Diagrams and Test Circuits (Continued) 20171912 FIGURE 11. Deserializer Setup and Hold Times 20171913 Note: CL includes instrumentation and fixture capacitance within 6 cm of ROUT[23:0] FIGURE 12. Deserializer TRI-STATE Test Circuit and Timing www.national.com 10 DS90C241/DS90C124 AC Timing Diagrams and Test Circuits (Continued) 20171914 FIGURE 13. Deserializer PLL Lock Times and RPWDNB TRI-STATE Delay 20171915 FIGURE 14. Transmitter Output Eye Opening 20171916 FIGURE 15. Receiver Input Tolerance (RxIN_TOL) and Sampling Window 11 www.national.com DS90C241/DS90C124 AC Timing Diagrams and Test Circuits (Continued) 20171917 VOD = (DOUT+) – (DOUT -) Differential output signal is shown as (DOUT+) – (DOUT -), device in Data Transfer mode. FIGURE 16. Serializer VOD Diagram 20171918 FIGURE 17. AC Coupled Application www.national.com 12 DS90C241/DS90C124 Pin Descriptions Pin # Pin Name I/O Description DS90C241 SERIALIZER PIN DESCRIPTIONS 22 VDDDR VDD Analog Voltage Supply, LVDS O/P Power 21 VSSDR GND Analog Ground, LVDS O/P Ground 16 VDDPT0 VDD Analog Voltage supply, VCO Power 17 VSSPT0 GND Analog ground, VCO Ground 14 VDDPT1 VDD Analog Voltage supply, PLL Power 15 VSSPT1 GND Analog Ground, PLL Ground 30 VDDT VDD Digital Voltage supply, Tx serializer Power 31 VSST GND Digital Ground, Tx serializer Ground 7 VDDL VDD Digital Voltage supply, Tx Logic Power 6 VSSL GND Digital Ground, Tx Logic Ground 42 VDDIT VDD Digital Voltage supply, Tx Input Power 43 VSSIT GND Digital Ground, Tx Input Ground 24 VSSESD GND ESD Ground 4-1, 48-44, 41-32, 29-25 DIN[23:0] CMOS_I Transmitter Data INputs 10 TCLK CMOS_I Transmitter reference CLocK. Used to strobe data at the DIN inputs and to drive the transmitter PLL 9 TPWDNB CMOS_I Transmitter PoWer DowN Bar (ACTIVE L). TPWDNB = L; Disabled, DOUT (+/-) are TRI-STATED stand-by mode, PLL is shutdown TPWDNB = H; Enabled 18 DEN CMOS_I Data ENable (ACTIVE H) DEN = L; Disabled, DOUT (+/-) are TRI-STATED, PLL still operational DEN = H; Enabled 13 RESRVD CMOS_I RESERVED - tie Low 23 PRE CMOS_I PRE-emphasis select pin. PRE = (RPRE ≥ 3 kΩ); Imax = (1.2/R*20), Rmin = 3 kΩ PRE = H or floating; pre-emphasis off 11 TRFB CMOS_I Transmitter Rising/Falling Bar Clock Edge Select (H = rising edge L = falling edge) 12 VODSEL CMOS_I VOD level SELect VODSEL = L; IOD ≈ 3.5 mA, (default). e.g. 3.5 mA*100Ω≈350 mV VODSEL = H; IOD ≈ 7.0 mA, VOD doubles approximately. e.g. 7 mA*100Ω ≈ 700 mV 5 DCAOFF CMOS_I RESERVED — tie Low 8 DCBOFF CMOS_I RESERVED — tie Low 20 DOUT+ LVDS_O Transmitter LVDS true (+) OUTput 19 DOUT− LVDS_O Transmitter LVDS inverted (-) OUTput DS90C124 DESERIALIZER PIN DESCRIPTIONS 39 VDDIR VDD Analog LVDS Voltage supply, Power 40 VSSIR GND Analog LVDS Ground 47 VDDPR0 VDD Analog Voltage supply, PLL Power 46 VSSPR0 GND Analog Ground, PLL Ground 45 VDDPR1 VDD Analog Voltage supply, PLL VCO Power 44 VSSPR1 GND Analog Ground, PLL VCO Ground 37 VDDR1 VDD Digital Voltage supply, Logic Power 38 VSSR1 GND Digital Ground, Logic Ground 36 VDDR0 VDD Digital Voltage supply, Logic Power 35 VSSR0 GND Digital Ground, Logic Ground 30 VDDOR1 VDD Digital Voltage supply, LVTTL O/P Power 13 www.national.com DS90C241/DS90C124 Pin Descriptions Pin # Pin Name (Continued) I/O Description DS90C124 DESERIALIZER PIN DESCRIPTIONS 29 VSSOR1 GND Digital Ground, LVTTL O/P Ground 20 VDDOR2 VDD Digital Voltage supply, LVTTL O/P Power 19 VSSOR2 GND Digital Ground, LVTTL O/P Ground 7 VDDOR3 VDD Digital Voltage supply, LVTTL O/P Power 8 VSSOR3 GND Digital Ground, LVTTL O/P Ground 41 RIN+ LVDS_I Receiver LVDS true (+) INput 42 RIN− LVDS_I Receiver LVDS inverted (−) INput 2 RESRVD CMOS_I RESERVED - tie Low 43 RRFB CMOS_I Receiver Rising Falling Bar clock Edge Select RRFB = H; ROUT LVTTL O/P clocked on Rising CLK RRFB = L; ROUT LVTTL O/P clocked on Falling CLK 48 REN CMOS_I Receiver ENable, (ACTIVE H) REN = L; Disabled, ROUT[23-0] and RCLK TRI-STATED, PLL still operational REN = H; Enabled 1 RPWDNB CMOS_I Receiver PoWer DowN Bar (ACTIVE L) RPWDNB = L; Disabled, ROUT[23-0], RCLK, and LOCK are TRI-STATED in stand-by mode, PLL is shutdown RPWDNB = H; Enabled 17 LOCK CMOS_O LOCK indicates the status of the receiver PLL LOCK = L; receiver PLL is unlocked, ROUT[23-0] and RCLK are TRI-STATED LOCK = H; receiver PLL is locked 25-28, 31-34 ROUT[7:0] CMOS_O Receiver Outputs – Group 1 13-16, 21-24 ROUT[15:8] CMOS_O Receiver Outputs – Group 2 3-6, 9-12 ROUT[23:16] CMOS_O Receiver Outputs – Group 3 18 RCLK CMOS_O Recovered CLocK. Parallel data rate clock recovered from the embedded clock. www.national.com 14 DS90C241/DS90C124 Pin Diagrams Serializer - DS90C241 20171919 15 www.national.com DS90C241/DS90C124 Pin Diagrams (Continued) Deserializer - DS90C124 20171920 www.national.com 16 inches (millimeters) unless otherwise noted Dimensions show in millimeters only Order Number DS90C241IVS, DS90C124IVS NS Package Number IVS48 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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