ETC 74ACT125SJX

Revised November 1999
74AC125 • 74ACT125
Quad Buffer with 3-STATE Outputs
General Description
Features
The AC/ACT125 contains four independent non-inverting
buffers with 3-STATE outputs.
■ Outputs source/sink 24 mA
■ ICC reduced by 50%
■ ACT125 has TTL-compatible outputs
Ordering Code:
Order Number
Package Number
Package Description
74AC125SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC125SJ
74AC125MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC125PC
N14A
74ACT125SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
74ACT125SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT125MTC
74ACT125PC
14-Lead Plastic Dual-in-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
N14A
14-Lead Plastic Dual-in-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Logic Symbol
IEEE/IEC
Function Table
Pin Descriptions
Pin Names
Inputs
Description
An, Bn
Inputs
On
Outputs
Output
An
Bn
L
L
L
L
H
H
H
X
Z
On
H = HIGH Voltage Level
L = LOW Voltage Level
Z = HIGH Impedance
X = Immaterial
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS010692
www.fairchildsemi.com
74AC125 • 74ACT125 Quad Buffer with 3-STATE Outputs
March 1990
74AC125 • 74ACT125
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
−0.5V to +7.0V
Supply Voltage (VCC)
DC Input Diode Current (IK)
VI = −0.5V
−20 mA
VI = VCC + 0.5V
+20 mA
Supply Voltage (VCC)
−0.5V to VCC + 0.5V
DC Input Voltage (VI)
VO = VCC + 0.5V
+20 mA
AC Devices
VIN from 30% to 70% of VCC
VCC @ 3.3V, 4.5V, 5.5V
±50 mA
ACT Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
±50 mA
−65°C to +150°C
Junction Temperature (TJ)
PDIP
125 mV/ns
Minimum Input Edge Rate (∆V/∆t)
DC VCC or Ground Current
Storage Temperature (TSTG)
0V to VCC
−40°C to +85°C
Minimum Input Edge Rate (∆V/∆t)
DC Output Source
per Output Pin (ICC or IGND)
0V to VCC
Operating Temperature (TA)
−0.5V to VCC + 0.5V
or Sink Current (IO)
4.5V to 5.5V
Output Voltage (VO)
−20 mA
DC Output Voltage (VO)
2.0V to 6.0V
ACT
Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
AC
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
140°C
DC Electrical Characteristics for AC
Symbol
VIH
VIL
VOH
Parameter
VCC
TA = +25°C
TA = −40°C to +85°C
(V)
Typ
Guaranteed Limits
Minimum HIGH Level
3.0
1.5
Input Voltage
4.5
2.25
3.15
3.15
5.5
2.75
3.85
3.85
2.1
Units
Maximum LOW Level
3.0
1.5
0.9
0.9
Input Voltage
4.5
2.25
1.35
1.35
5.5
2.75
1.65
1.65
Minimum HIGH Level
3.0
2.99
2.9
2.9
Output Voltage
4.5
4.49
4.4
4.4
5.5
5.49
5.4
5.4
3.0
2.56
2.46
4.5
3.86
3.76
5.5
4.86
4.76
Conditions
VOUT = 0.1V
2.1
V
or VCC − 0.1V
VOUT = 0.1V
V
or VCC − 0.1V
V
IOUT = −50 µA
VIN = VIL or VIH
VOL
IOH = −12 mA
V
IOH = −24 mA
IOH = −24 mA (Note 2)
Maximum LOW Level
3.0
0.002
0.1
0.1
Output Voltage
4.5
0.001
0.1
0.1
5.5
0.001
0.1
0.1
3.0
0.36
0.44
4.5
0.36
0.44
5.5
0.36
0.44
5.5
± 0.1
± 1.0
µA
5.5
± 0.25
± 2.5
µA
V
IOUT = 50 µA
VIN = VIL or VIH
IIN (Note 4)
Maximum Input Leakage Current
IOZ
Maximum 3-STATE Current
IOL = 12 mA
V
IOL =24 mA
IOL = 24 mA (Note 2)
VI = VCC, GND
VI (OE) = VIL, VIH
VI = VCC, VGND
VO = VCC, GND
IOLD
Minimum Dynamic
5.5
75
mA
VOLD = 1.65V Max
IOHD
Output Current (Note 3)
5.5
−75
mA
VOHD = 3.85V Min
ICC (Note 4) Maximum Quiescent Supply Current
5.5
40.0
µA
VIN = VCC or GND
4.0
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: Note: IIN and [email protected] 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
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2
Symbol
VIH
VIL
VOH
Parameter
Minimum HIGH Level
TA = +25°C
VCC
(V)
Typ
4.5
1.5
TA = −40°C to +85°C
Guaranteed Limits
2.0
2.0
Input Voltage
5.5
1.5
2.0
2.0
Maximum LOW Level
4.5
1.5
0.8
0.8
Input Voltage
5.5
1.5
0.8
0.8
Minimum HIGH Level
4.5
4.49
4.4
4.4
Output Voltage
5.5
5.49
5.4
5.4
4.5
3.86
3.76
5.5
4.86
4.76
Units
V
V
V
Conditions
VOUT = 0.1V
or VCC − 0.1V
VOUT = 0.1V
or VCC − 0.1V
IOUT = −50 µA
VIN = VIL or VIH
VOL
V
IOH = −24 mA
IOH = −24 mA (Note 5)
Maximum LOW Level
4.5
0.001
0.1
0.1
Output Voltage
5.5
0.001
0.1
0.1
4.5
0.36
0.44
5.5
0.36
0.44
5.5
±0.1
±1.0
µA
5.5
±0.5
±5.0
µA
1.5
mA
VI = VCC − 2.1V (Note 7)
VOLD = 1.65V Max
V
IOUT = 50 µA
VIN = VIL or VIH
IIN
Maximum Input
Leakage Current
IOZ
Maximum 3-STATE
Current
ICCT
Maximum ICC/Input
5.5
IOLD
Minimum Dynamic
5.5
75
mA
IOHD
Output Current (Note 6)
5.5
−75
mA
ICC
Maximum Quiescent
Supply Current
0.6
V
5.5
4.0
40.0
µA
IOL = 24 mA
IOL = 24 mA (Note 5)
VI = VCC, GND
VI = VIL, VIH
VO = VCC, GND
VOHD = 3.85V Min
VIN = VCC
or GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
Note 7: May be measured per the JEDEC Alternate Method.
3
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74AC125 • 74ACT125
DC Electrical Characteristics for ACT
74AC125 • 74ACT125
AC Electrical Characteristics for AC
Symbol
tPLH
tPHL
tPZH
tPZL
Parameter
CL = 50 pF
Min
Typ
Propagation Delay
3.3
1.0
6.5
Data to Output
5.0
1.0
5.5
Propagation Delay
3.3
1.0
6.5
Data to Output
5.0
1.0
5.0
Output Enable Time
3.3
1.0
6.0
5.0
1.0
5.0
3.3
1.0
5.0
1.0
3.3
5.0
Output Disable Time
tPLZ
TA = +25°C
(V)
(Note 8)
Output Enable Time
tPHZ
VCC
Output Disable Time
TA = −40°C to +85°C
CL = 50 pF
Max
Min
Max
9.0
1.0
10.0
7.0
1.0
7.5
9.0
1.0
10.0
7.0
1.0
7.5
10.5
1.0
11.0
7.0
1.0
8.0
7.5
10.0
1.0
11.0
5.5
8.0
1.0
8.5
1.0
7.5
10.0
1.0
10.5
1.0
6.5
9.0
1.0
9.5
3.3
1.0
7.5
10.5
1.0
11.5
5.0
1.0
6.5
9.0
1.0
9.5
Units
ns
ns
ns
ns
ns
ns
Note 8: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Electrical Characteristics for ACT
Symbol
tPLH
Parameter
Propagation Delay
Data to Output
tPHL
Propagation Delay
Data to Output
VCC
TA = +25°C
(V)
CL = 50 pF
TA = −40°C to +85°C
CL = 50 pF
Units
(Note 9)
Min
Typ
Max
Min
Max
5.0
1.0
6.5
9.0
1.0
10.0
ns
5.0
1.0
7.0
9.0
1.0
10.0
ns
tPZH
Output Enable Time
5.0
1.0
6.0
8.5
1.0
9.5
ns
tPZL
Output Enable Time
5.0
1.0
7.0
9.5
1.0
10.5
ns
tPHZ
Output Disable Time
5.0
1.0
7.0
9.5
1.0
10.5
ns
tPLZ
Output Disable Time
5.0
1.0
7.5
10.0
1.0
10.5
ns
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
AC/ACT
Units
Conditions
Typ
CIN
Input Capacitance
4.5
pF
VCC = OPEN
CPD
Power Dissipation Capacitance
45.0
pF
VCC = 5.0V
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74AC125 • 74ACT125
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
Package Number M14A
5
www.fairchildsemi.com
74AC125 • 74ACT125
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
www.fairchildsemi.com
6
74AC125 • 74ACT125
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
7
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74AC125 • 74ACT125 Quad Buffer with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-in-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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