ETC 74F189SCX

Revised September 2000
74F189
64-Bit Random Access Memory with 3-STATE Outputs
General Description
Features
The F189 is a high-speed 64-bit RAM organized as a 16word by 4-bit array. Address inputs are buffered to minimize loading and are fully decoded on-chip. The outputs
are 3-STATE and are in the high impedance state whenever the Chip Select (CS) input is HIGH. The outputs are
active only in the Read mode and the output data is the
complement of the stored data.
■ 3-STATE outputs for data bus applications
■ Buffered inputs minimize loading
■ Address decoding on-chip
■ Diode clamped inputs minimize ringing
Ordering Code:
Order Number
Package Number
Package Description
74F189SC
M16B
16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F189SJ
(Note 1)
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F189PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending suffix “X” to the ordering code.
Note 1: This device not available in Tape and Reel.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation
DS009493
www.fairchildsemi.com
74F189 64-Bit Random Access Memory with 3-STATE Outputs
April 1988
74F189
Unit Loading/Fan Out
Pin Names
U.L.
Input IIH/IIL
HIGH/LOW
Output IOH/IOL
Description
A0–A3
Address Inputs
1.0/1.0
20 µA/−0.6 mA
CS
Chip Select Input (Active LOW)
1.0/1.0
20 µA/−1.2 mA
WE
Write Enable Input (Active LOW)
1.0/1.0
20 µA/−0.6 mA
D0–D3
Data Inputs
1.0/1.0
20 µA/−0.6 mA
O 0–O 3
Inverted Data Outputs
150/40 (33.3) −3.0 mA/24 mA (20 mA)
Function Table
Inputs
Operation
CS
L
L
Write
High Impedance
L
H
Read
Complement of Stored Data
H
X
Inhibit
High Impedance
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Block Diagram
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Condition of Outputs
WE
2
Recommended Operating
Conditions
Storage Temperature
−65°C to +150 °C
Ambient Temperature under Bias
−55°C to +125 °C
Free Air Ambient Temperature
Junction Temperature under Bias
−55°C to +175 °C
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
VCC Pin Potential to
−0.5V to +7.0V
Ground Pin
Input Voltage (Note 2)
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
Current Applied to Output
in LOW State (Max)
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
VCD
Input Clamp Diode Voltage
−1.2
V
VOH
2.0
Units
VIH
10% VCC
2.5
IOH = −1 mA
2.4
IOH = −3 mA
5% VCC
2.7
5% VCC
2.7
Input HIGH
V
Min
0.5
V
Min
IOL = 24 mA
5.0
µA
Max
VIN = 2.7V
7.0
µA
Max
VIN = 7.0V
50
µA
Max
VOUT = VCC
V
0.0
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
4.75
Test
IID = 1.9 µA
All Other Pins Grounded
Output Leakage
3.75
Circuit Current
IIL
IOH = −1 mA
IOH = −3 mA
10% VCC
Current
IOD
IIN = −18 mA
10% VCC
IIH
VID
Recognized as a LOW Signal
Min
Output HIGH
Output LOW Voltage
ICEX
Conditions
Recognized as a HIGH Signal
Voltage
VOL
IBVI
VCC
V
−0.6
Input LOW Current
−1.2
µA
0.0
mA
Max
VIOD = 150 mV
All Other Pins Grounded
VIN = 0.5V (except CS)
VIN = 0.5V (CS)
IOZH
Output Leakage Current
50
µA
Max
IOZL
Output Leakage Current
−50
µA
Max
VOUT = 0.5V
IOS
Output Short-Circuit Current
−150
mA
Max
VOUT = 0V
IZZ
Bus Drainage Test
500
µA
0.0V
VOUT = 5.25V
ICCZ
Power Supply Current
55
mA
Max
VO = HIGH Z
−60
37
3
VOUT = 2.7V
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74F189
Absolute Maximum Ratings(Note 2)
74F189
AC Electrical Characteristics
Symbol
Parameter
TA = +25°C
TA = −55°C to +125°C
TA = 0°C to +70°C
VCC = +5.0V
VCC = +5.0V
VCC = +5.0V
CL = 50 pF
CL = 50 pF
CL = 50 pF
Min
Typ
Max
Min
Max
Min
Max
tPLH
Access Time, HIGH or LOW
10.0
18.5
26.0
9.0
32.0
10.0
27.0
tPHL
An to On
8.0
13.5
19.0
8.0
23.0
8.0
20.0
Units
ns
tPZH
Access Time, HIGH or LOW
3.5
6.0
8.5
3.5
10.5
3.5
9.5
tPZL
CS to On
5.0
9.0
13.0
5.0
15.0
5.0
14.0
ns
tPHZ
Disable Time, HIGH or LOW
2.0
4.0
6.0
2.0
8.0
2.0
7.0
tPLZ
CS to On
3.0
5.5
8.0
2.5
10.0
3.0
9.0
ns
tPZH
Write Recovery Time,
6.5
15.0
28.0
6.5
37.5
6.5
29.0
tPZL
HIGH or LOW WE to On
6.5
11.0
15.5
6.5
17.5
6.5
16.5
tPHZ
Disable Time, HIGH or LOW
4.0
7.0
10.0
3.5
12.0
4.0
11.0
tPLZ
WE to On
5.0
9.0
13.0
5.0
15.0
5.0
14.0
ns
ns
AC Operating Requirements
Symbol
Parameter
TA = +25°C
TA = −55°C to +125°C
TA = 0°C to +70°C
VCC = +5.0V
VCC = +5.0V
VCC = +5.0V
Min
tS(H)
Setup Time, HIGH or LOW
tS(L)
An to WE
tH(H)
Hold Time, HIGH or LOW
Max
0
Min
0
Max
Min
Units
Max
0
0
0
0
2.0
2.0
2.0
ns
tH(L)
An to WE
2.0
2.0
2.0
tS(H)
Setup Time, HIGH or LOW
10.0
11.0
10.0
tS(L)
Dn to WE
10.0
11.0
10.0
tH(H)
Hold Time, HIGH or LOW
0
2.0
0
ns
tH(L)
Dn to WE
0
2.0
0
tS(L)
Setup Time, LOW
0
0
0
tH(L)
Hold Time, LOW
6.0
7.5
6.0
6.0
15.0
6.0
CS to WE
ns
CS to WE
tW(L)
WE Pulse Width, LOW
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4
ns
74F189
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M16B
5
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74F189
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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6
74F189 64-Bit Random Access Memory with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
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to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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