Revised September 2000 74F193 Up/Down Binary Counter with Separate Up/Down Clocks General Description The 74F193 is an up/down modulo-16 binary counter. Separate Count Up and Count Down Clocks are used, and in either counting mode the circuits operate synchronously. The outputs change state synchronously with the LOW-toHIGH transitions on the clock inputs. Separate Terminal Count Up and Terminal Count Down outputs are provided that are used as the clocks for subsequent stages without extra logic, thus simplifying multi-stage counter designs. Individual preset inputs allow the circuit to be used as a programmable counter. Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks. Ordering Code: Order Number Package Number Package Description 74F193SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F193SJ (Note 1) M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F193PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Note 1: Device not available in Tape and Reel. Logic Symbols Connection Diagram IEEE/IEC © 2000 Fairchild Semiconductor Corporation DS009497 www.fairchildsemi.com 74F193 Up/Down Binary Counter with Separate Up/Down Clocks April 1988 74F193 Unit Loading/Fan Out Pin Names U.L. Input IIH/IIL Description HIGH/LOW Output IOH/IOL CPU Count Up Clock Input (Active Rising Edge) 1.0/3.0 20 µA/−1.8 mA CPD Count Down Clock Input (Active Rising Edge) 1.0/3.0 20 µA/−1.8 mA MR Asynchronous Master Reset Input (Active HIGH) 1.0/1.0 20 µA/−0.6 mA PL Asynchronous Parallel Load Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA P0–P3 Parallel Data Inputs 1.0/1.0 20 µA/−0.6 mA Q0–Q3 Flip-Flop Outputs 50/33.3 −1 mA/20 mA TCD Terminal Count Down (Borrow) Output (Active LOW) 50/33.3 −1 mA/20 mA TCU Terminal Count Up (Carry) Output (Active LOW) 50/33.3 −1 mA/20 mA Functional Description Function Table The 74F193 is a 4-bit binary synchronous up/down (reversible) counter. It contains four edge-triggered flip-flops, with internal gating and steering logic to provide master reset, individual preset, count up and count down operations. A LOW-to-HIGH transition on the CP input to each flip-flop causes the output to change state. Synchronous switching, as opposed to ripple counting, is achieved by driving the steering gates of all stages from a common Count Up line and a common Count Down line, thereby causing all state changes to be initiated simultaneously. A LOW-to-HIGH transition on the Count Up input will advance the count by one; a similar transition on the Count Down input will decrease the count by one. While counting with one clock input, the other should be held HIGH, as indicated in the Function Table. PL CPU CPD H X X X Reset (Asyn.) L L X X Preset (Asyn.) L H H No Change L H H H Count Up L H H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition State Diagram The Terminal Count Up (TCU) and Terminal Count Down (TCD) outputs are normally HIGH. When the circuit has reached the maximum count state 15, the next HIGH-toLOW transition of the Count Up Clock will cause TCU to go LOW. TCU will stay LOW until CPU goes HIGH again, thus effectively repeating the Count Up Clock, but delayed by two gate delays. Similarly, the TCD output will go LOW when the circuit is in the zero state and the Count Down Clock goes LOW. Since the TC outputs repeat the clock waveforms, they can be used as the clock input signals to the next higher order circuit in a multistage counter. TCU = Q0 • Q1 • Q2 • Q 3 • CPU TCD = Q0• Q1 • Q2 • Q3 • CPD The 74F193 has an asynchronous parallel load capability permitting the counter to be preset. When the Parallel Load (PL) and the Master Reset (MR) inputs are LOW, information present on the Parallel Data input (P0–P3) is loaded into the counter and appears on the outputs regardless of the conditions of the clock inputs. A HIGH signal on the Master Reset input will disable the preset gates, override both clock inputs, and latch each Q output in the LOW state. If one of the clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted as a legitimate signal and will be counted. www.fairchildsemi.com MR 2 Mode Count Down 74F193 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74F193 Absolute Maximum Ratings(Note 2) Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 3) −0.5V to +7.0V Input Current (Note 3) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Current Applied to Output in LOW State (Max) Note 3: Either voltage limit or current limit is sufficient to protect inputs. twice the rated IOL (mA) DC Electrical Characteristics Symbol Parameter Min Typ Max VCC VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min V Min V Min IOL = 20 mA Max VIN = 2.7V µA Max VIN = 7.0V µA Max VOUT = VCC V 0.0 µA 0.0 mA Max Output HIGH 10% VCC 2.5 Voltage 5% VCC 2.7 VOL Output LOW Voltage 10% VCC IIH Input HIGH V Conditions Input HIGH Voltage VOH 2.0 Units VIH 0.5 5.0 Current IBVI ICEX Input HIGH Current 100 Breakdown Test 7.0 Output HIGH 50 Leakage Current VID Input Leakage Test IOD 4.75 Output Leakage 3.75 Circuit Current IIL −0.6 Input LOW Current −1.8 IOS Output Short-Circuit Current ICC Power Supply Current www.fairchildsemi.com −60 38 4 Recognized as a HIGH Signal Recognized as a LOW Signal −150 mA Max 55 mA Max IIN = −18 mA IOH = −1 mA IOH = −1 mA IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V (MR, PL, Pn) VIN = 0.5V (CPu, CPD) VOUT = 0V 74F193 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Min Typ fMAX Maximum Count Frequency 100 125 Max Min tPLH Propagation Delay 4.0 7.0 9.0 4.0 10.0 tPHL CPU or CPD to 3.5 6.0 8.0 3.5 9.0 Units Max 90 MHz ns TCU or TCD tPLH Propagation Delay 4.0 6.5 8.5 4.0 9.5 tPHL CPU or CPD to Qn 5.5 9.5 12.5 5.5 13.5 tPLH Propagation Delay 3.0 4.5 7.0 3.0 8.0 tPHL Pn to Qn 6.0 11.0 14.5 6.0 15.5 tPLH Propagation Delay 5.0 8.5 11.0 5.0 12.0 tPHL PL to Qn 5.5 10.0 13.0 5.5 14.0 tPHL Propagation Delay 5.5 11.0 14.5 5.5 15.5 6.0 10.5 13.5 6.0 14.5 6.0 11.5 14.5 6.0 15.5 MR to Qn tPLH Propagation Delay MR to TCU tPHL Propagation Delay MR to TCD tPLH Propagation Delay 7.0 12.0 15.5 7.0 16.5 tPHL PL to TCU or TCD 7.0 11.5 14.5 7.0 15.5 tPLH Propagation Delay 7.0 11.5 14.5 7.0 15.5 tPHL Pn to TCU or TCD 6.5 11.0 14.0 6.5 15.0 ns ns ns ns ns ns AC Operating Requirements TA = +25°C Symbol VCC = +5.0V Parameter Min Max TA = 0°C to +70°C VCC = +5.0V Min tS(H) Setup Time, HIGH or LOW 4.5 5.0 tS(L) Pn to PL 4.5 5.0 tH(H) Hold Time, HIGH or LOW 2.0 2.0 Units Max ns tH(L) Pn to PL 2.0 2.0 tW(L) PL Pulse Width, LOW 6.0 6.0 ns tW(L) CPU or CPD 5.0 5.0 ns 10.0 10.0 ns 6.0 6.0 ns 6.0 6.0 ns 4.0 4.0 ns Pulse Width, LOW tW(L) CPU or CPD Pulse Width, LOW (Change of Direction) tW(H) MR Pulse Width, HIGH tREC Recovery Time PL to CPU or CPD tREC Recovery Time MR to CPU or CPD 5 www.fairchildsemi.com 74F193 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A www.fairchildsemi.com 6 74F193 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 7 www.fairchildsemi.com 74F193 Up/Down Binary Counter with Separate Up/Down Clocks Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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