ETC 74FST3244/D

74FST3244
8-Bit Bus Switch
The ON Semiconductor 74FST3244 is an 8–bit, high performance
switch. The device is CMOS TTL compatible when operating between
4 and 5.5 Volts. The device exhibits extremely low RON and adds
nearly zero propagation delay. The device adds no noise or ground
bounce to the system.
The device consists of two 4–bit switches with separate
Output/Enable (OE) pins. Port A is connected to Port B when OE is
low. If OE is high, the switch is high Z.
•
•
•
•
•
•
•
RON 4 Typical
Less Than 0.25 ns–Max Delay Through Switch
Nearly Zero Standby Current
No Circuit Bounce
Control Inputs are TTL/CMOS Compatible
Pin–For–Pin Compatible with QS3244, FST3244, CBT3244
All Popular Packages: QSOP–20, TSSOP–20, SOIC–20
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MARKING
DIAGRAMS
20
20
1
FST3244
AWLYYWW
SO–20
DW SUFFIX
CASE 751D
1
20
20
FST
3244
ALYW
1
OE1
1A0
2B3
1A1
2B2
1A2
2B1
1A3
2B0
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TSSOP–20
DT SUFFIX
CASE 948E
VCC
OE2
1B0
2A3
1B1
2A2
1B2
2A1
1B3
2A0
20
20
FST3244
AWLYWW
1
QSOP–20
QS SUFFIX
CASE 492A
Figure 1. 20–Lead Pinout
A
L, WL
Y
W, WW
TRUTH TABLE
Inputs
1
=
=
=
=
1
Assembly Location
Wafer Lot
Year
Work Week
PIN NAMES
Pin
Inputs/Outputs
Description
OE1
OE2
1A, 1B
2A, 2B
OE1, OE2
L
1A = 1B
1A = 1B
2A = 2B
Z
1A, 2A
Bus A
L
L
H
1B, 2B
Bus B
H
L
Z
2A = 2B
H
H
Z
Z
Bus Switch Enables
ORDERING INFORMATION
 Semiconductor Components Industries, LLC, 2001
August, 2001 – Rev. 0
1
Device
Package
Shipping
74FST3244DW
SO–20
38 Units/Rail
74FST3244DWR2
SO–20
1000 Units/Reel
74FST3244DT
TSSOP–20
75 Units/Rail
74FST3244DTR2
TSSOP–20
2500 Units/Reel
74FST3244QS
QSOP–20
55 Units/Rail
74FST3244QSR
QSOP–20
2500 Units/Reel
Publication Order Number:
74FST3244/D
74FST3244
OE1
1A0
1A3
OE3
2A0
2A3
1
2
3
5
6
1B0
1B3
10
9
8
12
11
Figure 2. Logic Diagram
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2
2B0
2B3
74FST3244
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage
0.5 to 7.0
V
VI
DC Input Voltage
0.5 to 7.0
V
VO
DC Output Voltage
0.5 to 7.0
V
IIK
DC Input Diode Current
VI GND
50
mA
IOK
DC Output Diode Current
VO GND
50
mA
IO
DC Output Sink Current
128
mA
ICC
DC Supply Current per Supply Pin
100
mA
IGND
DC Ground Current per Ground Pin
100
mA
TSTG
Storage Temperature Range
65 to 150
C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
Junction Temperature Under Bias
JA
Thermal Resistance (Note 1)
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
ESD Withstand Voltage
Human Body Model (Note 2)
Machine Model (Note 3)
2000
200
V
ILATCH–UP
Latch–Up Performance
Above VCC and Below GND at 85C (Note 4)
500
mA
SOIC
TSSOP
QSOP
260
C
150
C
96
128
200
C/W
Level 1
Oxygen Index: 28 to 34
UL 94 V–0 @ 0.125 in
Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm–by–1 inch, 2–ounce copper trace with no air flow.
2. Tested to EIA/JESD22–A114–A.
3. Tested to EIA/JESD22–A115–A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
Supply Voltage
VI
Input Voltage
VO
Output Voltage
TA
Operating Free–Air Temperature
t/V
Input Transition Rise or Fall Rate
Min
Max
Unit
4.0
5.5
V
(Note )
0
5.5
V
(HIGH or LOW State)
0
VCC
V
40
85
C
0
0
5
DC
ns/V
Operating, Data Retention Only
Switch Control Input
Switch I/O
5. Unused control inputs may not be left open. All control inputs must be tied to a high or low logic input voltage level.
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3
74FST3244
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
IIN = 18mA
VCC
TA = 40C to 85C
(V)
Min
Typ*
4.5
Max
Unit
1.2
V
VIK
Clamp Diode Resistance
VIH
High–Level Input Voltage
VIL
Low–Level Input Voltage
4.0 to 5.5
0.8
V
II
Input Leakage Current
0 VIN 5.5 V
5.5
1.0
A
IOZ
OFF–STATE Leakage Current
0 A, B VCC
5.5
1.0
A
RON
Switch On Resistance (Note 6)
VIN = 0 V, IIN = 64 mA
4.5
4
7
VIN = 0 V, IIN = 30 mA
4.5
4
7
VIN = 2.4 V, IIN = 15 mA
4.5
8
15
11
20
4.0 to 5.5
2.0
V
VIN = 2.4 V, IIN = 15 mA
4.0
ICC
Quiescent Supply Current
VIN = VCC or GND, IOUT = 0
5.5
3
A
ICC
Increase In ICC per Input
One input at 3.4 V, Other inputs at VCC or GND
5.5
2.5
mA
*Typical values are at VCC = 5.0 V and TA = 25C.
6. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower
of the voltages on the two (A or B) pins.
AC ELECTRICAL CHARACTERISTICS
Limits
TA = 40C to 85C
VCC = 4.5 to 5.5 V
Symbol
Parameter
Conditions
Figures
tPHL,
tPLH
Prop Delay Bus to Bus
(Note 7)
VI = OPEN
3 and 4
tPZH,
tPZL
Output Enable Time
VI = 7 V for tPZL
VI = OPEN for tPZH
3 and 4
tPHZ,
tPLZ
Output Disable Time
VI = 7 V for tPLZ
VI = OPEN for tPHZ
3 and 4
Min
Max
VCC = 4.0 V
Max
Unit
0.25
Min
0.25
ns
1.0
5.6
6.1
ns
1.5
6.2
5.6
ns
7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the
typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).
CAPACITANCE (Note 8)
Symbol
Parameter
Conditions
Typ
Max
Unit
CIN
Control Pin Input Capacitance
VCC = 5.0 V
3
pF
CI/O
Input/Output Capacitance
VCC, OE = 5.0 V
5
pF
8. TA = 25C, f = 1 MHz, Capacitance is characterized but not tested.
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4
74FST3244
AC Loading and Waveforms
VI
500 FROM
OUTPUT
UNDER
TEST
CL *
500 NOTES:
1. Input driven by 50 source terminated in 50 .
2. CL includes load and stray capacitance.
*CL = 50 pF
Figure 3. AC Test Circuit
tf = 2.5 nS
90 %
SWITCH
INPUT
tf = 2.5 nS
3.0 V
90 %
1.5 V
1.5 V
10 %
10 %
tPLH
GND
tPLH
VOH
1.5 V
1.5 V
OUTPUT
VOL
Figure 4. Propagation Delays
tf = 2.5 nS
tf = 2.5 nS
ENABLE
INPUT
90 %
90 %
1.5 V
1.5 V
10 %
10 %
tPZL
OUTPUT
3.0 V
GND
tPZL
1.5 V
tPZH
VOL + 0.3 V
VOL
tPHZL
VOH
1.5 V
OUTPUT
Figure 5. Enable/Disable Delays
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5
VOH – 0.3 V
74FST3244
PACKAGE DIMENSIONS
SO–20
DW SUFFIX
CASE 751D–05
ISSUE F
A
20
X 45 h
1
10
20X
DIM
A
A1
B
C
D
E
e
H
h
L
B
B
0.25
M
T A
S
B
S
A
L
H
M
E
0.25
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
11
B
M
D
18X
e
SEATING
PLANE
A1
C
T
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0
7
TSSOP–20
DT SUFFIX
CASE 948E–02
ISSUE A
20X
0.15 (0.006) T U
2X
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
S
K
K1
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
11
J J1
B
L
–U–
PIN 1
IDENT
SECTION N–N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
S
M
A
–V–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
N
F
DETAIL E
–W–
C
D
G
H
DETAIL E
0.100 (0.004)
–T– SEATING
PLANE
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6
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
8
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0
8
74FST3244
PACKAGE DIMENSIONS
QSOP–20
QS SUFFIX
CASE 492A–01
ISSUE O
–A–
Q
R
H x 45
U
0.25 (0.010)
RAD.
0.005–0.010
TYP
G
P
L
MOLD PIN
MARK
RAD.
0.013 X 0.005
DP. MAX
–B–
DETAIL E
T
M
V
N 8 PL
J
K
M
–T–
C
20 PL
D
0.25 (0.010)
SEATING
PLANE
M
T B
S
A
F
S
DETAIL E
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7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. THE BOTTOM PACKAGE SHALL BE BIGGER THAN
THE TOP PACKAGE BY 4 MILS (NOTE: LEAD SIDE
ONLY). BOTTOM PACKAGE DIMENSION SHALL
FOLLOW THE DIMENSION STATED IN THIS
DRAWING.
4. PLASTIC DIMENSIONS DOES NOT INCLUDE MOLD
FLASH OR PROTRUSIONS. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 6 MILS PER
SIDE.
5. BOTTOM EJECTOR PIN WILL INCLUDE THE
COUNTRY OF ORIGIN (COO) AND MOLD CAVITY I.D.
INCHES
DIM MAX
MIN
A
0.337
0.344
B
0.150
0.157
C
0.061
0.068
D
0.008
0.012
F
0.016
0.035
G
0.025 BSC
H
0.008
0.018
J 0.0098 0.0075
K
0.004
0.010
L
0.230
0.244
M
0
8
N
0
7
P
0.052
0.062
Q
0.035 DIA
R
0.035
0.045
U
0.035
0.045
8
V
0
MILLIMETERS
MAX
MIN
8.56
8.74
3.81
3.99
1.55
1.73
0.20
0.31
0.41
0.89
0.64 BSC
0.20
0.46
0.249
0.191
0.10
0.25
5.84
6.20
0
8
0
7
1.32
1.58
0.89 DIA
0.89
1.14
0.89
1.14
0
8
74FST3244
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
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4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031
Phone: 81–3–5740–2700
Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
N. American Technical Support: 800–282–9855 Toll Free USA/Canada
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8
74FST3244/D