ETC 82C205

®
ChromaCast
82C205
LCD Monitor Controller
Advance Information
CONFIDENTIAL
Revision 1.0
912-1000-024
7/8/99
Copyright
No part of this publication may be reproduced, transmitted, transcribed,
stored in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic,
mechanical, magnetic, optical, manual, or otherwise, without the prior written permission of OPTi Inc., 1440 McCarthy Blvd.
Milpitas, CA 95035.
Disclaimer
OPTi Inc. makes no representations or warranties with respect to the design and documentation herein described and
especially disclaims any implied warranties of merchantability or fitness for any particular purpose. Further, OPTi Inc.
reserves the right to revise the design and associated documentation and to make changes from time to time in the content
without obligation of OPTi Inc. to notify any person of such revisions or changes.
Trademarks
OPTi and OPTi Inc. are registered trademarks of OPTi Inc. All other trademarks and copyrights are the property of
their respective holders.
OPTi Inc.
1440 McCarthy Blvd.
Milpitas, CA 95035
Tel: (408) 486-8000
Fax: (408) 486-8001
WWW: http://www.opti.com
Advance Information
82C205
®
Table of Contents
1.
FEATURES .........................................................................................................................................................1
2.
OVERVIEW .........................................................................................................................................................3
3.
SIGNAL DEFINITIONS .......................................................................................................................................5
4.
5.
3.1.
PIN DIAGRAM .................................................................................................................................................5
3.2.
PIN LISTING....................................................................................................................................................6
3.3.
SIGNAL DESCRIPTIONS ...................................................................................................................................8
3.3.1.
Terminology/Nomenclature Conventions ..............................................................................................8
3.3.2.
CPU and System Interface....................................................................................................................8
3.3.3.
NTSC/PAL Decoder Interface ...............................................................................................................9
3.3.4.
DRAM Interface.....................................................................................................................................9
3.3.5.
Panel Interface Signals .......................................................................................................................10
3.3.6.
Power and Ground Signals .................................................................................................................10
3.4.
TEST MODE SIGNALS ...................................................................................................................................12
3.5.
POWER AND GROUND PINS...........................................................................................................................12
3.6.
POWER UP STRAPPING ASSIGNMENTS ..........................................................................................................13
3.6.1.
Panel Type ..........................................................................................................................................13
3.6.2.
Register Base Address Strapping .......................................................................................................13
FUNCTIONAL DESCRIPTION..........................................................................................................................15
4.1.
INTERNAL BLOCK DIAGRAM ...........................................................................................................................15
4.2.
MICRO-CONTROLLER INTERFACE ..................................................................................................................15
4.3.
INPUT SOURCE .............................................................................................................................................15
4.4.
AUTOMATIC RESOLUTION DETECTION ...........................................................................................................16
4.5.
TV MODE.....................................................................................................................................................16
4.6.
FULL SCALE AND CENTERING OPTIONS .........................................................................................................16
4.7.
CONTRAST/BRIGHTNESS CONTROL ...............................................................................................................16
4.8.
ON SCREEN DISPLAY ...................................................................................................................................16
4.9.
DITHERING ...................................................................................................................................................17
4.10.
VERSATILE PANEL SUPPORT .....................................................................................................................17
4.11.
CLOCK GENERATION .................................................................................................................................17
4.12.
DRAM INTERFACE....................................................................................................................................18
REGISTER DESCRIPTIONS ............................................................................................................................19
5.1.
REVISION REGISTER .....................................................................................................................................19
5.2.
SYSTEM CONTROL REGISTER .......................................................................................................................19
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82C205
6.
5.3.
MEMORY CONTROL REGISTERS ................................................................................................................... 19
5.4.
OSD REGISTERS ........................................................................................................................................ 22
5.5.
DITHER REGISTER SETTINGS ....................................................................................................................... 23
5.6.
CAPTURE CRTC REGISTERS ....................................................................................................................... 23
5.7.
SCALING REGISTERS ................................................................................................................................... 25
5.8.
CONTRAST AND BRIGHTNESS CONTROL REGISTERS ..................................................................................... 27
5.9.
VIDEO INPUT SOURCE SELECTION REGISTERS.............................................................................................. 27
5.10.
RESOLUTION DETECTION REGISTERS ....................................................................................................... 28
5.11.
TV DECODER INTERFACE REGISTERS ...................................................................................................... 29
5.12.
DISPLAY HORIZONTAL SCALING ................................................................................................................ 30
5.13.
DISPLAY CRTC REGISTERS ..................................................................................................................... 30
5.14.
PANEL REGISTERS ................................................................................................................................... 33
5.15.
BANDWIDTH CONSERVATION REGISTERS .................................................................................................. 34
5.16.
INTERRUPT CONTROL REGISTERS ............................................................................................................ 34
5.17.
CLUT ACCESS CONTROL ........................................................................................................................ 35
5.18.
ADC AND PLL CONTROL REGISTERS ....................................................................................................... 35
5.19.
POWER MANAGEMENT REGISTERS ........................................................................................................... 35
5.20.
CLUT REGISTERS ................................................................................................................................... 36
5.21.
STATUS REGISTERS ................................................................................................................................. 38
5.22.
I/O CONTROL REGISTERS ........................................................................................................................ 39
TIMING INFORMATION AND WAVEFORMS ................................................................................................. 40
VERTICAL TIMING FOR TFT PANEL .......................................................................................................................... 40
6.2.
HORIZONTAL TIMING FOR TFT PANEL .......................................................................................................... 41
DETAIL OF PIXEL CLOCK TIMING ............................................................................................................................. 41
6.4.
7.
MICRO-CONTROLLER INTERFACE ................................................................................................................. 41
208-PIN PQFP MECHANICAL DRAWING ...................................................................................................... 47
®
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82C205
®
1. Features
Digital Input Support
•
24-bit digital input
•
300 Mb/sec data rate
Full Screen Image Scaling At All
Resolutions
•
Incoming video scaled via high quality
interpolation/decimation filters to full panel
screen size
Multiple LCD Panel Type Support
•
Horizontal frequency from 15 to 70 kHz
•
Vertical frequency from 40 to 85 Hz
Host Interface
•
Direct 8-bit micro-controller interface (8051compatible)
LCD TV Support
•
Direct video decoder interface support for
LCD TV applications
•
High quality scale up algorithm for TV input
•
9, 12, 18, 24, 36 bit TFT panel resolution
from 640x480 up to 1280x1024
•
Drives Single/Multiple Pixels per Clock
•
DPMS for Display Power Management
•
90 Hz panel refresh rate for TFT
•
FPDI-1 Flat Panel Display Interface
•
LVDS and PanelLink transceiver interface
for FPDI-2 (24 bpp mode)
VESA Compliant
Super OSD Support
•
16-color OSD support
•
Transparent, translucent, inverted video, and
blinking color attribute support
Multi-sync support
•
Supports incoming video with resolutions
from 640x480 up to 1280x1024
•
Automatic incoming resolution detection
912-1000-024
Revision 2.0
Electrical/Physical Specification
•
0.35 µm process
•
3.3 Volt power supply
•
5V-tolerant I/O
•
208 PQF package
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82C205
®
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82C205
®
2. Overview
This data book describes the ChromaCast 82C205 LCD monitor controller, a cost reduced solution for LCD (liquid
crystal display) monitor control from OPTi Inc. The ChromaCast solution supports a 64-bit DRAM interface for data
buffering, an 8051-compatible micro-controller interface, a 24-bit digital interface that can be used with an RGB
A/D converter, a PanelLink™ receiver, or an NTSC/PAL decoder, and direct drive control for TFT panels.
ChromaCast 82C205 is packaged in a 208-pin PQF package. 82C205 is a cost-effective, high-performance
universal panel controller. Figure 1 shows a system configuration using the 82C205.
8051
16
R-G-B
sync
A/D
+
PLL
PanelLink
option
available
24
OPTi
36
82C205
64
SDRAM
4MB
Figure 1.
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ChromaCast 82C205 System Diagram
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82C205
®
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82C205
®
3. Signal Definitions
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
GND (G2)
MD22
MD23
DQM3#
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MCLK
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
VCC3 (P0/P2)
BS
SDWE#
GND (G0)
SDCAS#
SDRAS#
SDCS#
DQM4#
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
DQM5#
MD40
MD41
MD42
MD43
VCC3 (P2)
MD44
MD45
MD46
MD47
DQM6#
MD48
AVCC-PLL2 (AP2)
3.1. Pin Diagram
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
ChromaCast
82C205
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
AGND-PLL2 (AG2)
GND (G2)
MD49
MD50
MD51
GND (G0)
MD52
MD53
MD54
MD55
VCC3 (P0/P2)
DQM7#
MD56
MD57
MD58
ND59
MD60
MD61
MD62
MD63
FPDR0
FPDR1
FPDR2
FPDR3
VCC3-LCD (P1)
FPDR4
FPDR5
FPDR6
FPDR7
FPDR8
FPDR9
AGND-SRAM (AGS)
FPDR10
VCC3-SRAM (APS)
FPDR11
AGND-SRAM (AGS)
FPDB0
FPDB1
VCC3-SRAM (APS)
FPDB2
FPDB3
FPDB4
FPDB5
VCC3-LCD (P1)
FPDB6
FPDB7
FPDB8
FPDB9
FPDB10
FPDB11
GND (G1)
AGN-PLL3 (AG3)
GND (G2)
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
VCC3 (P0/P2)
VCLK1
HSYNC+TV-HS+DE
VSYNC+TV-VS
TV-CK2
GND (G0)
FPFRAME
FPLINE
DE
GND (G1)
FPSHIFT
AGND-SRAM (AG5)
FPDG11
FPDG10
VCC3-SRAM (APS)
FPDG9
FPDG8
FPDG7
FPDG6
VCC3-LCD (P1)
FPDG5
FPDG4
FPDG3
FPDG2
FPDG1
FPDG0
VCC-PLL3 (AP3)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
MD21
MD20
MD19
MD18
MD17
MD16
DQM2#
GND-(G0)
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
DQM1#
VCC3 (P0/P2)
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
DQM0#
CPUAD15
CPUAD14
CPUAD13
CPUAD12
CPUAD11
CPUAD10
CPUAD9
CPUAD8
CPUAD7
CPUAD6
CPUAD5
CPUAD4
CPUAD3
CPUAD2
CPUAD1
CPUAD0
VCC3 (P2)
CPUINT+TESTOUT
PSEN#
ALE+TMODE
CPU-WR#+TSCAN-EN
CPU-RD#+TEST-IN
REFCLK
RESET#
TMS
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82C205
3.2. Pin Listing
Signal Name
Pin
No.
Signal Name
Pin
No.
Signal Name
1
GND (G2)
35
GND (G1)
69
AGND_SRAM (AGS)
2
R0
36
FPSHIFT
70
FPDR11
3
R1
37
AGND_SRAM (AGS)
71
VCC3_SRAM (APS)
4
R2
38
FPDG11
72
FPDR10
5
R3
39
FPDG10
73
AGND_SRAM (AGS)
6
R4
40
VCC3_SRAM (APS)
74
FPDR9
7
R5
41
FPDG9
75
FPDR8
8
R6
42
FPDG8
76
FPDR7
9
R7
43
FPDG7
77
FPDR6
10
G0
44
FPDG6
78
FPDR5
11
G1
45
VCC3_LCD (P1)
79
FPDR4
12
G2
46
FPDG5
80
VCC3_LCD (P1)
13
G3
47
FPDG4
81
FPDR3
14
G4
48
FPDG3
82
FPDR2
15
G5
49
FPDG2
83
FPDR1
16
G6
50
FPDG1
84
FPDR0
17
G7
51
FPDG0
85
MD63
18
B0
52
VCC3_PLL3 (AP3)
86
MD62
19
B1
53
AGND_PLL3 (AG3)
87
MD61
20
B2
54
GND (G1)
88
MD60
21
B3
55
FPDB11
89
MD59
22
B4
56
FPDB10
90
MD58
23
B5
57
FPDB9
91
MD57
24
B6
58
FPDB8
92
MD56
25
B7
59
FPDB7
93
DQM7#
26
VCC3 (P0/P2)
60
FPDB6
94
VCC3 (P0/P2)
27
VCLK1
61
VCC3_LCD (P1)
95
MD55
28
HSYNC+TV_HS
62
FPDB5
96
MD54
29
VSYNC+TV_VS
63
FPDB4
97
MD53
30
TV_CK2
64
FPDB3
98
MD52
31
GND (G0)
65
FPDB2
99
GND (G0)
32
FPFRAME
66
VCC3_SRAM (APS)
100
MD51
33
FPLINE
67
FPDB1
34
DE
68
FPDB0
Pin
No.
®
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82C205
Pin
No.
Signal Name
Pin
No.
Signal Name
Pin
No.
Signal Name
101
MD50
137
MA6
173
DQM1#
102
MD49
138
MA5
174
VCC3 (P0/P2)
103
GND (G2)
139
MA4
175
MD7
104
AGND_PLL2 (AG2)
140
MA3
176
MD6
105
AVCC_PLL2 (AP2)
141
MA2
177
MD5
106
MD48
142
MA1
178
MD4
107
DQM6#
143
MA0
179
MD3
108
MD47
144
MCLK
180
MD2
109
MD46
145
MD31
181
MD1
110
MD45
146
MD30
182
MD0
111
MD44
147
MD29
183
DQM0#
112
VCC3 (P2)
148
MD28
184
CPUAD15
113
MD43
149
MD27
185
CPUAD14
114
MD42
150
MD26
186
CPUAD13
115
MD41
151
MD25
187
CPUAD12
116
MD40
152
MD24
188
CPUAD11
117
DQM5#
153
DQM3#
189
CPUAD10
118
MD39
154
MD23
190
CPUAD9
119
MD38
155
MD22
191
CPUAD8
120
MD37
156
GND (G2)
192
CPUAD7
121
MD36
157
MD21
193
CPUAD6
122
MD35
158
MD20
194
CPUAD5
123
MD34
159
MD19
195
CPUAD4
124
MD33
160
MD18
196
CPUAD3
125
MD32
161
MD17
197
CPUAD2
126
DQM4#
162
MD16
198
CPUAD1
127
SDCS#
163
DQM2#
199
CPUAD0
128
SDRAS#
164
GND (G0)
200
VCC3 (P2)
129
SDCAS#
165
MD15
201
CPUINT+TESTOUT
130
GND (G0)
166
MD14
202
PSEN#
131
SDWE#
167
MD13
203
ALE+TMODE
132
BS
168
MD12
204
CPU_WR#+TSCAN_EN
133
VCC3 (P0/P2)
169
MD11
205
CPU_RD#+TEST_IN
134
MA9
170
MD10
206
REFCLK
135
MA8
171
MD9
207
RESET#
136
MA7
172
MD8
208
TMS
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82C205
3.3. Signal Descriptions
3.3.1. Terminology/Nomenclature Conventions
The "#" symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at
a low voltage level. When "#" is not present after the signal name, the signal is asserted when at the high voltage
level.
The terms "assertion" and "negation" are used extensively. This is done to avoid confusion when working with a
mixture of "active low" and "active high" signals. The term "assert", or "assertion", indicates that a signal is active,
independent of whether that level is represented by a high or low voltage. The term "negate", or "negation",
indicates that a signal is inactive.
3.3.2.
CPU and System Interface
Signal Name
Pin
No.
Signal
Type
CPU_RD#
TEST_IN
205
I
CPU active low read strobe when TMS=0.
Test Input for Nand Tree and Tri-state tests when TMS=1
CPU_WR#
TSCAN_EN
204
I
CPU active low write strobe when TMS=0.
Reserved Input for tests when TMS=1
ALE+TMODE
203
I
CPU Address latch enable.
ChromaCast latches address from CPU address/data bus at negative edge of ALE.
When TMS=1, TMODE selects between NAND tree and tri-state testing (see Section
3.4, "Test Mode Signals").
CPUAD_[15:5]
190
199
I
I/O
CPU address/data bus bits [15:0]
Low Byte ([7:0]) is multiplexed data and the lower address byte.
Upper Byte (15:8) is upper address byte.
CPUINT +
TESTOUT
201
O
CPU active low interrupt when TMS=0.
Test Output for Nand Tree and Tri-state Tests when TMS=1
RESET#
207
I
ChromaCast System Reset (active low).
The minimum RESET time is 1ms, i.e. the RESET signal should stays active for at
least 1ms after power is stabilized.
REFCK
206
I
Reference Clock. 14.318 MHz reference clock driven externally.
CPUAD_[7:0]
Signal Description
This same 14MHz clock must be used to drive the external microcontroller.
PSEN#
202
I
Program strobe enable.
Active low signal indicates that the CPU needs to fetch a progarm instruction.
TMS
208
I
Test Mode Select – Sets test mode at power-up (see Secton 3.4, "Test Mode
Signals").
TMS=0: Normal operation
TMS=1: Test mode
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82C205
3.3.3.
NTSC/PAL Decoder Interface
Signal Name
Pin
No.
Signal
Type
R[7:0]
2-9
I
Digital Red Input
G[7:0]
1017
I
Digital Green Input
– OR –
Digital Luminance Data input for 16-bit NTSC/PAL Decoder Interface or Digital
Luminance and Chrominance Data input for 8-bit NTSC/PAL Decoder Interface.
B[7:0]
1825
I
Digital Blue Input
– OR –
Digital Chrominance Data input for 16-bit NTSC/PAL Decoder Interface.
VCLK1
27
I
Video Capture Clock from external line-locked PLL
TV_CK2
30
I
Clock from the NTSC/PAL Decoder.
HSYNC
28
I
Horizontal Sync signal from VGA
– OR –
HREF signal from NTSC/PAL Decoder
29
I
Vertical Sync signal from VGA
– OR –
Odd/Even flag from NTSC/PAL Decoder.
TV_HS
VSYNC
TV_VS
3.3.4.
Signal Description
DRAM Interface
Signal Name
Pin
No.
Signal
Type
DQM#[7:0]
93,
107,
117,
126,
153,
163,
173,
183
O
Data Mask (DQM) for SDRAM.
BS
132
O
SDRAM Bank Select (Active low)
MCLK
144
I/O
Memory clock for Memory Controller and SDRAM.
Internal MCK PLL or External oscillator provides this clock.
MD[63:0]
See
Sec
3.1
I/O
Memory data bus (64-bit).
MA[9:0]
134
143
O
Memory address bus signals.
SDRAS#
128
O
SDRAM RAS (Active Low)
SDCAS#
129
O
SDRAM CAS (Active Low)
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Signal Description
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82C205
Signal Name
Pin
No.
Signal
Type
SDCS#
127
O
Signal Description
SDRAM Chip Select (Active Low)
EDO RAS (Active Low)
SDWE#
3.3.5.
131
O
Write Enable (Active Low)
Panel Interface Signals
Signal Name
Pin
No.
Signal
Type
FPFRAME
32
O
Flat panel FRAME signal.
Analogous to vertical sync. Programmable polarity.
FPLINE
33
O
Flat panel line signal.
Analogous to horizontal sync. Programmable polarity.
FPSHIFT
36
O
Shift clock.
Analogous to pixel clock. Shift Clock can be programmed to be gated by DE.
DE
34
O
Panel enable (data ready) signal for display. Also known as DRDY.
FPDR[11:0]
7083
O
Flat Panel Red Display Data for TFT Mode (See Section 3.3.6.1 below for complete
mapping)
FPDG[11:0]
3957
O
Flat Panel Green Display Data (See Section 3.3.6.1 below for complete mapping)
FPDB[11:0]
5568
O
Flat Panel Blue Display Data (See Section 3.3.6.1 below for complete mapping)
3.3.6.
Signal Description
Power and Ground Signals
Signal Name
Pin
No.
Signal
Type
VCC3 (P0/P2)
26,
94,
112,
133,
174,
200
P
Core power plane. Also supplies I/O power for CPU, YUV and DRAM.
VCC_SRAM
(APS)
40,
66,
71
P
SRAM power plane
VCC_PLL2
(AP2)
105
P
PLL2 power plane
VCC3_PLL3
(AP3)
52
P
PLL3 power plane
VCC3_LCD
(P1)
45,
61,
80
P
Power plane for LCD
®
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Signal Description
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Revision 1.0
Advance Information
82C205
Signal Name
Pin
No.
Signal
Type
AGND_SRAM
(AGS)
37,
69,
73
P
Analog ground for SRAM
AGND_PLL2
(AG2)
104
P
Analog ground for PLL2
AGND_PLL3
(AG3)
53
P
Analog ground for PLL3
GND (G0)
31,
99,
130,
164
G
Digital ground for core plane
GND
(G1 and G2)
1,
35,
54,
103,
156,
G
Digital ground for all I/O planes
3.3.6.1.
Signal Description
TFT Panel Data Pin Mapping
(O: pixel#1,3,5…; E: pixel#2,4,6…)
Mode
Red (O)
A-333-S09
FPDR[7:5]
A-333-S18
FPDR[7:5]
A-444-S12
FPDR[7:4]
A-444-S24
FPDR[7:4]
A-666-S18
FPDR[7:2]
A-666-S36
FPDR[7:2]
A-888-S24
FPDR[7:0]
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Red (E)
Green (O)
Green (E)
FPDG[7:5]
FPDR[15:13]
FPDG[7:5]
FPDG[7:4]
FPDG[15:13]
FPDG[7:2]
FPDG[7:0]
FPDB[7:5]
FPDB[15:13]
FPDB[7:4]
FPDG[15:12]
FPDG[7:2]
FPDR[15:10]
Blue (E)
FPDB[7:5]
FPDG[7:4]
FPDR[15:12]
Blue (O)
FPDB[7:4]
FPDB[15:12]
FPDB[7:2]
FPDG[15:10]
FPDB[7:2]
FPDB[15:10]
FPDB[7:0]
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3.4. Test Mode Signals
Signal Name
Pin
No.
Signal
Type
TMS
208
I
Signal Description
Test Mode Select – Sets mode at power-up
TMS
TMODE
Operation Mode
0
0
Normal
0
1
Reserved
1
0
NAND-tree operation
1
1
Tri-state operation
TESTIN
205
I
Test Input for Nand Tree and Tri-state tests
TESTOUT
201
O
Test Output for Nand Tree and Tri-state Tests
3.5. Power and Ground Pins
Signal Name
Pin
No.
Signal
Type
GND (G0)
31
G
GND (G0)
99
G
GND (G0)
130
G
GND (G0)
164
G
GND (G1)
35
G
GND (G1)
54
G
GND (G2)
1
G
GND (G2)
103
G
GND (G2)
156
G
AGND_SRAM
(AGS)
37,
69,
73
G
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Signal Name
Pin
No.
Signal
Type
AGND_PLL2
(AG2)
104
G
AGND_PLL3
(AG3)
53
VCC3 (P0/P2)
Signal Name
Pin
No.
Signal
Type
VCC3_LCD (P1)
80
P
105
P
G
AVCC_PLL2
(AP2)
P
P
VCC3_PLL3
(AP3)
52
26
VCC3 (P0/P2)
94
P
P
133
P
VCC3_SRAM
(APS)
40
VCC3 (P0/P2)
VCC3 (P0/P2)
174
P
VCC3_SRAM
(APS)
66
P
VCC3 (P2)
112
P
P
200
P
VCC3_SRAM
(APS)
71
VCC3 (P2)
VCC3_LCD (P1)
45
P
VCC3_LCD (P1)
61
P
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82C205
3.6. Power Up Strapping Assignments
3.6.1.
Panel Type
Signal Name
Signal Description
MD[9:6]
At power-up, these pins strap the panel type. A 4.7KΩ resistor to ground represents 0.
0000 = Reserved
0001 = Reserved
0010 = Reserved
0100 = A333-S09
0101 = A444-S12
0110 = A666-S18
0111 = A888-S24
1000 = A333-S18
1001 = A444-S24
1010 = A666-S36
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
3.6.2.
Register Base Address Strapping
Signal Name
Signal Description
MD[5:0]
At power-up, these pins strap a portion of the register base address for ChromaCast’s register
file, which corresponds to address bits [13:8] of the micro-controller bus. The setting 01h is not
allowed due to a conflict with the CLUT BASE default.
Bit 5 4 3 2 1 0 Operation
0 0 0 0 0 0 Fixed address at 8000h
0 0 0 0 0 1 Relocate Address to 8100h
----1 1 1 1 1 1 Relocate Address to BF00h
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82C205
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®
4. Functional Description
4.1. Internal Block Diagram
TV Proc
Digital RGB/
TV YUV
VCLK1
RFCK
MCLK
Scaling
Dither
Engine
Engine
OSD
Memory
Overlay
Control
TV
Display
Control
Panel
Panel I/F
Control
PLL2
PLL3
DRAM I/F
Host
Interface
8051 CPU
I/F
Figure 2.
ChromaCast Internal Block Diagram
4.2. Micro-Controller Interface
The 82C205 interfaces to the popular 8051-compatible micro-controller with a shared 16-bit address and data bus
(8-bit). The 82C205 provides the micro-controller with one interrupt source, which can be used by the programmer
to monitor the status of the 82C205.
The micro-controller can access the registers of the 82C205, the Color Look-Up Table (CLUT), and the DRAM
frame buffer. Since the internal address of the frame buffer is 22 bits wide, the 82C205 uses a bank switching
technique in order to allow the micro-controller access to the entire memory address space.
4.3. Input Source
The 82C205 supports 24-bit digital input. This 24-bit digital input port can be connected to a TV decoder, external
ADC and PanelLink™ receiver. The 82C205 can also generate its own internal test patterns and syncs that can be
used for system integration tests.
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4.4. Automatic Resolution Detection
The 82C205 monitors the horizontal and vertical syncs from the VGA and performs automatic polarity detection,
as well as determination of the horizontal sync frequency and the incoming image resolution. Changes in the
horizontal sync frequency and the input image resolution can be configured to prompt an interrupt when these
changes occur. The micro-controller can then read the system status and then re-program the 82C205
appropriately.
A fully programmable capture CRTC can be adjusted by the programmer to align with incoming data, based upon
the status information that the 82C205 provides.
4.5. TV Mode
The 82C205 chip can be used to turn the LCD monitor into a TV monitor. If the system design for the monitor
includes a TV input and NTSC/PAL decoder, then the 82C205 can enable the flat panel to display television
signals. Both 16- and 8-bit interfaces to TV decoders are supported, which offers the designer the flexibility of
using a less expensive decoder. The 82C205 requires an ODD/EVEN flag as its vertical sync, and the HREF
signal as its horizontal sync.
4.6. Full Scale and Centering Options
Scaling is always an important issue for multi-sync monitors, so the 82C205 uses high quality filters to perform
image scaling, both horizontally and vertically. Even low resolution images, such as the output from a TV decoder,
can be displayed at the full panel resolution. A “centering” option also allows for a smaller resolution image to be
displayed on a larger panel with its original resolution surrounded by a black border.
4.7. Contrast/Brightness Control
Contrast and brightness are adjusted digitally on the 82C205, with built in clamping to prevent overflow and
underflow. The contrast and brightness controls exist for each color component separately (R-G-B), so color
weighting can also be performed by adjusting the contrast of each component to give a component a certain
weight relative to the other color components.
Ro
=
Ri * ContrastR + BrightnessR
Go
=
Gi * ContrastG + BrightnessG
Bo
=
Bi * ContrastB + BrightnessB
4.8. On Screen Display
The 82C205 supports 8 color OSD. Using the attribute control of the 82C205, the programmer is able to build onscreen menus with transparency, translucency, video inversion, and blinking special effects.
The OSD region on the display is defined as a rectangular region. The rectangular region’s size and location on
the display are controlled by programmable registers, so the OSD can be of any size, and be located at any
coordinate on the display.
The micro-controller writes the bitmap data for the rectangular OSD region to a DRAM buffer. The OSD data in the
DRAM buffer contains a 4-bit index into a Color Look Up Table (CLUT) register which is internal to the 82C205
and is also programmable by the micro-controller.
The CLUT contains 16 entries each using 6 bits to describe a 3-bit RGB color value, a 2-bit attribute value to
control the overlay graphics, and a 1-bit alpha blend value to control the global alpha value or translucency of the
of the overlay graphics. Figure 3 illustrates the organization of the CLUT.
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82C205
Bit[5]
Bit[4]
Bit[3]
Bits[2:1]
Bit[0]
Red
Green
Blue
Overlay
α
Figure 3.
CLUT contents
A global alpha is defined for the entire table, and each entry is tagged with an alpha-blend flag. Inverted video,
transparent and blinking attributes are also supported in this mode.
Using the alpha blend value, the OSD graphics can be composited with the video stream controlled by a blend
factor in order to create a translucent effect. Pixels in the defined rectangular OSD region that the programmer
wishes to be “blank” graphics, i.e. the underlying video is clearly visible, can attach the “transparent” attribute to
the OSD pixel. The formula used to control alpha blending is as follows:
Output = Video * (1-α) + OSD * (α)
Attributes further expand the OSD effects, with an invert attribute (which inverts the video data) and a blink
attribute, which performs a hardware controlled blink using a programmable blink rate.
4.9. Dithering
Some flat panels do not provide a 24-bit “true color” interface, so the challenge is to achieve the effect of true color
when the panel itself supports less than a full color display. OPTi uses an advanced dithering technique which
delivers a true color effect on all display types.
4.10. Versatile Panel Support
The 82C205 is configurable to support a wide range of active matrix displays with resolutions of 640 x 480, 800 x
600, 1024 x 768, and 1280 x 1024 pixels. TFT displays with 9-, 12-, 18-, and 24-bits per pixel are supported.
82C205 also supports multiple pixels per clock and provides a 36-bit interface for panel support.
The synchronization signals to the flat panel are controlled by a fully programmable display CRTC. Positive and
negative polarity syncs are supported. In addition to the horizontal and vertical syncs, and the pixel clock for the
panel, a data ready (DE) signal is also provided for TFT displays
4.11. Clock Generation
82C205 contains two internal PLLs that are used to generate the clocks necessary for operation. In addition to
these two clocks, which control the video processing unit and the memory subsystem, the 14.318 Mhz reference
clock is also used internally. This 14.319Mhz same as the system clock for the micro-controller interface.
§
PLL2 (MCK) uses the 14.318 MHz reference clock to generate the clock for the memory controller. This clock
frequency should match the speed of the DRAM. For SDRAM, a 100 MHz clock is recommended.
§
PLL3 (VCLK2) uses the 14.318 MHz reference clock to generate the display clock for the video processing
unit. This is also the clock that will be used to drive the panel and its frequency is closely linked to the panel
specifications.
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82C205
4.12. DRAM Interface
82C205 contains an integrated memory controller that supports 64-bit SDRAM. There is also a bypass mode
available for some TFT panels that can be used to eliminate the need for a frame buffer, but at the cost of reduced
functionality, such as loss of the TV support option.
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®
5. Register Descriptions
5.1. Revision Register
7
6
5
4
Index 00h
3
2
1
0
Chip Revision (R)
Default = 00h
Chip Revision
5.2. System Control Register
7
6
5
4
Reserved
Reserved
Reserved
Index 01h
Reserved
3
2
1
0
CPU DRAM
Access:
Video Display
Control
Video Capture
Control
0: Enable
0: Disable
0: Disable
1: Disable
1: Enable
1: Enable
System Enable (R/W)
Default = 00h
Add one clock
for CPU
read/write:
0: Enable
1: Disable
Index 02h
Software Reset (R/W)
Default = 00h
These software resets allow the CPU flexibility for debug and power down functions.
The default value is zero and software reset is unnecessary at startup
Reserved
Reserved
Capture
Reset:
Display Reset:
Reserved
0: Normal
0: Normal
1: Reset
Memory
Controller
Reset:
Reserved
0: Normal
1: Reset the
timer
0: Normal
1: Reset
Timer Reset:
1: Reset
5.3. Memory Control Registers
7
6
Index 04h
5
4
3
2
Capture Start Address - Field 1 (R/W)
1
0
Default = 00h
Starting address for Video Capture Field 1 -- Low Byte
Index 05h
Default = 00h
Starting address for Video Capture Field 1 -- Middle Byte
Index 06h
Reserved
Default = 00h
Reserved
Index 07h
Starting address for Video Capture Field 1 -- High Byte
Capture Start Address - Field 2 (R/W)
Default = 00h
Starting address for Video Capture Field 2 -- Low Byte
Index 08h
Default = 00h
Starting address for Video Capture Field 2 -- Middle Byte
Index 09h
Reserved
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Default = 00h
Reserved
Starting address for Video Capture Field 2 -- High Byte
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82C205
7
6
5
4
Index 0Ah -0Ch
Index 0Dh
3
2
1
0
Reserved
Default = 00h
OSD Start Address (R/W)
Default = 00h
Starting address of OSD Index Buffer Low Byte
Index 0Eh
Default = 00h
Starting address of OSD Index Buffer Middle Byte
Index 0Fh
Default = 00h
Reserved
Reserved
Index 10h
Starting address of OSD Index Buffer High Byte
Display Panel Start Address – Field 1 (R/W)
Default = 00h
Starting address for Display buffer.
This is the starting address for field 1 of the TV or VGA data.
Low Byte
Index 11h
Default = 00h
Middle Byte
Index 12h
Default = 00h
Reserved
Reserved
Index 13h
High Byte
Display Panel Start Address – Field 2 (R/W)
Default = 00h
Starting address for Display buffer.
This is the starting address for field 2 of the TV data.
Low Byte
Index 14h
Default = 00h
Middle Byte
Index 15h
Default = 00h
Reserved
Reserved
High Byte
Index 16h
Video Pitch (R/W)
Default = 00h
Pitch of the Frame Buffer.
Low Byte
Index 17h
Default = 00h
Reserved
Reserved
Reserved
Index 18h - 19h
Index 1Ah
High Byte
Reserved
Default = 00h
OSD Pitch (R/W)
Default = 00h
Pitch of the OSD Index Buffer
Low Byte
Index 1Bh
Default = 00h
Reserved
Reserved
Index 1Ch
Reserved
High Byte
Memory Bank (R/W)
Default = 00h
Bank Address for DRAM access by CPU.
The CPU address is structured so that the resultant memory address is:
bank[7:0], cpu_addr[21:14]
Hence, each bank is 16Kbytes, with 256 available banks.
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7
6
5
4
Index 1Dh
Reserved
3
2
1
Sequencer Control (R/W)
Reserved
Arbiter Client
Acknowledge
Overlap:
Reserved
0
Default = 20h
Reserved
Reserved
Reserved
Reserved
This bit should be
set to 1 (default)
for optimal
memory
performance. It
allows for greater
throughput for
internal client
requests.
Index 1Eh
Refresh Rate Control (R/W)
Default = FFh
Number of reference clock cycles between refresh requests (f = 14.318Mhz, T = 70ns).
The duration between refresh requests should be 1/3 of the maximum refresh interval for a row.
Low Byte
Index 1Fh
Default = FFh
High Byte
Index 20h - 21h
Reserved
Index 22h
Reserved
Default = 00h
SDRAM Control 0 (R/W)
Reserved
Reserved
Reserved
Default = 00h
CAS
Latency = 3:
SDRAM Burst
Type:
0: Disable
0: Sequential
1: Enable
1: Interleave
SDRAM Burst Length:
00: Burst Length = 1
01: Burst Length = 2
10: Burst Length = 4
11: Burst Length = 8
Index 23h
Reserved
Default = 00h
Index 24h
CLUT Base Address (R/W)
Default = 01h
Reserved
Reserved
Color Look Up Table Base Address.
This 6-bit value corresponds to bits [13:8] of the micro-controller address.
Default = 1
(REGBASE should NOT be strapped to '1'.)
Index 25h
Reserved
TV Weave Mode (R/W)
Reserved
Reserved
Reserved
Reserved
Default = 00h
Reserved
Reserved
TV Weave
Mode
Capture
Pitch
Adjust:
0: Enable
1: Disable
(See note
below.)
Note: If set to '1', adjusts the Capture Pitch to twice the Video Pitch if selected in order to accommodate TV Weave mode. TV Weave mode
captures both fields of the TV image in an interleaved manner. (Sets Capture Pitch = 2 * Video Pitch.)
Index 26h
CPU Memory Read Buffer (R)
Default = 00h
CPU Memory Read Buffer Status
This register latches the CPU read data from memory and can be used by the microcontroller to perform a "double read".
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82C205
7
6
5
Index 27h
4
3
2
1
Arbiter State (R)
0
Default = 00h
This register can be used to detect a lock-up of the arbiter.
For debug purposes only.
Reserved
Reserved
Reserved
Index 28h
Arbiter State Status
Sequencer State (R)
Default = 00h
This register can be used to detect a lock-up of the memory sequencer.
For debug purposes only.
Reserved
Reserved
Reserved
Sequencer State Status
5.4. OSD Registers
7
6
5
4
Reserved
Reserved
Reserved
Index 29h
3
2
1
OSD Configuration (R/W)
Reserved
Reserved
0
Default = 00h
OSD Blink
Background
Select:
0: Blink to
Video
Background
OSD function:
Reserved
0: Disable
(default)
1: Enable
1: Blink to
CLUT
Index0
Background
Index 2Ah
OSD Window Horizontal Offset (R/W)
Default = 00h
Horizontal Offset for the rectangular OSD region referenced from the far left of the display and in units of display pixels.
Low Byte
Index 2Bh
OSD Window Horizontal Offset (R/W)
Reserved
Reserved
Reserved
Index 2Ch
Reserved
Reserved
Default = 00h
High Byte
OSD Horizontal Size (R/W)
Default = 00h
Width of rectangular OSD region in units of display pixels.
Low Byte
Index 2Dh
OSD Horizontal Size (R/W)
Reserved
Reserved
Reserved
Index 2Eh
Reserved
Reserved
Default = 00h
High Byte
OSD Window Vertical Offset (R/W)
Default = 00h
Vertical Offset for the rectangular OSD region referenced from the top of the display and in units of display lines.
Low Byte
Index 2Fh
OSD Window Vertical Offset (R/W)
Reserved
Reserved
Reserved
Index 30h
Reserved
Reserved
Default = 00h
High Byte
OSD Vertical Size (R/W)
Default = 00h
Height of rectangular OSD region in units of display lines.
Low Byte
Index 31h
OSD Vertical Size (R/W)
Reserved
Reserved
®
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Reserved
Reserved
Reserved
Default = 00h
High Byte
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82C205
7
6
5
Index 32h
4
3
2
1
0
Blink Rate for OSD (R/W)
Default = 00h
Blink Rate for On Screen Display.
Blink Rate is in units of frames. Setting the blink rate to 30 means
that the OSD will appear for 30 frames, then disappear for 30 frames.
The OSD will blink only if the blink attribute is selected
Index 33h - 37h
Reserved
Default = 00h
5.5. Dither Register Settings
7
6
5
Index 38h
4
3
2
1
0
Primary Bits (R/W)
Capture Data Bits:
Default = 00h
Reserved
(set to 0)
Bits per pixel color component for dither capture data.
Dither Line Depth Select:
For TFT:
Dither Line Depth =
(8 - Primary Bits) / 2
Index 39h
Reserved
(set to 1)
Dither Control (R/W)
Reserved
(set to 1)
Reserved
(set to 1)
Index 3Ah
Reserved
(set to 1)
Default = FAh
Reserved
(set to 2)
Reserved
(set to 2)
Dither Threshold (R/W)
Default = 00h
Adjustment of this value can reduce Moire pattern effects.
Index 3Bh
Reserved
Dither Algorithm Initializations (R/W)
Reserved
Reserved
Index 3Ch
Reserved
Reserved
Default = 03h
Reserved
Reserved
(set to 1)
Dither Frame and Line Offset (R/W)
Reserved
Reserved
(set to 1)
Default = 00h
Dither Line Offset Function Control:
This register setting depends on the values in Register
38h, the Primary Bits, and the Dither Line Depth.
8 - Primary Bits - Dither Line Depth
Index 3Dh
Reserved
Dither Mode (R/W)
Reserved
Reserved
Reserved
Index 3Eh - 3Fh
Reserved
Default = 00h
Reserved
Reserved
Reserved
Reserved
Default = 00h
5.6. Capture CRTC Registers
7
6
5
Index 40h
4
3
2
1
Capture Horizontal Sync Width (R/W)
0
Default = 00h
Capture Horizontal Sync Width (in units of VCLK1 cycles).
Low Byte
Index 41h
Reserved
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Capture Horizontal Sync Width (R/W)
Reserved
Reserved
Reserved
Default = 00h
High Byte
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7
6
5
Index 42h
4
3
2
1
Capture Horizontal Display Start (R/W)
0
Default = 00h
Counter Value that corresponds to the horizontal start location of active video during video capture (in units of VCLK1 cycles).
Low Byte
Index 43h
Capture Horizontal Display Start (R/W)
Reserved
Reserved
Reserved
Index 44h
Reserved
Default = 00h
High Byte
Capture Horizontal Display End (R/W)
Default = 00h
Counter Value that corresponds to the horizontal end location of active video during video capture (in units of VCLK1 cycles).
Low Byte
Index 45h
Capture Horizontal Display End (R/W)
Reserved
Reserved
Reserved
Index 46h
Reserved
Default = 00h
High Byte
Capture Horizontal Total (R/W)
Default = 00h
Period of the Horizontal Sync in units of VCLK1. Used when free running the internal capture horizontal sync.
Low Byte
Index 47h
Capture Horizontal Total (R/W)
Reserved
Reserved
Reserved
Index 48h
Default = 00h
High Byte
Capture Vertical Sync Start (R/W)
Default = 00h
Starting Location for Vertical Sync Pulse, i.e. counter value in units of capture video lines specifying the
delay from the start of the VGA vertical sync going active to when the internal capture vertical sync goes active.
Index 4Ah
Capture Vertical Sync End (R/W)
Default = 00h
Ending Location for Vertical Sync Pulse, i.e. counter value in units of capture video lines specifying the
delay from the start of the VGA vertical sync going active to when the internal capture vertical sync goes inactive.
Low Byte
Index 4Bh
Capture Vertical Sync End (R/W)
Reserved
Reserved
Reserved
Index 4Ch
Reserved
Default = 00h
High Byte
Capture Vertical Display Start (R/W)
Default = 00h
Counter Value that corresponds to the vertical start location of active video in units of capture video lines.
Low Byte
Index 4Dh
Capture Vertical Display Start (R/W)
Reserved
Reserved
Reserved
Index 4Eh
Reserved
Default = 00h
High Byte
Capture Vertical Display End (R/W)
Default = 00h
Counter Value that corresponds to the vertical end location of active video in units of capture video lines.
Low Byte
Index 4Fh
Capture Vertical Display End (R/W)
Reserved
Reserved
Reserved
Index 50h
Reserved
Default = 00h
High Byte
Capture Vertical Total (R/W)
Default = 00h
Period of Vertical Sync in units of capture video lines. Used when free running the internal capture vertical sync.
Low Byte
Index 51h
Capture Vertical Total (R/W)
Reserved
Reserved
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Reserved
Reserved
Default = 00h
High Byte
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82C205
7
6
5
4
Index 52h
Reserved
3
2
1
Synchronization Control (R/W)
Reserved
VGA Vertical
Sync:
0: Sync
present
1: Sync lost
(Read only)
VGA
Horizontal
Sync
VGA Vertical
Sync Input
Polarity:
0: Sync
present
0: Positive
1: Negative
1: Sync lost
(Read only)
(Read only)
Index 53h
0
Default = 03h
VGA
Horizontal
Sync Input
Polarity:
0: Positive
1: Negative
(Read only)
Synchronize to
Vertical Sync:
0: Free run the
internal
vertical
sync:
1: Synchronize
to external
vertical
sync.
Reserved
Synchronize to
Horizontal
Sync:
0: Free run the
internal
horizontal
sync:
1: Synchronize
to external
horizontal
sync.
Default = 00h
5.7. Scaling Registers
7
6
5
4
Index 54h
3
2
1
Vertical Scale Ratio (R/W)
0
Default = 00h
Vertical Scale Ratio for Vertical Decimation:
This value is determined by the following formula, where Capture Ysize is the number
of lines in the incoming video frame and Display Ysize is the number of lines in the panel:
If Capture Ysize < Display Ysize, then
Yratio = (Capture Ysize * 1024) / Display Ysize.
Otherwise,
Yratio = (((Display Ysize * 2048) / Capture Ysize) + 1 ) / 2.
Low Byte
Index 55h
Reserved
Vertical Scale Ratio (R/W)
Reserved
Reserved
Index 56h
Reserved
Reserved
Default = 00h
High Byte
Input Y Size (R/W)
Default = 00h
Number of lines per frame in the incoming image
Low Byte
Index 57h
Reserved
Input Y Size (R/W)
Reserved
Reserved
Index 58h
Reserved
Reserved
Default = 00h
High Byte
Output Y Size (R/W)
Default = 00h
Number of lines per frame in the displayed image (after scaling)
Low Byte
Index 59h
Reserved
Output Y Size (R/W)
Reserved
Index 5Ah
Reserved
Reserved
Reserved
Default = 00h
High Byte
Vertical Scale-Down Random DDA Initialization (R/W)
Default = 00h
Maximum random initialization value for Vertical scale down DDA
(Disable with 01h)
Low Byte
Index 5Bh
Reserved
912-1000-024
Revision 1.0
Vertical Scale-Down Random DDA Initialization (R/W)
Reserved
Reserved
Reserved
Reserved
Default = 00h
High Byte
®
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7
6
Index 5Ch
5
4
3
2
1
Vertical Scale-Up Random DDA Initialization (R/W)
0
Default = 00h
Maximum random initialization value for Vertical scale up DDA
Low Byte
Index 5Dh
Vertical Scale-Up Random DDA Initialization (R/W)
Reserved
Reserved
Reserved
Reserved
Seed Sign Bit:
(Adds
randomness to
vertical scale
up.)
Default = 00h
High Byte (for Maximum random initialization for
Vertical scale up DDA)
0: DDA init
value is an
unsigned
number.
1: DDA init
value is a
signed
number.
Index 5Eh
Vertical Scale-Up Mid Point Selection (R/W)
Reserved
Reserved
Reserved
Reserved
Index 5Fh
Index 60h
Reserved
Default = 02h
TV Mode Even
Field:
DDA Field
Compensation:
0: Select DDA
Reference
0: Reverse
0: Disable
1: Normal
1: Enable
1: Select MidPoint
Reference
Reserved
Default = 00h
Horizontal Scale Ratio (R/W)
Default = 00h
Horizontal Scale Ratio for Decimation
This value is determined by the following formula, where Capture Xsize is the number of pixels per
line in the incoming video frame and Display Xsize is the number of pixels per line in the panel:
If Capture Xsize > Display Xsize then
Xratio = (((Display Xsize * 8192) / Capture Xsize) + 1) / 2
Otherwise,
Xratio = 4096
Low Byte
Index 61h
Horizontal Scale Ratio (R/W)
Reserved
Reserved
Reserved
Index 62h
Default = 00h
High Byte
Output X Size (R/W)
Default = 00h
Number of Pixels in a line of the displayed image (after scaling).
Low Byte
Index 63h
Output X Size (R/W)
Reserved
Reserved
Reserved
Index 64h
Reserved
Reserved
Default = 00h
High Byte
Input X Size (R/W)
Default = 00h
Number of Pixels per line in incoming image (before scaling).
Low Byte
Index 65h
Input X Size (R/W)
Reserved
Reserved
Index 66h
Reserved
Reserved
Horizontal Scale-Down Random DDA Initialization (R/W)
®
Page 26
Reserved
Default = 00h
High Byte
Default = 00h
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Revision 1.0
Advance Information
82C205
7
6
5
4
3
2
1
0
Maximum Random Initialization Value for Horizontal Scale Down DDA
Low Byte
Index 67h
Reserved
Horizontal Scale-Down Random DDA Initialization (R/W)
Reserved
Reserved
Reserved
Reserved
Default = 00h
High Byte
5.8. Contrast and Brightness Control Registers
7
6
5
Index 68h
4
3
2
1
Red Contrast Control (R/W)
0
Default = 80h
Red contrast level (0 to 255)
Note: 128 is unity
Index 69h
Green Contrast Control (R/W)
Default = 80h
Green contrast level (0 to 255)
Note: 128 is unity
Index 6Ah
Blue Contrast Control (R/W)
Default = 80h
Blue contrast level (0 to 255)
Note: 128 is unity
Index 6Bh
Red Brightness Control (R/W)
Default = 00h
Red brightness level (-128 to 127)
Index 6Ch
Green Brightness Control (R/W)
Default = 00h
Green brightness level (-128 to 127)
Index 6Dh
Blue Brightness Control (R/W)
Default = 00h
Blue brightness level (-128 to 127)
5.9. Video Input Source Selection Registers
7
6
5
4
Reserved
Reserved
Reserved
Index 6Eh
Reserved
3
2
1
0
Reserved
Reserved
Anti-Alias PreFilter
Operation:
Anti-Alias Pre-Filter (R/W)
Reserved
Default = 00h
0: Enable
1: Disable
NOTE: Enable
for VGA scale
down only.
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®
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Advance Information
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7
6
5
Index 6Fh
4
3
2
1
Video Input Source Selection (R/W)
Reserved
Reserved
Reserved
Overlay grid
dots on input
pattern:
0
Default = 00h
Video Input Source Select. Video sources can be from the A/D
converters or a test pattern generator:
0000: Reserved
0: disable
(default)
0001: Black color pattern
0010: White color pattern
1: enable
0011: Grey color pattern
0100: Red color pattern
0101: Green color pattern
0110: Blue color pattern
0111: Horizontal ramp pattern
1000: Horizontal line pattern
1001: Vertical ramp pattern
1010: Vertical line pattern
1011: Alternating block scan patterns
1100: B/W checker board pattern
1101: G&P checker board pattern
1110: Color bar pattern
1111: 4 corner blend pattern
5.10. Resolution Detection Registers
7
6
5
Index 70h
4
3
2
1
Resolution Counter (R)
0
Default = 00h
Counter for number of VGA horizontal syncs in a frame (in units of capture video lines).
Low Byte
Index 71h
Resolution Counter (R)
Default = 00h
High Byte
Index 72h
Horizontal Frequency Counter (R)
Default = 00h
Counter for period of VGA horizontal sync (in units of reference clock).
Reference clock frequency is 14.318 MHz
Low Byte
Index 73h
Horizontal Frequency Counter (R)
Default = 00h
High Byte
Index 74h
Active Video Top Edge (R)
Default = 00h
The line number of the first line which contains active VGA data after Vertical Sync.
Low Byte
Index 75h
Active Video Top Edge (R)
Reserved
Reserved
®
Page 28
Reserved
Reserved
Default = 00h
High Byte
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Advance Information
82C205
7
6
5
Index 76h
4
3
2
1
Active Video Bottom Edge (R)
0
Default = 00h
The line number of the last line which contains active VGA data after Vertical Sync.
Low Byte
Index 77h
Reserved
Active Video Bottom Edge (R)
Reserved
Reserved
Index 78h
Default = 00h
Reserved
High Byte
Active Video Left Edge (R)
Default = 00h
The first horizontal position that contains active VGA data after Horizontal Sync.
Low Byte
Index 79h
Reserved
Active Video Left Edge (R)
Reserved
Reserved
Index 7Ah
Default = 00h
High Byte
Active Video Right Edge (R)
Default = 00h
The last horizontal position that contains active VGA data after Horizontal Sync.
Low Byte
Index 7Bh
Reserved
Active Video Right Edge (R)
Reserved
Reserved
Default = 00h
High Byte
5.11. TV Decoder Interface Registers
7
6
5
Index 7Ch
Reserved
4
3
2
TV Mode (R/W)
Reserved
Reserved
Reserved
Index 7Dh
Phase Counter Offset:
NTSC
Decoder data
bus width:
Reserved
Reserved
Reserved
Input Mode:
0: 16-bit
(default)
0: VGA or test
pattern
input
(default)
1: 8-bit
1: TV input
Odd/Even Flag
Polarity:
HREF polarity:
TV Sync Polarity Adjustment (R/W)
Reserved
0
Default = 00h
These bits are used to adjust
the lumninance and
chrominance phase offset.
Reserved
1
Default = 00h
Reserved
0: Positive
(typical)
0: Positive
1: Negative
(typical)
1: Negative
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5.12. Display Horizontal Scaling
7
6
5
4
Index 7Eh
3
2
1
Horizontal Scale X Ratio 1 (R/W)
0
Default = 00h
Horizontal Scale x Ratio 1
Index 7Fh
Horizontal Scale X Ratio 2 (R/W)
Horizontal
Scale-Up:
Reserved
Default = 00h
Horizontal Scale x Ratio 2
0: Enable
1: Disable
5.13. Display CRTC Registers
7
6
5
4
Index 80h
3
2
1
Display Horizontal Total (R/W)
0
Default = 00h
Horizontal Total (in units of VCLK2)
Low Byte
Index 81h
Display Horizontal Total (R/W)
Reserved
Reserved
Reserved
Index 82h
Reserved
Default = 00h
High Byte
Display Horizontal Sync Width (R/W)
Default = 00h
Horizontal Sync Width (in units of VCLK2)
Low Byte
Index 83h
Display Horizontal Sync Width (R/W)
Reserved
Reserved
Reserved
Index 84h
Reserved
Default = 00h
High Byte
Display Horizontal Display Start (R/W)
Default = 00h
Horizontal Display Start Location (in units of VCLK2)
Low Byte
Index 85h
Display Horizontal Display Start (R/W)
Reserved
Reserved
Reserved
Index 86h
Reserved
Default = 00h
High Byte
Display Horizontal Display End (R/W)
Default = 00h
Horizontal Display End Location (in units of VCLK2)
Low Byte
Index 87h
Display Horizontal Display End (R/W)
Reserved
Reserved
Reserved
Index 88h
Reserved
Default = 00h
High Byte
Display Vertical Total - Odd Frame (R/W)
Default = 00h
Vertical Total for Odd Frame (in units of display video lines).
Low Byte
Index 89h
Display Vertical Total - Odd Frame (R/W)
Reserved
Reserved
®
Page 30
Reserved
Reserved
Default = 00h
High Byte
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82C205
7
6
5
4
Index 8Ah
3
2
1
Display Vertical Total - Even Frame (R/W)
0
Default = 00h
Vertical Total for Even Frame (in units of display video lines).
If odd and even frames have the same vertical total,
this register still needs to be programmed.
Low Byte
Index 8Bh
Reserved
Display Vertical Total - Even Frame (R/W)
Reserved
Reserved
Index 8Ch
Reserved
Default = 00h
High Byte
Display Vertical Sync Width (R/W)
Default = 00h
Vertical Sync Width (in units of display video lines)
Low Byte
Index 8Dh
Reserved
Display Vertical Sync Width (R/W)
Reserved
Reserved
Index 8Eh
Reserved
Default = 00h
High Byte
Display Vertical Display Start (R/W)
Default = 00h
Vertical Display Start (in units of display video lines)
Low Byte
Index 8Fh
Reserved
Display Vertical Display Start (R/W)
Reserved
Reserved
Index 90h
Reserved
Default = 00h
High Byte
Display Vertical Display End (R/W)
Default = 00h
Vertical Display End (in units of display video lines)
Low Byte
Index 91h
Reserved
Display Vertical Display End (R/W)
Reserved
Reserved
Index 92h
Reserved
Default = 00h
High Byte
Vertical Sync Signal Offset Control (R/W)
Default = 05h
Defines the delay in units of capture video lines, from the rising edge of
the capture vertical sync to the rising edge of the display vertical sync
Low Byte
Index 93h
Reserved
Vertical Sync Signal Offset Control (R/W)
Reserved
Reserved
Index 94h
Reserved
High Byte
Bypass Mode HSYNC Offset (R/W)
Reserved
Index 95h
Default = 00h
Default = 06h
High Byte
Bypass Mode HSYNC Offset (R/W)
Default = 0Ah
Defines the delay in units of VCLK2 display HSYNC to capture HSYNC in bypass mode.
Low Byte
Index 96h
912-1000-024
Revision 1.0
Reserved
Default = 00h
®
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7
6
5
4
Index 97h
3
2
1
Synchronization Control (R/W)
Reserved
Reserved
Index 98h
Reserved
Reserved
0
Default = 03h
Reserved
Reserved
0: Free run
display
vertical
sync.
0: Free run
display
horizontal
sync.
1: Synchronize
display
vertical
sync to
capture
vertical
sync.
1: Synchronize
display
horizontal
sync to
capture
horizontal
sync.
Panel Display Window Horizontal Start (R/W)
Default = 00h
Horizontal Start of Panel Display Window (in units of VCLK2)
Low Byte
Index 99h
Panel Display Window Horizontal Start (R/W)
Reserved
Reserved
Reserved
Reserved
Default = 00h
Horizontal Start of Panel Display Window (in units of VCLK2)
High Byte
Index 9Ah
Panel Display Window Horizontal End (R/W)
Default = 00h
Horizontal End of Panel Display Window (in units of VCLK2)
Low Byte
Index 9Bh
Panel Display Window Horizontal End (R/W)
Reserved
Reserved
Reserved
Reserved
Default = 00h
Horizontal End of Panel Display Window (in units of VCLK2)
High Byte
Index 9Ch
Panel Display Window Vertical Start (R/W)
Default = 00h
Vertical Start of Panel Display Window (in units of display video lines)
Low Byte
Index 9Dh
Panel Display Window Vertical Start (R/W)
Reserved
Reserved
Reserved
Reserved
Default = 00h
Vertical Start of Panel Display Window
(in units of display display video lines)
High Byte
Index 9Eh
Panel Display Window Vertical End (R/W)
Default = 00h
Vertical End of Panel Display Window (in units of display video lines)
Low Byte
Index 9Fh
Panel Display Window Vertical End (R/W)
Reserved
Reserved
Reserved
Reserved
Default = 00h
Vertical End of Panel Display Window
(in units of display video lines)
High Byte
®
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5.14. Panel Registers
7
6
5
Index A0h
Reserved
4
3
2
1
Panel Type (R)
Reserved
Reserved
Reserved
0
Default = 00h
Panel Type. Nomenclature according to FPDI standards:
0000: Reserved
0001: Reserved
0010: Reserved
0011: Reserved
0100: A333-S09
0101: A444-S12
0110: A666-S18
0111: A888-S24
1000: A333-S18
1001: A444-S24
1010: A666-S36
1011: Reserved
Index A1h
Reserved
Panel Sync Signal Control (R/W)
Reserved
Reserved
Reserved
Selects an
FPS Gated by
the valid data
region.
0: Data
changes at
rising edge
of FPSHIFT
0: Continuous
FPS (TFT)
1: Data
changes at
falling edge
of FPSHIFT
Index A2h - A3h
Index A4h
Reserved
Reserved
Reserved
Default = 00h
Selects where
data changes
relative to
FPSHIFT:
Flat Panel
Frame signal
polarity:
Flat Panel
Line signal
polarity:
0: Active high
(default)
0: Active high
(default)
1: Active low
1: Active low
1: Gate FPS
by Valid
Data
Region (not
used)
Reserved
Default = 00h
Memory Bypass Mode (R/W)
Default = 00h
Reserved
Reserved
Reserved
Reserved
Memory
Bypass:
0: Use
external
DRAM
(Default)
1: Bypass
DRAM
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5.15. Bandwidth Conservation Registers
7
6
5
4
Index B0h
3
2
1
OSD FIFO Word Count (R/W)
0
Default = 00h
Special register for OSD FIFO control, indicating the number of 64-bit words that will be fetched in one line for OSD.
Index B1h
Reserved
Default = 00h
Index B2h
Panel Display FIFO Word Count (R/W)
Default = 00h
Special register for upper display FIFO control, indicating the number of words that will be fetched for the whole panel.
Index B3h
Reserved
Default = 00h
5.16. Interrupt Control Registers
7
6
5
Index B4h
4
3
2
1
Interrupt Enable (R/W)
VGA
Horizontal
Frequency
Change
interrupt:
0: Disable
(default)
Display VBI
start interrupt:
Display VBI
end interrupt:
Capture VBI
start interrupt:
Capture VBI
end interrupt;
0: Disable
(default)
0: Disable
(default)
0: Disable
(default)
0: Disable
(default)
1: Enable
1: Enable
1: Enable
1: Enable
0
Default = 00h
VGA Vertical
Frequency
Change
interrupt:
0: Disable
(default)
Timer
interrupt:
Reserved
0: Disable
(default)
1: Enable
1: Enable
1: Enable
Index B5h
Interrupt Clear (W)
VGA
Horizontal
Frequency
Change
interrupt clear:
Display VBI
start interrupt
clear:
Display VBI
end interrupt
clear:
Capture VBI
start interrupt
clear:
Capture VBI
end interrupt
clear:
Write 1 to
clear
Write 1 to
clear
Write 1 to
clear
Write 1 to
clear
Write 1 to
clear
Index B5h
Timer interrupt
clear:
®
Display VBI
start event
status:
Display VBI
end event
status:
Capture VBI
start event
status:
Capture VBI
end event
status:
Occurs at
beginning of
display vertical
sync pulse.
Occurs at end
of display
vertical sync
pulse.
Occurs at
beginning of
capture
vertical sync
pulse.
Occurs at end
of capture
vertical sync
pulse.
Reserved
Write 1 to
clear
Write 1 to
clear
Interrupt Status (R)
VGA
Horizontal
Frequency
Change event
status
Page 34
Default = 00h
VGA Vertical
Frequency
Change
interrupt clear:
Default = 00h
VGA Vertical
Frequency
Change event
status
Timer event
status:
Reserved
Occurs when
count-down
timer reaches
zero.
912-1000-024
Revision 1.0
Advance Information
82C205
5.17. CLUT Access Control
7
6
5
4
Index B6h -B7h
3
2
1
Reserved
0
Default = 00h
5.18. ADC and PLL Control Registers
7
6
5
4
Index B8h C2h
Index C3h
3
2
1
0
Reserved
Default = 00h
VCLK1 Phase Offset (R/W)
Default = 09h
Reserved
Phase offset for VCLK1
Index C4h
MCLK PLL Control (R/W)
Default = 02h
14.318 Mhz reference clock * N/M = MCLK frequency
Divide MCLK
PLL output
frequency by 2
(If enabled,
the output of
the MCLK PLL
will be divided
by 2):
MCLK PLL M Factor (M[5:0])
0: Disable
1: Enable
Index C5h
MCLK PLL Control (R/W)
Reserved
Default = 09h
MCLK PLL N Factor (N[6:0])
Index C6h
VCLK2 PLL Control (R/W)
Default = 02h
14.318 Mhz reference clock * N/M = VCLK2 frequency
Divide VCLK2
PLL output
frequency by
2:
VCLK2 PLL M Factor (M[5:0])
0: Disable
1: Enable
Index C7h
VCLK2 PLL Control (R/W)
Default = 03h
VCLK2 PLL N Factor (N[6:0])
5.19. Power Management Registers
7
6
5
4
Index C8h
3
2
1
Power Enables for Panel Voltages (R/W)
0
Default = 00h
This power up/down sequencing is very important.
Improper sequencing can cause panel damage!
These signals default to zero at reset, i.e. inactive.
Reserved
912-1000-024
Revision 1.0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
®
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7
6
5
Index C9h
4
3
2
1
0
Hardware Enables (R/W)
Default = 00h
Control of Wake-up and Power Down for Power Conservation in the 82C200.
Master Bias
Reserved (set
to 0)
0: Disable
Reserved
1: Enable
Line Buffer
Power
VCLK2 PLL
Power
MCK PLL
Power
0: Disable
0: Disable
0: Disable
1: Enable
1: Enable
1: Enable
Index CAh
Reserved (set
to 0)
Timer (R/W)
Reserved
Default = FFh
General Purpose Count Down Timer (in units of 10 us) to assist the software power sequencing.
Generates a timer event whenever it reaches zero. Range from 0~5s.
The low byte should be written last, i.e. write the high and mid bytes before the low byte.
Low Byte
Index CBh
Timer (R/W)
Default = FFh
Mid Byte
Index CCh
Timer (R/W)
Reserved
Reserved
Reserved
Reserved
Default = 07h
Reserved
High Byte
The high byte should be written first,
before writing the mid and low bytes
Index CDh - CEh
Reserved
Default = 00h
5.20. CLUT Registers
This is the Color Look Up Table used for the OSD, providing 8 colors available to 16 entries. A global alpha blend
value is defined for all blending in this mode, and a 1-bit value for each entry selects whether or not the blend will
occur.
Transparent, inverted video, and blinking attributes are also supported.
In the CLUT registers D0h - DFh, the Global Blend Enable and attribute bits (bits 5, 1:0) work together as follows:
000: Normal
X01: Inverted Video
010: Blink, no blend
X11: Transparent
100: Blend
110: Blink, blend
7
6
5
Index CFh
4
3
2
CLUT Register Control (R/W)
Reserved
Reserved
Enable CLUT
registers
Default = 00h
Global blend value
CLUT0 (R/W)
Reserved
Global Blend:
0
Can be used in place of the Attribute to define a global value for pixel translucency.
Index D0h
Reserved
1
Red
Green
Default = 00h
Blue
Attribute
0: Disable
1: Enable
®
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7
6
5
4
3
Index D1h
Reserved
2
CLUT1 (R/W)
Reserved
Global Blend:
Red
Green
1
0
Default = 00h
Blue
Attribute
0: Disable
1: Enable
Index D2h
Reserved
CLUT2 (R/W)
Reserved
Global Blend:
Red
Green
Default = 00h
Blue
Attribute
Blue
Attribute
Blue
Attribute
Blue
Attribute
Blue
Attribute
Blue
Attribute
0: Disable
1: Enable
Index D3h
Reserved
CLUT3 (R/W)
Reserved
Global Blend:
Red
Green
Default = 00h
0: Disable
1: Enable
Index D4h
Reserved
CLUT4 (R/W)
Reserved
Global Blend:
Red
Green
Default = 00h
0: Disable
1: Enable
Index D5h
Reserved
CLUT5 (R/W)
Reserved
Global Blend:
Red
Green
Default = 00h
0: Disable
1: Enable
Index D6h
Reserved
CLUT6 (R/W)
Reserved
Global Blend:
Red
Green
Default = 00h
0: Disable
1: Enable
Index D7h
Reserved
CLUT7 (R/W)
Reserved
Global Blend:
Red
Green
Default = 00h
0: Disable
1: Enable
Index D8h
Reserved
CLUT8 (R/W)
Reserved
Global Blend:
Red
Green
Default = 00h
Blue
Attribute
0: Disable
1: Enable
Index D9h
Reserved
CLUT9 (R/W)
Reserved
Global Blend:
Red
Green
Default = 00h
Blue
Attribute
0: Disable
1: Enable
Index DAh
Reserved
CLUTA (R/W)
Reserved
Global Blend:
Red
Green
Default = 00h
Blue
Attribute
0: Disable
1: Enable
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®
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Advance Information
82C205
7
6
5
4
Index DBh
3
2
1
CLUTB (R/W)
Reserved
Reserved
Global Blend:
Red
0
Default = 00h
Green
Blue
Attribute
0: Disable
1: Enable
Index DCh
CLUTC (R/W)
Reserved
Reserved
Global Blend:
Red
Default = 00h
Green
Blue
Attribute
Blue
Attribute
Blue
Attribute
Blue
Attribute
0: Disable
1: Enable
Index DDh
CLUTD (R/W)
Reserved
Reserved
Global Blend:
Red
Default = 00h
Green
0: Disable
1: Enable
Index DEh
CLUTE (R/W)
Reserved
Reserved
Global Blend:
Red
Default = 00h
Green
0: Disable
1: Enable
Index DFh
CLUTF (R/W)
Reserved
Reserved
Global Blend:
Red
Default = 00h
Green
0: Disable
1: Enable
Index E0h - E8h
Reserved
Default = 00h
5.21. Status Registers
7
6
5
4
Reserved
Reserved
Reserved
Index E9h
2
1
Reserved
Reserved
Reserved
Reserved
Clear FIFO Error (R/W)
Reserved
Index EAh
Reserved
Reserved
OSD FIFO
overflow:
OSD FIFO
underflow:
0: Normal
operation
0: Normal
operation
1: Overflow
1: Underflow
Index EBh
Reserved
Reserved
®
Capture FIFO
overflow
Capture FIFO
underflow
Display upper
FIFO overflow
Writes 1 to
clear all the
error flags.
Write 0 to
resume
normal
operation.
Default = 00h
FIFO Status – Byte 2 (R)
Reserved
0
Default = 00h
FIFO Status – Byte 1 (R)
Reserved
Page 38
3
Reserved
Default = 00h
Display upper
FIFO
underflow
Reserved
Reserved
912-1000-024
Revision 1.0
Advance Information
82C205
7
6
5
Index Ech
4
3
2
1
Capture Signature – Byte 1 (R)
0
Default = 00h
Capture Signature
Signature analyzer output on video capture data stream (used for testing).
Low Byte
Index EDh
Capture Signature – Byte 2 (R)
Default = 00h
High Byte
Index EEh
Display Signature – Byte 1 (R)
Default = 00h
Display Signature
Signature analyzer output on video display data stream (used for testing).
Low Byte
Index EFh
Display Signature – Byte 2 (R)
Default = 00h
High Byte
Index F0-FBh
Reserved
Default = 00h
5.22. I/O Control Registers
7
6
5
Index FCh
4
3
2
Clock Control (R/W)
Display Sync
Bi-direction
control:
Capture Sync
Bi-direction
control:
0: Input
0: Input
1: Output
1: Output
Reserved
Reserved
Memory Clock
Source
Selection:
Reserved
0: External
oscillator
(default)
Index FDh
VCLK1
External Clock
Input Invert
Selection:
Reserved
Reserved
Reserved
Reserved
0: No invertion
(default)
1: Invert
VCLK1
RGB Data Input Selection (R/W)
Reserved
0
Default = 00h
1: Internal PLL
Reserved
1
Default = 00h
Pull Down
Function for
Bi-directional
Buffer:
Reserved
(set to 1)
Reserved
(set to 1)
0: Disable
1: Enable
912-1000-024
Revision 1.0
®
Page 39
Advance Information
82C205
®
6. Timing Information and Waveforms
Signal
Max
Unit
0
4095
Lines
t1
0
4095
Lines
Vertical Display Start
t2
0
4095
Lines
Vertical Display End
t3
0
4095
Lines
Horizontal Total
t5
0
4095
Pixel Clock
Sync Width
t6
0
4095
Pixel Clock
Horizontal Display Start
t7
0
4095
Pixel Clock
Horizontal Display End
t8
0
4095
Pixel Clock
DE
Data Valid
t10
0
4095
Pixel Clock
FPSHIFT
Pixel Clock Frequency
t11
10
120
MHz
FPFRAME
FPLINE
Description
Symbol
Min
Vertical Total
t0
Sync Width
Typical
6.1. Vertical Timing for TFT Panel
t0
t1
FPFRAME
FPLINE
DE (DRDY)
t2
DATA
t3
912-1000-024
Revision 1.0
Page 40
Advance Information
82C205
6.2. Horizontal Timing for TFT Panel
t5
t6
FPLINE
t7
DE (DRDY)
…
DATA
t8
6.3. Detail of Pixel Clock Timing
t10
DE (DRDY)
t11
FPSHIFT
DATA
* Polarity of FPFRAME, FPLINE, & FPSHIFT is programmable.
* One and Two Pixels Per Clock are supported.
6.4. Micro-Controller Interface
PSEN#
ALE#
AD[15:0]
Addr[15:0]
Data[7:0]
Addr[15:0]
WR#
RD#
INT#
912-1000-024
Revision 1.0
®
Page 41
®
Advance Information
82C205
7. 208-Pin PQFP Mechanical Drawing
912-1000-024
Revision 1.0
Page 47