ETC A54SX32

v 2 .0
54SX Family FPGAs
RadTolerant and HiRel
Hig h D ens it y De vi ces
Fe a t ur es
• 16,000 and 32,000 Available Logic Gates
Rad To ler ant 54S X Fam i ly
• Tested Total Ionizing Dose (TID) Survivability Level
• Up to 228 User I/Os
• Radiation Performance to 100Krads (Si) (ICC Standby
Parametric)
• Up to 1,080 Dedicated Flip-Flops
• Devices Available from Tested Pedigreed Lots
• Non-Volatile, User Programmable
• Up to 160 MHz On-Chip Performance
• Offered as Class B and E-Flow (Actel Space Level Flow)
• Highly Predictable Performance with 100% Automatic
Place and Route
• QMl Certified Devices
• 100% Resource Utilization with 100% Pin Locking
H iR el 5 4 S X F a m i ly
• Mixed Voltage Support—3.3V Operation with 5.0V Input
Tolerance for Low Power Operation
• Fastest HiRel FPGA Family Available
E asy L ogi c In teg ra ti on
• JTAG Boundary Scan Testing in Compliance with IEEE
Standard 1149.1
• Up to 240 MHz On-Chip Performance
• Low Cost Prototyping Vehicle for RadTolerant Devices
• Offered as Commercial or Military Temperature Tested
and Class B
• Cost Effective QML MIL-Temp Plastic Packaging Options
• Standard Hermetic Packaging Offerings
• QML Certified Devices
• Secure Programming Technology Prevents Reverse
Engineering and Design Theft
• Permanently Programmed for Operation on Power-Up
• Unique In-System Diagnostic and Debug Facility with
Silicon Explorer
• Supported by Actel’s Designer Series and DeskTOP Series
Development Systems with Automatic Timing Driven
Place and Route
• Predictable, Reliable, and Permanent Antifuse Technology
Performance
SX P r o du ct Pr of i l e
Device
RT54SX16
A54SX16
RT54SX32
A54SX32
Capacity
System Gates
Logic Gates
24,000
16,000
24,000
16,000
48,000
32,000
48,000
32,000
Logic Modules
1,452
1,452
2,880
2,880
Register Cells
528
528
1,080
1,080
Combinatorial Cells
924
924
1,800
1,800
User I/Os (Maximum)
179
180
227
228
JTAG
Yes
Yes
Yes
Yes
208, 256
208, 256
208, 256
208, 256
Packages (by pin count)
CQFP
March 2001
© 2001 Actel Corporation
1
5 4 SX F a m ily F PG A s R a d To l e r a n t a n d Hi R e l
O r d e r i n g I nf o r m a t i o n
RT54SX32
–
CQ
1
256
B
Application (Temperature Range)
Blank = Commercial (0 to +70°C)
M = Military (–55 to +125°C)
B = MIL-STD-883
E = E-Flow (Actel Space Level Flow)
Package Lead Count
Package Type
CQ = Ceramic Quad Flat Pack
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% Faster than Standard
Part Number
A54SX16= 16,000 Gates
A54SX32= 32,000 Gates
RT54SX16=16,000 Gates—RadTolerant
RT54SX32=32,000 Gates—Rad Tolerant
Pr od uc t P l a n
Speed Grade
Application
Std
–1*
C
M
B
E
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
—
—
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
RT54SX16 Devices
208-Pin Ceramic Quad Flat Pack (CQFP)
256-Pin Ceramic Quad Flat Pack (CQFP)
A54SX16 Devices
208-Pin Ceramic Quad Flat Pack (CQFP)
256-Pin Ceramic Quad Flat Pack (CQFP)
RT54SX32 Devices
208-Pin Ceramic Quad Flat Pack (CQFP)
256-Pin Ceramic Quad Flat Pack (CQFP)
A54SX32 Devices
208-Pin Ceramic Quad Flat Pack (CQFP)
✔
✔
✔
✔
✔
—
256-Pin Ceramic Quad Flat Pack (CQFP)
✔
✔
✔
✔
✔
—
Contact your Actel sales representative for product availability.
Applications:
C = Commercial
Availability: ✔
= Available
* Speed Grade: –1 = Approx. 15% Faster than Standard
M = Military
P
= Planned
B = MIL-STD-883
—
= Not Planned
E = E-flow (Actel Space Level Flow)
C er a m i c De v i ce R es ou r c es
User I/Os
Device
CQFP 208-Pin
CQFP 256-Pin
RT54SX16
174
179
A54SX16
175
180
RT54SX32
173
227
A54SX32
174
228
Package Definitions: CQFP = Ceramic Quad Flat Pack
(Contact your Actel sales representative for product availability.)
2
v2.0
5 4 SX F a m ily F P GA s R a d T o le r a n t a n d H iR e l
G en er al D e sc r i p t i on
Actel’s RadTolerant (RT) and HiRel versions of the SX
Family of FPGAs offer all of these advantages for
applications such as commercial and military satellites,
deep space probes, and all types of military and high
reliability equipment.
radiation effects is both device and lot dependent. The
customer must evaluate and determine the applicability of
these devices to their specific design and environmental
requirements.
The RT and HiRel versions are fully pin compatible allowing
designs to migrate across different applications that may or
may not have radiation requirements. Also, the HiRel
devices can be used as a low cost prototyping tool for RT
designs.
Actel will provide total dose radiation testing along with the
test data on each pedigreed lot that is available for sale.
These reports are available on our website or you can
contact your local sales representative to receive a copy. A
listing of available lots and devices will also be provided.
These results are only provided for reference and for
customer information.
The programmable architecture of these devices offer high
performance, design flexibility, and fast and inexpensive
prototyping—all without the expense of test vectors, NRE
charges, long lead times, and schedule and cost penalties
for design modifications that are required by ASIC devices.
For a radiation performance summary, see Radiation
Performance of Actel Products at http://www.actel.com/hirel.
This summary will also show single event upset (SEU) and single
event latch-up (SEL) testing that has been performed on Actel
FPGAs.
Dev ic e D es cri pt io n
The RT54SX16 and A54SX16 devices have 16,000 available
gates and up to 179 I/Os. The RT54SX32 and A54SX32 have
32,000 available gates and up to 228 I/Os. All of these
devices support JTAG boundary scan testability.
All of these devices are available in Ceramic Quad Flat Pack
(CQFP) packaging, with 208-pin and 256-pin versions. The
256-pin version offers the user the highest I/O capability,
while the 208-pin version offers pin compatibility with the
commercial Plastic Quad Flat Pack (PQFP-208). This
compatibility allows the user to prototype using the very low
cost plastic package and then switch to the ceramic
package for production. For more information on plastic
packages, refer to the SX family FPGAs data sheet at:
http://www.actel.com/docs/datasheets/A54SXDS.pdf
The A54SX16 and A54SX32 are manufactured using a 0.35µ
technology at the Chartered Semiconductor facility in
Singapore. These devices offer the highest speed
performance available in FPGAs today.
The RT54SX16 and RT54SX32 are manufactured using a
0.6µ technology at the Matsushita (MEC) facility in Japan.
These devices offer levels of radiation survivability far in
excess of typical CMOS devices.
R ad i at i on Su r v i va bi l i t y
Total dose results are summarized in two ways. First by the
maximum total dose level that is reached when the parts
fail to meet a device specification but remain functional.
For Actel FPGAs, the parameter that exceeds the
specification first is ICC, the standby supply current. Second
by the maximum total dose that is reached prior to the
functional failure of the device.
Q M L C e rti f i c at i on
Actel has achieved full QML certification, demonstrating
that quality management, procedures, processes, and
controls are in place and comply with MIL-PRF-38535, the
performance specification used by the Department of
Defense for monolithic integrated circuits.
QML
certification is a good example of Actel's commitment to
supplying the highest quality products for all types of
high-reliability, military and space applications.
Many suppliers of microelectronics components have
implemented QML as their primary worldwide business
system. Appropriate use of this system not only helps in the
implementation of advanced technologies, but also allows
for a quality, reliable and cost-effective logistics support
throughout QML products’ life cycles.
D i sc l ai m e r
All radiation performance information is provided for
information purposes only and is not guaranteed. The total
dose effects are lot-dependent, and Actel does not
guarantee that future devices will continue to exhibit
similar radiation characteristics. In addition, actual
performance can vary widely due to a variety of factors,
including but not limited to, characteristics of the orbit,
radiation environment, proximity to satellite exterior,
amount of inherent shielding from other sources within the
satellite and actual bare die variations. For these reasons,
Actel does not guarantee any level of radiation survivability,
and it is solely the responsibility of the customer to
determine whether the device will meet the requirements
of the specific design.
The RT SX devices have varying total dose radiation
survivability. The ability of these devices to survive
v2.0
3
5 4 SX F a m ily F PG A s R a d To l e r a n t a n d Hi R e l
SX F am i l y A r c hi t e c t ur e
The SX family architecture was designed to satisfy
next-generation performance and integration requirements
for production-volume designs in a broad range of
applications.
antifuse interconnect elements, which are embedded
between the M2 and M3 layers. The antifuses are normally
open circuit and, when programmed, form a permanent
low-impedance connection.
P rog ra m ma ble Int er con nect E l em ent
The extremely small size of these interconnect elements
gives the SX family abundant routing resources and provides
excellent protection against design pirating. Reverse
engineering is virtually impossible, because it is extremely
difficult to distinguish between programmed and
unprogrammed antifuses, and there is no configuration
bitstream to intercept.
Actel’s SX family provides much more efficient use of silicon
by locating the routing interconnect resources between the
Metal 2 (M2) and Metal 3 (M3) layers (Figure 1). This
completely eliminates the channels of routing and
interconnect resources between logic modules (as
implemented on SRAM FPGAs and previous generations of
antifuse FPGAs), and enables the entire floor of the device
to be spanned with an uninterrupted grid of logic modules.
Interconnection between these logic modules is achieved
using Actel’s patented metal-to-metal programmable
Additionally, the interconnects (i.e., the antifuses and metal
tracks) have lower capacitance and lower resistance than
any other device of similar capacity, leading to the fastest
signal propagation in the industry.
Routing Tracks
Metal 3
Amorphous Silicon/
Dielectric Antifuse
Tungsten Plug Via
Metal 2
Metal 1
Tungsten Plug
Contact
Silicon Substrate
Figure 1 • SX Family Interconnect Elements
Logi c Modul e Des ign
The SX family architecture has been called a
“sea-of-modules” architecture because the entire floor of
the device is covered with a grid of logic modules with
virtually no chip area lost to interconnect elements or
routing (see Figure 2 on page 5). Actel provides two types of
logic modules, the register cell (R-cell) and the
combinatorial cell (C-cell).
The R-cell contains a flip-flop featuring more control signals
than in previous Actel architectures, including
asynchronous clear, asynchronous preset, and clock enable
(using the S0 and S1 lines). The R-cell registers feature
4
programmable clock polarity, selectable on a
register-by-register basis (Figure 3 on page 5). This provides
the designer with additional flexibility while allowing
mapping of synthesized functions into the SX FPGA. The
clock source for the R-cell can be chosen from the
hard-wired clock or the routed clock.
The C-cell implements a range of combinatorial functions
up to 5-inputs (Figure 4 on page 6). Inclusion of the DB
input and its associated inverter function dramatically
increases the number of combinatorial functions that can be
implemented in a single module from 800 options in
previous architectures to more than 4,000 in the SX
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5 4 SX F a m ily F P GA s R a d T o le r a n t a n d H iR e l
Channelled Array Architecture
Sea-of-Modules Architecture
Figure 2 • Channelled Array and Sea-of-Modules Architectures
S0
Routed
Data Input S1
PSET
Direct
Connect
Input
D
Q
Y
HCLK
CLRB
CLKA,
CLKB
CKS
CKP
Figure 3 • R-Cell
architecture. An example of the improved flexibility
enabled by the inversion capability is the ability to integrate
a 3-input exclusive-OR function into a single C-cell. This
facilitates construction of 9-bit parity-tree functions with 2
ns propagation delays. At the same time, the C-cell
structure is extremely synthesis-friendly, simplifying the
overall design and reducing synthesis time.
Chi p Ar chi tec tu re
The SX family’s chip architecture provides a
uniqueapproach to module organization and chip routing
that delivers the best register/logic mix for a wide variety of
new and emerging applications.
M o d ule O r g a n i z a t io n
Actel has arranged all C-cell and R-cell logic modules into
horizontal banks called Clusters. There are two types of
Clusters: Type 1 contains two C-cells and one R-cell, while
Type 2 contains one C-cell and two R-cells.
To increase design efficiency and device performance, Actel
has further organized these modules into SuperClusters
(see Figure 5 on page 6). SuperCluster 1 is a two-wide
grouping of Type 1 clusters. SuperCluster 2 is a two-wide
group containing one Type 1 cluster and one Type 2 cluster.
SX devices feature more SuperCluster 1 modules than
SuperCluster 2 modules because designers typically require
more combinatorial logic than flip-flops.
v2.0
5
5 4 SX F a m ily F PG A s R a d To l e r a n t a n d Hi R e l
D0
D1
Y
D2
D3
Sa
Sb
DB
A0
B0
A1
B1
Figure 4 • C-Cell
R-Cell
S0
C-Cell
D0
Routed
Data Input S1
D1
PSET
Y
D2
Direct
Connect
Input
D
Q
D3
Y
Sa
Sb
HCLK
CLRB
CLKA,
CLKB
DB
CKS
Cluster 1
CKP
A0
Cluster 2
Cluster 2
Type 1 SuperCluster
B0
A1
B1
Cluster 1
Type 2 SuperCluster
Figure 5 • Cluster Organization
Rou ti ng Res our ces
Clusters and SuperClusters can be connected through the
use of two innovative local routing resources called
FastConnect and DirectConnect that enable extremely fast
and predictable interconnections of modules within
Clusters and SuperClusters (see Figure 6 and Figure 7 on
page 7). This routing architecture also dramatically reduces
the number of antifuses required to complete a circuit,
ensuring the highest possible performance.
6
DirectConnect is a horizontal routing resource that provides
connections from a C-cell to its neighboring R-cell in a given
SuperCluster. DirectConnect uses a hard-wired signal path
requiring no programmable interconnection to achieve its
fast signal propagation time of less than 0.1 ns.
FastConnect enables horizontal routing between any two
logic modules within a given SuperCluster, and vertical
routing with the SuperCluster immediately below it. Only
one programmable connection is used in a FastConnect
path, delivering maximum pin-to-pin propagation of 0.4 ns.
v2.0
5 4 SX F a m ily F P GA s R a d T o le r a n t a n d H iR e l
In addition to DirectConnect and FastConnect, the
architecture makes use of two globally-oriented routing
resources known as segmented routing and high-drive
routing. Actel’s segmented routing structure provides a
variety of track lengths for extremely fast routing between
SuperClusters. The exact combination of track lengths and
antifuses within each path is chosen by the 100% automatic
place and route software to minimize signal propagation
delays.
DirectConnect
• No antifuses
FastConnect
• One antifuse
Routing Segments
• Typically 2 antifuses
• Max. 5 antifuses
Type 1 SuperClusters
Figure 6 • DirectConnect and FastConnect for Type 1 SuperClusters
DirectConnect
• No antifuses
FastConnect
• One antifuse
Routing Segments
• Typically 2 antifuses
• Max. 5 antifuses
Type 2 SuperClusters
Figure 7 • DirectConnect and FastConnect for Type 2 SuperClusters
v2.0
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5 4 SX F a m ily F PG A s R a d To l e r a n t a n d Hi R e l
Clock Resources
Actel’s high-drive routing structure provides three clock
networks. The first clock, called HCLK, is hardwired from the
HCLK buffer to the clock select MUX in each R-cell. HCLK
cannot be connected to combinational logic. This provides a
fast propagation path for the clock signal, enabling the 5.8 ns
clock-to-out (pad-to-pad) performance of the RT54SX devices.
The hard-wired clock is tuned to provide clock skew is less
than 0.5ns worst case.
The remaining two clocks (CLKA, CLKB) are global clocks
that can be sourced from external pins or from internal logic
signals within the RT54SX device. CLKA and CLKB may be
connected to sequential cells or to combinational logic. If
CLKA or CLKB is sourced from internal logic signals then the
external clock pin cannot be used for any other input and
must be tied low or high. Figure 8 describes the clock circuit
used for the constant load HCLK. Figure 9 describes the
CLKA and CLKB circuit used in RT54SX devices with the
exception of RT54SX72S.
O t h er Ar ch i t e ct u r e Fe a t ur es
P er f or m ance
The combination of architectural features described above
enables RT54SX devices to operate with internal clock
frequencies exceeding 160 MHz, enabling very fast
execution of complex logic functions. Thus, the RT54SX
family is an optimal platform upon which to integrate the
functionality previously contained in multiple CPLDs. In
addition, designs that previously would have required a gate
array to meet performance goals can now be integrated into
an RT54SX device with dramatic improvements in cost and
time-to-market. Using timing-driven place-and-route tools,
designers can achieve highly deterministic device
performance. With RT54SX devices, designers do not need
to use complicated performance-enhancing design
techniques such as redundant logic to reduce fanout on
critical nets or the instantiation of macros in HDL code to
achieve high performance.
I / O M o d u les
Constant Load
Clock Network
HCLKBUF
Figure 8 • RT54SX Constant Load Clock Pad
Clock Network
From Internal Logic
Each I/O on an RT54SX device can be configured as an
input, an output, a tristate output, or a bidirectional pin.
Even without the inclusion of dedicated registers, these
I/Os, in combination with array registers, can achieve
clock-to-out (PAD-to-PAD) timing as fast as 5.8 ns. I/O cells
including embedded latches and flip-flops require
instantiation in HDL code. This is a design complication not
encountered in RT54SX FPGAs. Fast PAD-to-PAD timing
ensures that the device will have little trouble interfacing
with any other device in the system, which in turn enables
parallel design of system components and reduces overall
design time.
P owe r Re quir em en ts
CLKBUF
CLKBUFI
CLKINT
CLKINTI
Figure 9 • RT54SX Clock Pads
The RT54SX family supports either 3.3V or 5.0V I/O voltage
operation and is designed to tolerate 5V inputs in each case
(Table 1). Power consumption is extremely low due to the
very short distances signals are required to travel to
complete a circuit. Power requirements are further reduced
due to the small number of antifuses in the path, and
because of the low resistance properties of the antifuses.
The antifuse architecture does not require active circuitry
to hold a charge (as do SRAM or EPROM), making it the
lowest-power architecture on the market.
Table 1 • Supply Voltages
A54SX16
A54SX32
RTSX16
RTSX32
8
v2.0
Maximum Maximum
Input
Output
Tolerance
Drive
V CCA
V CCI
V CCR
3.3V
3.3V
5.0V
3.3V
3.3V
3.3V
3.3V
5.0V
5.0V
3.3V
5 4 SX F a m ily F P GA s R a d T o le r a n t a n d H iR e l
Bou ndar y S can T es ti ng (BS T )
Table 2 • Boundary Scan Pin Functionality
All RT54SX devices are IEEE 1149.1 (JTAG) compliant.
They offer superior diagnostic and testing capabilities by
providing Boundary Scan Testing (BST) and probing
capabilities. These functions are controlled through the
special test pins in conjunction with the program fuse. The
functionality of each pin is described in Table 2. Figure 10
is a block diagram of the RT54SX JTAG circuitry.
TDI
Program Fuse Blown
(Dedicated Test Mode)
Program Fuse Not Blown
(Flexible Mode)
TCK, TDI, TDO are
dedicated test pins
TCK, TDI, TDO are flexible
and may be used as I/Os
No need for pull-up resistor
for TMS
Use a pull-up resistor of
10k Ω on TMS
Data Registers (DRs)
0
1
output
stage
TDO
Instruction Register (IR)
clocks and/or controls
TMS
TAP Controller
TCK
TRST external
hard-wired pin
Figure 10 • RT54SX JTAG Circuitry
Con f igu ri ng Di agnos t ic P ins
The JTAG and Probe pins (TDI, TCK, TMS, TDO, PRA, and
PRB) are placed in the desired mode by selecting the
appropriate check boxes in the “Variation” dialog window.
This dialog window is accessible through the Design Setup
Wizard under the Tools menu in Actel’s Designer software.
T RS T pi n
The TRST pin functions as a Boundary Scan Reset pin. The
TRST pin is an asynchronous, active-low input to initialize
or reset the BST circuit. An internal pull-up resistor is
automatically enabled on the TRST pin.
Ded ica ted T es t Mod e
When the “Reserve JTAG” box is checked in the Designer
software, the RT54SX is placed in Dedicated Test mode, which
configures the TDI, TCK, and TDO pins for BST or in-circuit
verification with Silicon Explorer II. An internal pull-up resistor
is automatically enabled on both the TMS and TDI pins. In
dedicated test mode, TCK, TDI, and TDO are dedicated test pins
and become unavailable for pin assignment in the Pin Editor.
The TMS pin will function as specified in the IEEE 1149.1
(JTAG) Specification.
Fle xib le Mode
When the “Reserve JTAG” box is not selected (default setting
in Designer software), the RT54SX is placed in flexible mode,
which allows the TDI, TCK, and TDO pins to function as user
I/Os or BST pins. In this mode the internal pull-up resistors on
the TMS and TDI pins are disabled. An external 10k Ω pull-up
resistor to VCCI is required on the TMS pin.
The TDI, TCK, and TDO pins are transformed from user I/Os
into BST pins when a rising edge on TCK is detected while
TMS is at logical low. Once the BST pins are in test mode
they will remain in BST mode until the internal BST state
v2.0
9
5 4 SX F a m ily F PG A s R a d To l e r a n t a n d Hi R e l
iteration. The probe circuitry is accessed by Silicon Explorer
II, an easy to use integrated verification and logic analysis
tool that can sample data at 100 MHz (asynchronous) or
66 MHz (synchronous). Silicon Explorer attaches to a PC’s
standard COM port, turning the PC into a fully functional 18
channel logic analyzer. Silicon Explorer allows designers to
complete the design verification process at their desks and
reduces verification time from several hours per cycle to a
few seconds.
machine reaches the “logic reset” state. At this point the
BST pins will be released and will function as regular I/O
pins. The "logic reset” state is reached 5 TCK cycles after
the TMS pin is set to logical HIGH.
The program fuse determines whether the device is in
Dedicated Test or Flexible mode. The default (fuse not
programmed) is Flexible mode.
Dev el opm ent To ol S uppor t
The RT54SX RadTolerant devices are fully supported by
Actel’s line of FPGA development tools, including the Actel
DeskTOP Series and Designer Series’ tools. The Actel
DeskTOP Series is an integrated design environment for PCs
that includes design entry, simulation, synthesis, and
place-and-route tools. Designer Series is Actel’s suite of
FPGA development point tools for PCs and Workstations
that includes the ACTgen Macro Builder, Designer Series
with DirectTime timing driven place-and-route and analysis
tools, and device programming software.
The Silicon Explorer II tool uses the boundary scan ports
(TDI, TRST, TCK, TMS, and TDO) to select the desired nets
for verification. The selected internal nets are assigned to
the PRA/PRB pins for observation. Figure 11 illustrates the
interconnection between Silicon Explorer II and the FPGA
to perform in-circuit verification.
D esi gn Con si der at ion s
For prototyping, the TDI, TCK, TDO, PRA, and PRB pins
should not be used as input or bidirectional ports. Because
these pins are active during probing, critical signals input
through these pins are not available while probing. In
addition, the security fuse should not be programmed during
prototyping because doing so disables the probe circuitry.
RT 54S X P r obe Ci rc uit C ont r ol P ins
Channels
16
The RT54SX RadTolerant devices contain internal probing
circuitry that provides built-in access to every node in a
design, enabling 100-percent real-time observation and
analysis of a device's internal logic nodes without design
RT54SX-S FPGA
TRST
TCK
TMS
Serial Connection
Silicon Explorer II
TDO
PRA
PRB
Figure 11 • Probe Setup
10
v2.0
5 4 SX F a m ily F P GA s R a d T o le r a n t a n d H iR e l
R ec om m en de d Op e r at i ng C on di t i on s
3. 3 V / 5V O p era t i n g C o nd i t i o ns
R ec om m e n de d O p er a t i n g
C o nd i t i o ns 1
Symbol
Parameter
Parameter
Commercial
Military
Units
VCCR
0 to +70
–55 to +125
°C
Temperature
Range1
3.3V Power2
Supply Tolerance
±10
±10
%VCC
5V Power Supply 2
Tolerance
±5
±10
%VCC
Limits
Units
DC Supply Voltage
–0.3 to +6.0
V
VCCA
DC Supply Voltage
–0.3 to +4.0
V
VCCI
DC Supply Voltage
–0.3 to +4.0
V
VI
Input Voltage
–0.5 to +5.5
V
VO
Output Voltage
–0.5 to +3.6
V
–30 to +5.0
mA
–40 to +125
°C
I/O Source Sink
IIO
Notes:
1. Ambient temperature (TA) is used for commercial and
industrial; case temperature (TC) is used for military.
2. All power supplies must be in the recommended operating range
for 250µs. For more information, please refer to the
Power-Up Design Considerations application note at
http://www.actel.com/appnotes.
Current2
TSTG
Storage Temperature
Notes:
1. Stresses beyond those listed in the Absolute Maximum Ratings
table may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may
affect device reliability. Device should not be operated outside
the Recommended Operating Conditions.
2. The I/O source sink numbers refer to tristated inputs and
outputs
El e c t r i c al S p ec i f i c at i o n s
Commercial
Symbol
Parameter
(IOH = –20µA) (CMOS)
VOH
(IOH = –8mA) (TTL)
Min.
Max.
Min.
Max.
(VCCI – 0.1)
VCCI
(VCCI – 0.1)
VCCI
2.4
VCCI
(IOL= 20µA) (CMOS)
0.10
(IOL = 12mA) (TTL)
0.50
Units
V
2.4
(IOH = –6mA) (TTL)
VOL
Military
VCCI
V
(IOL = 8mA) (TTL)
0.50
VIL
Low Level Inputs
0.8
VIH
High Level Inputs
tR, tF
Input Transition Time tR, tF
50
50
ns
CIO
CIO I/O Capacitance
10
10
pF
ICC
Standby Current, ICC
4.0
25
mA
ICC(D)
ICC(D) IDynamic VCC Supply Current
2.0
0.8
2.0
V
V
See the “Power Dissipation” section on page 13.
v2.0
11
5 4 SX F a m ily F PG A s R a d To l e r a n t a n d Hi R e l
Po w e r- U p S e qu en ci ng
RT 54S X 16, A 54S X16 , RT 54S X 32, A5 4S X32
VCCA
3.3V
VCCR
5.0V
VCCI
3.3V
Power-Up Sequence
Comments
5.0V First
3.3V Second
No possible damage to device.
3.3V First
5.0V Second
Possible damage to device.
Po w e r - D ow n Se q ue nc i n g
RT54SX16, A54SX16, RT54SX32, A54SX32
VCCA
3.3V
VCCR
5.0V
VCCI
3.3V
Power-Down Sequence
Comments
5.0V First
3.3V Second
Possible damage to device.
3.3V First
5.0V Second
No possible damage to device.
Pa c ka ge T he r m a l C ha r a ct e r i s t i c s
The device junction to case thermal characteristic is θjc,
and the junction to ambient air characteristic is θja. The
thermal characteristics for θja are shown with two different
air flow rates.
Maximum junction temperature is 150°C.
A sample calculation of the absolute maximum power
dissipation allowed for an RT54SX16 in a CQFP 256-pin
package at military temperature and still air is as follows:
Max. junction temp. (°C) – Max. ambient temp. (°C)
150°C – 125°C
Absolute Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------------ = ------------------------------------ = 1.09W
θ ja (°C/W)
23°C/W
θja
Pin Count
θjc
Still Air
Units
Ceramic Quad Flat Pack (CQFP)
208
7.5
29
°C/W
Ceramic Quad Flat Pack (CQFP)
256
4.6
23
°C/W
Ceramic Quad Flat Pack (CQFP)
208
6.9
35
°C/W
Ceramic Quad Flat Pack (CQFP)
256
3.5
20
°C/W
Ceramic Quad Flat Pack (CQFP)
208
7.9
30
°C/W
Ceramic Quad Flat Pack (CQFP)
256
5.6
25
°C/W
Ceramic Quad Flat Pack (CQFP)
208
7.6
30
°C/W
Ceramic Quad Flat Pack (CQFP)
256
4.8
24
°C/W
Package Type
RT54SX16
RT54SX32
A54SX16
A54SX32
12
v2.0
5 4 SX F a m ily F P GA s R a d T o le r a n t a n d H iR e l
Po w e r D i ss i pa t i o n
and load device inputs. An additional component of the
active power dissipation is the totempole current in CMOS
transistor pairs. The net effect can be associated with an
equivalent capacitance that can be combined with
frequency and voltage to represent active power dissipation.
P = [ICCstandby + ICCactive] * VCCA + IOL * VOL * N +
IOH *(VCCA – VOH) * M
where:
ICCstandby is the current flowing when no inputs or
outputs are changing.
E qui val ent C apac it ance
The power dissipated by a CMOS circuit can be expressed by
Equation 1:
ICCactive is the current flowing due to CMOS switching.
IOL, IOH are TTL sink/source currents.
Power (µW) = CEQ * VCCA2 * F
VOL, VOH are TTL level output voltages.
where:
N equals the number of outputs driving TTL loads to VOL.
CEQ
VCCA
F
M equals the number of outputs driving TTL loads to VOH.
Accurate values for N and M are difficult to determine
because they depend on the design and on the system I/O.
The power can be divided into two components: static and
active.
The power due to standby current is typically a small
component of the overall power. Standby power is shown
below for military, worst case conditions (70°C).
VCC
3.6V
= Equivalent capacitance in pF
= Power supply in volts (V)
= Switching frequency in MHz
Equivalent capacitance is calculated by measuring
ICCactive at a specified frequency and voltage for each
circuit component of interest. Measurements have been
made over a range of frequencies at a fixed value of VCCA.
Equivalent capacitance is frequency-independent so that
the results may be used over a wide range of operating
conditions. Equivalent capacitance values are shown below.
S tat i c P ow er Co m ponen t
ICC
20 mA
(1)
Power
72 mW
C E Q Va lue s ( pF)
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic
must be known. Equation 2 shows a piece-wise linear
summation over all components.
Act i ve P ower C om po nent
Power dissipation in CMOS devices is usually dominated by
the active (dynamic) power dissipation. This component is
frequency-dependent, a function of the logic and the
external I/O. Active power dissipation results from charging
internal chip capacitances of the interconnect,
unprogrammed antifuses, module inputs, and module
outputs, plus external capacitance due to PC board traces
Power =VCCA2 * [(m * CEQM * fm)modules +
(n * CEQI * fn)inputs+ (p * (CEQO + CL) * fp)outputs+
0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 +
0.5 * (q2 * CEQCR * fq2)routed_Clk2+ (r2 * fq2)routed_Clk2 +
0.5 * (s1 * CEQCD * fs1)dedicated_CLK]
(2)
RT54SX16
A54SX16
RT54SX32
A54SX32
Equivalent Capacitance (pF)
Modules
CEQM
7.0
3.9
7.0
3.9
Input Buffers
CEQI
2.0
1.0
2.0
1.0
Output Buffers
CEQO
10.0
5.0
10.0
5.0
Routed Array Clock Buffer Loads
CEQCR
0.4
0.2
0.6
0.3
Dedicated Clock Buffer Loads
CEQCD
0.25
0.15
0.34
0.23
routed_Clk1
r1
120
60
210
107
routed_Clk2
r2
120
60
210
107
s1
528
528
1,080
1,080
Fixed Capacitance (pF)
Fixed Clock Loads
Clock Loads on Dedicated Array Clock
v2.0
13
5 4 SX F a m ily F PG A s R a d To l e r a n t a n d Hi R e l
D et erm i nin g A ve ra ge S wi t chi ng F re quenc y
where:
m
n
p
q1
=
=
=
=
q2
=
r1
=
r2
=
s1
=
CEQM
CEQI
CEQO
CEQCR
=
=
=
=
CEQCD
=
CL
fm
fn
fp
fq1
fq2
=
=
=
=
=
=
14
Number of logic modules switching at fm
Number of input buffers switching at fn
Number of output buffers switching at fp
Number of clock loads on the first routed array
clock
Number of clock loads on the second routed
array clock
Fixed capacitance due to first routed array
clock
Fixed capacitance due to second routed array
clock
Fixed number of clock loads on the dedicated
array clock = (528 for A54SX16)
Equivalent capacitance of logic modules in pF
Equivalent capacitance of input buffers in pF
Equivalent capacitance of output buffers in pF
Equivalent capacitance of routed array clock in
pF
Equivalent capacitance of dedicated array
clock in pF
Output lead capacitance in pF
Average logic module switching rate in MHz
Average input buffer switching rate in MHz
Average output buffer switching rate in MHz
Average first routed array clock rate in MHz
Average second routed array clock rate in MHz
To determine the switching frequency for a design, you must
have a detailed understanding of the data input values to
the circuit. The following guidelines are meant to represent
worst-case scenarios so that they can be generally used to
predict the upper limits of power dissipation. These
guidelines are as follows:
Logic Modules (m)
=
Inputs Switching (n)
=
Outputs Switching (p)
=
First Routed Array Clock Loads (q1) =
Second Routed Array Clock Loads
(q2)
=
Load Capacitance (CL)
Average Logic Module Switching
Rate (fm)
Average Input Switching Rate (fn)
Average Output Switching Rate (fp)
Average First Routed Array Clock
Rate (fq1)
Average Second Routed Array Clock
Rate (fq2)
Average Dedicated Array Clock Rate
(fs1)
=
=
80% of modules
# inputs/4
# output/4
40% of
sequential
modules
40% of
sequential
modules
35 pF
F/10
=
=
=
F/5
F/10
F/2
=
F/2
=
F
v2.0
5 4 SX F a m ily F P GA s R a d T o le r a n t a n d H iR e l
Te m p er a t u r e an d Vo l t a ge D er at i n g Fa ct or s
(Normalized to Worst-Case Commercial, T J = 70 ° C, V CCA = 3.0V)
Junction Temperature (TJ)
VCCA
–40
0
25
70
85
125
3.0
0.78
0.87
0.89
1.00
1.04
1.16
3.3
0.73
0.82
0.83
0.93
0.97
1.08
3.6
0.69
0.77
0.78
0.87
0.92
1.02
54 S X T i m i n g M o d el *
Input Delays
I/O Module
tINY = 2.2 ns
Internal Delays
Predicted
Routing
Delays
Combinatorial
Cell
Output Delays
I/O Module
tIRD2 = 1.2 ns
tDHL = 2.8 ns
tPD =0.9 ns
tRD1 = 0.7 ns
tRD4 = 2.2 ns
tRD8 = 4.3 ns
I/O Module
tDHL = 2.8 ns
Register
Cell
D
Q
Register
Cell
tRD1 = 0.7 ns
D
Q
tRD1 = 0.7 ns
tENZH = 2.8 ns
tSUD = 0.8 ns
tHD = 0.0 ns
tRCO = 0.6 ns
Routed
Clock
tRCO = 0.6 ns
tRCKH = 2.8 ns (100% Load)
FMAX = 175 MHz
Hard-Wired
Clock
tHCKH = 1.3 ns
FHMAX = 240 MHz
*Values shown for A54SX16-1 at worst-case commercial conditions.
H ar d-W i re d C loc k
Ro ute d C loc k
External Set-Up = tINY + tIRD1 + tSUD – tHCKH
External Set-Up = tINY + tIRD1 + tSUD – tRCKH
= 2.2 + 0.7 + 0.8 – 1.7 = 2.0 ns
Clock-to-Out (Pin-to-Pin)
= 2.2 + 0.7 + 0.8 – 2.4 = 1.3 ns
Clock-to-Out (Pin-to-Pin)
= tHCKH + tRCO + tRD1 + tDHL
= tRCKH + tRCO + tRD1 + tDHL
= 1.7 + 0.6 + 0.7 + 2.8 = 5.8 ns
= 2.4 + 0.6 + 0.7 + 2.8 = 6.5 ns
v2.0
15
5 4 SX F a m ily F PG A s R a d To l e r a n t a n d Hi R e l
O ut p u t B uf f e r D e l ay s
E
D
VCC
In
50%
Out
VOL
PAD To AC test loads (shown below)
TRIBUFF
VCC
GND
50%
VOH
En
1.5V
1.5V
50%
VCC
VCC
50%
GND
1.5V
Out
En
Out
GND
10%
VOL
tDLH
tDHL
tENZL
tENLZ
GND
50%
VOH
50%
90%
1.5V
tENHZ
tENZH
A C T e st L oa d s
Load 1
(Used to measure propagation delay)
Load 2
(Used to measure rising/falling edges)
VCC
GND
To the output under test
50 pF
R to VCC for tPLZ/tPZL
R to GND for tPHZ/tPZH
R = 1 kΩ
To the output under test
50 pF
I n pu t B uf f er D e l ay s
PAD
C - Ce l l D el a y s
S
A
B
Y
INBUF
Y
VCC
3V
In
Out
GND
50% 50%
VCC
Out
GND
50%
50%
50%
tINY
16
0V
1.5V 1.5V
VCC
S, A or B
tPD
GND
50%
tPD
VCC
Out
50%
tPD
tINY
v2.0
GND
tPD
50%
5 4 SX F a m ily F P GA s R a d T o le r a n t a n d H iR e l
R eg i st e r C e l l Ti m i ng C ha r a ct e r i s t i c s
Fli p- Flop s
D
PRESET
CLK
Q
CLR
(Positive edge triggered)
tHD
D
tSUD
CLK
tHP
tHPWH,
tRPWH
tRCO
tHPWL,
tRPWL
Q
tCLR
tPRESET
CLR
tWASYN
PRESET
Ti m i ng C ha r a ct e r i s t i c s
Long T r acks
Timing characteristics for 54SX devices fall into three
categories: family-dependent, device-dependent, and
design-dependent. The input and output buffer
characteristics are common to all 54SX family members.
Internal routing delays are device dependent. Design
dependency means actual delays are not determined until
after placement and routing of the user’s design is
complete. Delay values may then be determined by using
the DirectTime Analyzer utility or performing simulation
with post-layout delays.
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows, columns,
or modules. Long tracks employ three and sometimes five
antifuse connections. This increases capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically up to 6% of nets in a fully
utilized device require long tracks. Long tracks contribute
approximately 4 ns to 8.4 ns delay. This additional delay is
represented statistically in higher fanout (FO=24) routing
delays in the data sheet specifications section.
Cr it ic al Net s and T ypi cal Ne ts
T im in g D er at ing
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most
time-critical paths. Critical nets are determined by net
property assignment prior to placement and routing. Up to
6 percent of the nets in a design may be designated as
critical, while 90 percent of the nets in a design are typical.
54SX devices are manufactured in a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process variations. Minimum
timing parameters reflect maximum operating voltage,
minimum operating temperature, and best-case processing.
Maximum timing parameters reflect minimum operating
voltage, maximum operating temperature, and worst-case
processing.
v2.0
17
5 4 SX F a m ily F PG A s R a d To l e r a n t a n d Hi R e l
A 54 SX 1 6 T i m i n g C h ar ac t e r i st i cs
(Worst-Case Military Conditions, V C CR = 4.75V, V CCA, V C CI = 3.0V, T J = 125 ° C)
C-Cell Propagation Delays1
Parameter
Description
tPD
Internal Array Module
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
0.9
1.0
ns
Predicted Routing Delays2
tDC
FO=1 Routing Delay, Direct Connect
0.1
0.1
ns
tFC
FO=1 Routing Delay, Fast Connect
0.6
0.7
ns
tRD1
FO=1 Routing Delay
0.7
0.8
ns
tRD2
FO=2 Routing Delay
1.2
1.4
ns
tRD3
FO=3 Routing Delay
1.7
2.0
ns
tRD4
FO=4 Routing Delay
2.2
2.6
ns
tRD8
FO=8 Routing Delay
4.3
5.0
ns
tRD12
FO=12 Routing Delay
5.6
6.6
ns
tRD18
FO=18 Routing Delay
9.4
11.0
ns
tRD24
FO=24 Routing Delay
12.4
14.6
ns
tRCO
Sequential Clock-to-Q
0.6
0.8
ns
tCLR
Asynchronous Clear-to-Q
0.6
0.8
ns
tSUD
Flip-Flop Data Input Set-Up
0.8
0.9
ns
tHD
Flip-Flop Data Input Hold
0.0
0.0
ns
tWASYN
Asynchronous Pulse Width
2.4
2.9
ns
R-Cell Timing
I/O Module Input Propagation Delays
tINYH
Input Data Pad-to-Y HIGH
2.2
2.6
ns
tINYL
Input Data Pad-to-Y LOW
2.2
2.6
ns
Predicted Input Routing
Delays3
tIRD1
FO=1 Routing Delay
0.7
0.8
ns
tIRD2
FO=2 Routing Delay
1.2
1.4
ns
tIRD3
FO=3 Routing Delay
1.7
2.0
ns
tIRD4
FO=4 Routing Delay
2.2
2.6
ns
tIRD8
FO=8 Routing Delay
4.3
5.0
ns
tIRD12
FO=12 Routing Delay
5.6
6.6
ns
tIRD18
FO=18 Routing Delay
9.4
11.0
ns
tIRD24
FO=24 Routing Delay
12.4
14.6
ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
18
v2.0
5 4 SX F a m ily F P GA s R a d T o le r a n t a n d H iR e l
A 54 SX 1 6 T i m i n g C h ar ac t e r i st i cs (continued)
(Worst-Case Military Conditions, V C CR = 4.75V, V CCA, V C CI = 3.0V, T J = 125 ° C)
I/O Module – TTL Output Timing1
Parameter
Description
tDLH
Data-to-Pad LOW to HIGH
tDHL
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
2.8
3.3
ns
Data-to-Pad HIGH to LOW
2.8
3.3
ns
tENZL
Enable-to-Pad, Z to L
2.3
2.8
ns
tENZH
Enable-to-Pad, Z to H
2.8
3.3
ns
tENLZ
Enable-to-Pad, L to Z
4.5
5.2
ns
tENHZ
Enable-to-Pad, H to Z
2.2
2.6
ns
dTLH
Delta LOW to HIGH
0.05
0.06
ns/pF
dTHL
Delta HIGH to LOW
0.05
0.08
ns/pF
Input LOW to HIGH
(Pad to R-Cell Input)
1.7
2.0
ns
Input HIGH to LOW
(Pad to R-Cell Input)
1.9
2.2
ns
Dedicated (Hard-Wired) Array Clock Network
tHCKH
tHCKL
tHPWH
Minimum Pulse Width HIGH
2.1
2.4
ns
tHPWL
Minimum Pulse Width LOW
2.1
2.4
ns
tHCKSW
Maximum Skew
tHP
Minimum Period
fHMAX
Maximum Frequency
0.4
4.2
0.4
4.9
ns
ns
240
205
MHz
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
2.4
2.9
ns
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
2.7
3.1
ns
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
2.9
3.3
ns
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
2.9
3.5
ns
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
2.8
3.3
ns
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
2.9
3.5
ns
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
tRPWH
Min. Pulse Width HIGH
3.1
3.7
ns
tRPWL
Min. Pulse Width LOW
3.1
3.7
ns
tRCKSW
Maximum Skew (Light Load)
0.6
0.8
ns
tRCKSW
Maximum Skew (50% Load)
0.8
0.9
ns
tRCKSW
Maximum Skew (100% Load)
0.8
0.9
ns
Note:
1. Delays based on 35 pF loading, except for tENZL and tENZH . For tENZL and tENZH the loading is 5 pF.
v2.0
19
5 4 SX F a m ily F PG A s R a d To l e r a n t a n d Hi R e l
R T5 4S X 16 T i m i ng C ha r a ct er i s t i c s
(Worst-Case Military Conditions, V C CR = 4.75V, V CCA, V C CI = 3.0V, T J = 125 ° C)
C-Cell Propagation Delays1
Parameter
Description
tPD
Internal Array Module
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
1.7
1.8
ns
Predicted Routing Delays2
tDC
FO=1 Routing Delay, Direct Connect
0.2
0.2
ns
tFC
FO=1 Routing Delay, Fast Connect
1.1
1.3
ns
tRD1
FO=1 Routing Delay
1.3
1.5
ns
tRD2
FO=2 Routing Delay
2.2
2.6
ns
tRD3
FO=3 Routing Delay
3.1
3.6
ns
tRD4
FO=4 Routing Delay
4.0
4.7
ns
tRD8
FO=8 Routing Delay
7.8
9.0
ns
tRD12
FO=12 Routing Delay
10.1
11.9
ns
tRD18
FO=18 Routing Delay
17.0
19.8
ns
tRD24
FO=24 Routing Delay
22.4
26.3
ns
tRCO
Sequential Clock-to-Q
1.5
2.0
ns
tCLR
Asynchronous Clear-to-Q
1.5
2.0
ns
tSUD
Flip-Flop Data Input Set-Up
2.0
2.2
ns
tHD
Flip-Flop Data Input Hold
0.0
0.0
ns
tWASYN
Asynchronous Pulse Width
4.4
5.3
ns
R-Cell Timing
I/O Module Input Propagation Delays
tINYH
Input Data Pad-to-Y HIGH
4.0
4.7
ns
tINYL
Input Data Pad-to-Y LOW
4.0
4.7
ns
Predicted Input Routing
Delays3
tIRD1
FO=1 Routing Delay
1.3
1.5
ns
tIRD2
FO=2 Routing Delay
2.2
2.6
ns
tIRD3
FO=3 Routing Delay
3.1
3.6
ns
tIRD4
FO=4 Routing Delay
4.0
4.7
ns
tIRD8
FO=8 Routing Delay
7.8
9.0
ns
tIRD12
FO=12 Routing Delay
10.1
11.9
ns
tIRD18
FO=18 Routing Delay
17.0
19.8
ns
tIRD24
FO=24 Routing Delay
22.4
26.3
ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
20
v2.0
5 4 SX F a m ily F P GA s R a d T o le r a n t a n d H iR e l
R T5 4S X 16 T i m i ng C ha r a ct er i s t i c s (continued)
(Worst-Case Military Conditions, V C CR = 4.75V, V CCA, V C CI = 3.0V, T J = 125 ° C)
I/O Module – TTL Output Timing1
Parameter
Description
tDLH
Data-to-Pad LOW to HIGH
tDHL
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
5.1
6.0
ns
Data-to-Pad HIGH to LOW
5.1
6.0
ns
tENZL
Enable-to-Pad, Z to L
4.2
5.1
ns
tENZH
Enable-to-Pad, Z to H
5.1
6.0
ns
tENLZ
Enable-to-Pad, L to Z
8.1
9.4
ns
tENHZ
Enable-to-Pad, H to Z
4.0
4.7
ns
dTLH
Delta LOW to HIGH
0.09
0.11
ns/pF
dTHL
Delta HIGH to LOW
0.09
0.15
ns/pF
Input LOW to HIGH
(Pad to R-Cell Input)
3.1
3.6
ns
Input HIGH to LOW
(Pad to R-Cell Input)
3.5
4.0
ns
Dedicated (Hard-Wired) Array Clock Network
tHCKH
tHCKL
tHPWH
Minimum Pulse Width HIGH
3.8
4.4
ns
tHPWL
Minimum Pulse Width LOW
3.8
4.4
ns
tHCKSW
Maximum Skew
tHP
Minimum Period
fHMAX
Maximum Frequency
0.8
7.6
0.8
8.9
ns
ns
130
110
MHz
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
4.4
5.3
ns
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
4.9
5.6
ns
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
5.3
6.0
ns
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
5.3
6.3
ns
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
5.1
6.0
ns
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
5.3
6.3
ns
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
tRPWH
Min. Pulse Width HIGH
5.6
6.7
ns
tRPWL
Min. Pulse Width LOW
5.6
6.7
ns
tRCKSW
Maximum Skew (Light Load)
1.1
1.5
ns
tRCKSW
Maximum Skew (50% Load)
1.5
1.7
ns
tRCKSW
Maximum Skew (100% Load)
1.5
1.7
ns
Note:
1. Delays based on 35 pF loading, except for tENZL and tENZH . For tENZL and tENZH the loading is 5 pF.
v2.0
21
5 4 SX F a m ily F PG A s R a d To l e r a n t a n d Hi R e l
A 54 SX 3 2 T i m i n g C h ar ac t e r i st i cs
(Worst-Case Military Conditions, V C CR = 4.75V, V CCA, V C CI = 3.0V, T J = 125 ° C)
C-Cell Propagation Delays1
Parameter
Description
tPD
Internal Array Module
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
0.9
1.0
ns
Predicted Routing Delays2
tDC
FO=1 Routing Delay, Direct Connect
0.1
0.1
ns
tFC
FO=1 Routing Delay, Fast Connect
0.6
0.7
ns
tRD1
FO=1 Routing Delay
0.7
0.8
ns
tRD2
FO=2 Routing Delay
1.2
1.4
ns
tRD3
FO=3 Routing Delay
1.7
2.0
ns
tRD4
FO=4 Routing Delay
2.2
2.6
ns
tRD8
FO=8 Routing Delay
4.3
5.0
ns
tRD12
FO=12 Routing Delay
5.6
6.6
ns
tRD18
FO=18 Routing Delay
9.4
11.0
ns
tRD24
FO=24 Routing Delay
12.4
14.6
ns
tRCO
Sequential Clock-to-Q
0.6
0.8
ns
tCLR
Asynchronous Clear-to-Q
0.6
0.8
ns
tSUD
Flip-Flop Data Input Set-Up
0.8
0.9
ns
tHD
Flip-Flop Data Input Hold
0.0
0.0
ns
tWASYN
Asynchronous Pulse Width
2.4
2.9
ns
R-Cell Timing
I/O Module Input Propagation Delays
tINYH
Input Data Pad-to-Y HIGH
2.2
2.6
ns
tINYL
Input Data Pad-to-Y LOW
2.2
2.6
ns
Predicted Input Routing
Delays3
tIRD1
FO=1 Routing Delay
0.7
0.8
ns
tIRD2
FO=2 Routing Delay
1.2
1.4
ns
tIRD3
FO=3 Routing Delay
1.7
2.0
ns
tIRD4
FO=4 Routing Delay
2.2
2.6
ns
tIRD8
FO=8 Routing Delay
4.3
5.0
ns
tIRD12
FO=12 Routing Delay
5.6
6.6
ns
tIRD18
FO=18 Routing Delay
9.4
11.0
ns
tIRD24
FO=24 Routing Delay
12.4
14.6
ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
22
v2.0
5 4 SX F a m ily F P GA s R a d T o le r a n t a n d H iR e l
A 54 SX 3 2 T i m i n g C h ar ac t e r i st i cs (continued)
(Worst-Case Military Conditions, V C CR = 4.75V, V CCA, V C CI = 3.0V, T J = 125 ° C)
I/O Module – TTL Output Timing1
Parameter
Description
tDLH
Data-to-Pad LOW to HIGH
tDHL
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
2.8
3.3
ns
Data-to-Pad HIGH to LOW
2.8
3.3
ns
tENZL
Enable-to-Pad, Z to L
2.3
2.8
ns
tENZH
Enable-to-Pad, Z to H
2.8
3.3
ns
tENLZ
Enable-to-Pad, L to Z
4.5
5.2
ns
tENHZ
Enable-to-Pad, H to Z
2.2
2.6
ns
dTLH
Delta LOW to HIGH
0.05
0.06
ns/pF
dTHL
Delta HIGH to LOW
0.05
0.08
ns/pF
Input LOW to HIGH
(Pad to R-Cell Input)
1.7
2.0
ns
Input HIGH to LOW
(Pad to R-Cell Input)
1.9
2.2
ns
Dedicated (Hard-Wired) Array Clock Network
tHCKH
tHCKL
tHPWH
Minimum Pulse Width HIGH
2.1
2.4
ns
tHPWL
Minimum Pulse Width LOW
2.1
2.4
ns
tHCKSW
Maximum Skew
tHP
Minimum Period
fHMAX
Maximum Frequency
0.4
4.2
0.4
4.8
ns
ns
240
205
MHz
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
2.4
2.9
ns
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
2.7
3.1
ns
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
2.9
3.3
ns
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
2.9
3.5
ns
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
2.8
3.3
ns
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
2.9
3.5
ns
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
tRPWH
Min. Pulse Width HIGH
3.1
3.7
ns
tRPWL
Min. Pulse Width LOW
3.1
3.7
ns
tRCKSW
Maximum Skew (Light Load)
0.6
0.8
ns
tRCKSW
Maximum Skew (50% Load)
0.8
0.9
ns
tRCKSW
Maximum Skew (100% Load)
0.8
0.9
ns
Note:
1. Delays based on 35 pF loading, except tENZL and tENZH . For tENZL and tENZH the loading is 5 pF.
v2.0
23
5 4 SX F a m ily F PG A s R a d To l e r a n t a n d Hi R e l
R T5 4S X 32 T i m i ng C ha r a ct er i s t i c s
(Worst-Case Military Conditions, V C CR = 4.75V, V CCA, V C CI = 3.0V, T J = 125 ° C)
C-Cell Propagation Delays1
Parameter
Description
tPD
Internal Array Module
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
1.7
1.8
ns
Predicted Routing Delays2
tDC
FO=1 Routing Delay, Direct Connect
0.2
0.2
ns
tFC
FO=1 Routing Delay, Fast Connect
1.1
1.3
ns
tRD1
FO=1 Routing Delay
1.3
1.5
ns
tRD2
FO=2 Routing Delay
2.2
2.6
ns
tRD3
FO=3 Routing Delay
3.1
3.6
ns
tRD4
FO=4 Routing Delay
4.0
4.7
ns
tRD8
FO=8 Routing Delay
7.8
9.0
ns
tRD12
FO=12 Routing Delay
10.1
11.9
ns
tRD18
FO=18 Routing Delay
17.0
19.8
ns
tRD24
FO=24 Routing Delay
22.4
26.3
ns
tRCO
Sequential Clock-to-Q
1.5
2.0
ns
tCLR
Asynchronous Clear-to-Q
1.5
2.0
ns
tSUD
Flip-Flop Data Input Set-Up
2.0
2.2
ns
tHD
Flip-Flop Data Input Hold
0.0
0.0
ns
tWASYN
Asynchronous Pulse Width
4.4
5.3
ns
R-Cell Timing
I/O Module Input Propagation Delays
tINYH
Input Data Pad-to-Y HIGH
4.0
4.7
ns
tINYL
Input Data Pad-to-Y LOW
4.0
4.7
ns
Predicted Input Routing
Delays3
tIRD1
FO=1 Routing Delay
1.3
1.5
ns
tIRD2
FO=2 Routing Delay
2.2
2.6
ns
tIRD3
FO=3 Routing Delay
3.1
3.6
ns
tIRD4
FO=4 Routing Delay
4.0
4.7
ns
tIRD8
FO=8 Routing Delay
7.8
9.0
ns
tIRD12
FO=12 Routing Delay
10.1
11.9
ns
tIRD18
FO=18 Routing Delay
17.0
19.8
ns
tIRD24
FO=24 Routing Delay
22.4
26.3
ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
24
v2.0
5 4 SX F a m ily F P GA s R a d T o le r a n t a n d H iR e l
R T5 4S X 32 T i m i ng C ha r a ct er i s t i c s (continued)
(Worst-Case Military Conditions, V C CR = 4.75V, V CCA, V C CI = 3.0V, T J = 125 ° C)
I/O Module – TTL Output Timing1
Parameter
Description
tDLH
Data-to-Pad LOW to HIGH
tDHL
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
5.1
6.0
ns
Data-to-Pad HIGH to LOW
5.1
6.0
ns
tENZL
Enable-to-Pad, Z to L
4.2
5.1
ns
tENZH
Enable-to-Pad, Z to H
5.1
6.0
ns
tENLZ
Enable-to-Pad, L to Z
8.1
9.4
ns
tENHZ
Enable-to-Pad, H to Z
4.0
4.7
ns
dTLH
Delta LOW to HIGH
0.09
0.11
ns/pF
dTHL
Delta HIGH to LOW
0.09
0.15
ns/pF
Input LOW to HIGH
(Pad to R-Cell Input)
3.1
3.6
ns
Input HIGH to LOW
(Pad to R-Cell Input)
3.5
4.0
ns
Dedicated (Hard-Wired) Array Clock Network
tHCKH
tHCKL
tHPWH
Minimum Pulse Width HIGH
3.8
4.4
ns
tHPWL
Minimum Pulse Width LOW
3.8
4.4
ns
tHCKSW
Maximum Skew
tHP
Minimum Period
fHMAX
Maximum Frequency
0.8
7.6
0.8
8.9
ns
ns
130
110
MHz
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
4.4
5.3
ns
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
4.9
5.6
ns
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
5.3
6.0
ns
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
5.3
6.3
ns
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
5.1
6.0
ns
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
5.3
6.3
ns
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
tRPWH
Min. Pulse Width HIGH
5.6
6.7
ns
tRPWL
Min. Pulse Width LOW
5.6
6.7
ns
tRCKSW
Maximum Skew (Light Load)
1.1
1.5
ns
tRCKSW
Maximum Skew (50% Load)
1.5
1.7
ns
tRCKSW
Maximum Skew (100% Load)
1.5
1.7
ns
Note:
1. Delays based on 35 pF loading, except tENZL and tENZH . For tENZL and tENZH the loading is 5 pF.
v2.0
25
5 4 SX F a m ily F PG A s R a d To l e r a n t a n d Hi R e l
Pi n D es c r i pt i on
CLKA,
CLKB
Clock A and B
These pins are clock inputs for clock distribution networks.
Input levels are compatible with standard TTL or LVTTL
specifications. The clock input is buffered prior to clocking
the R-cells. If not used, this pin must be set LOW or HIGH on
the board. It must not be left floating.
GND
Ground
LOW supply voltage.
HCLK
Dedicated (Hard-wired)
Array Clock
This pin is the clock input for sequential modules. Input
levels are compatible with standard TTL or LVTTL
specifications. This input is directly wired to each R-cell and
offers clock speeds independent of the number of R-cells
being driven. If not used, this pin must be set LOW or HIGH
on the board. It must not be left floating.
I/O
Input/Output
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Based on certain configurations, input
and output levels are compatible with standard TTL or
LVTTL specifications. Unused I/O pins are automatically
tristated by the Designer Series software.
NC
No Connection
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
PRA, I/O,
PRB, I/O
Probe A/B
The Probe pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin can be used in conjunction with the other probe pin to
allow real-time diagnostic output of any signal path within
the device. The Probe pin can be used as a user-defined I/O
when verification has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality.
TCK, I/O
TDI, I/O
Serial input for boundary scan testing and diagnostic probe.
In flexible mode, TDI is active when the TMS pin is set LOW
(refer to Table 2 on page 9). This pin functions as an I/O
when the boundary scan state machine reaches the “logic
reset” state.
TDO, I/O
Test Data Output
Serial output for boundary scan testing. In flexible mode,
TDO is active when the TMS pin is set LOW (refer to Table 2
on page 9). This pin functions as an I/O when the boundary
scan state machine reaches the “logic reset” state.
TMS
Test Mode Select
The TMS pin controls the use of the IEEE 1149.1 Boundary
Scan pins (TCK, TDI, TDO, TRST). In flexible mode when
the TMS pin is set LOW, the TCK, TDI, and TDO pins are
boundary scan pins (refer to Table 2 on page 9). Once the
boundary scan pins are in test mode, they will remain in that
mode until the internal boundary scan state machine
reaches the “logic reset” state. At this point, the boundary
scan pins will be released and will function as regular I/O
pins. The “logic reset” state is reached 5 TCK cycles after
the TMS pin is set HIGH. In dedicated test mode, TMS
functions as specified in the IEEE 1149.1 specifications.
TRST
Boundary Scan Reset Pin
The TRST pin functions as an active-low input to
asynchronously initialize or reset the boundary scan circuit.
The TRST pin is equipped with an internal pull-up resistor.
V C CI
Supply Voltage
Supply voltage for I/Os. See Table 1 on page 8.
V C CA
Supply Voltage
Supply voltage for Array. See Table 1 on page 8.
V C CR
Supply Voltage
Supply voltage for input tolerance (required for internal
biasing). See Table 1 on page 8.
Test Clock (Input)
Test clock input for diagnostic probe and device
programming. In flexible mode, TCK becomes active when
the TMS pin is set LOW (see Table 2 on page 9). This pin
functions as an I/O when the JTAG state machine reaches
the “logic reset “ state.
26
Test Data Input
v2.0
5 4 SX F a m ily F P GA s R a d T o le r a n t a n d H iR e l
P a c ka ge P i n A s si g nm e n t s
208-Pin CQFP (Top View)
208 207 206 205 204 203 202 201 200
164 163 162 161 160 159 158 157
Pin #1
Index
1
156
2
155
3
154
4
153
5
152
6
151
7
150
8
149
208-Pin
CQFP
44
113
45
112
46
111
47
110
48
109
49
108
50
107
51
106
52
105
53 54 55 56 57 58 59 60 61
97 98 99 100 101 102 103 104
v2.0
27
5 4 SX F a m ily F PG A s R a d To l e r a n t a n d Hi R e l
208- P in CQF P
Pin
Number
A54SX16
Function
RT54SX16
Function
A54SX32
Function
1
GND
GND
GND
2
TDI, I/O
TDI, I/O
TDI, I/O
3
I/O
I/O
I/O
4
I/O
I/O
I/O
5
I/O
I/O
I/O
6
I/O
I/O
I/O
7
I/O
I/O
I/O
8
I/O
I/O
I/O
9
I/O
I/O
I/O
10
I/O
I/O
I/O
11
TMS
TMS
TMS
12
VCCI
VCCI
VCCI
13
I/O
I/O
I/O
14
I/O
I/O
I/O
15
I/O
I/O
I/O
16
I/O
I/O
I/O
17
I/O
I/O
I/O
18
I/O
I/O
I/O
19
I/O
I/O
I/O
20
I/O
I/O
I/O
21
I/O
I/O
I/O
22
I/O
I/O
I/O
23
I/O
I/O
I/O
24
I/O
I/O
I/O
25
VCCR
VCCR
VCCR
26
GND
GND
GND
27
VCCA
VCCA
VCCA
28
GND
GND
GND
29
I/O
I/O
I/O
30
I/O
TRST
I/O
31
I/O
I/O
I/O
32
I/O
I/O
I/O
33
I/O
I/O
I/O
34
I/O
I/O
I/O
35
I/O
I/O
I/O
36
I/O
I/O
I/O
37
I/O
I/O
I/O
38
I/O
I/O
I/O
39
I/O
I/O
I/O
40
VCCI
VCCI
VCCI
41
VCCA
VCCA
VCCA
42
I/O
I/O
I/O
43
I/O
I/O
I/O
44
I/O
I/O
I/O
45
I/O
I/O
I/O
46
I/O
I/O
I/O
47
I/O
I/O
I/O
48
I/O
I/O
I/O
49
I/O
I/O
I/O
50
I/O
I/O
I/O
51
I/O
I/O
I/O
52
GND
GND
GND
Notes:
1.
Pin 30 in RT54SX16 and RT54SX32-CQ208 are TRST pins.
2.
Pin 65 in A54SX32 and RT54SX32-CQ208 are No Connects.
28
RT54SX32
Function
Pin
Number
A54SX16
Function
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
GND
TDI, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TMS
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCR
GND
VCCA
GND
I/O
TRST
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
GND
VCCA
GND
VCCR
I/O
HCLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
TDO, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
GND
VCCA
GND
VCCR
I/O
HCLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
TDO, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
GND
VCCA
GND
VCCR
I/O
HCLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
TDO, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
GND
VCCA
GND
VCCR
I/O
HCLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
TDO, I/O
I/O
v2.0
5 4 SX F a m ily F P GA s R a d T o le r a n t a n d H iR e l
208- P in CQF P (Co nti nue d)
Pin
Number
A54SX16
Function
RT54SX16
Function
A54SX32
Function
105
GND
GND
GND
106
I/O
I/O
I/O
107
I/O
I/O
I/O
108
I/O
I/O
I/O
109
I/O
I/O
I/O
110
I/O
I/O
I/O
111
I/O
I/O
I/O
112
I/O
I/O
I/O
113
I/O
I/O
I/O
VCCA
VCCA
114
VCCA
115
VCCI
VCCI
VCCI
116
I/O
I/O
I/O
117
I/O
I/O
I/O
118
I/O
I/O
I/O
119
I/O
I/O
I/O
120
I/O
I/O
I/O
121
I/O
I/O
I/O
122
I/O
I/O
I/O
123
I/O
I/O
I/O
124
I/O
I/O
I/O
125
I/O
I/O
I/O
126
I/O
I/O
I/O
127
I/O
I/O
I/O
128
I/O
I/O
I/O
129
GND
GND
GND
VCCA
VCCA
130
VCCA
131
GND
GND
GND
132
VCCR
VCCR
VCCR
133
I/O
I/O
I/O
134
I/O
I/O
I/O
135
I/O
I/O
I/O
136
I/O
I/O
I/O
137
I/O
I/O
I/O
138
I/O
I/O
I/O
139
I/O
I/O
I/O
140
I/O
I/O
I/O
141
I/O
I/O
I/O
142
I/O
I/O
I/O
143
I/O
I/O
I/O
144
I/O
I/O
I/O
145
VCCA
VCCA
VCCA
146
GND
GND
GND
147
I/O
I/O
I/O
148
VCCI
VCCI
VCCI
149
I/O
I/O
I/O
150
I/O
I/O
I/O
151
I/O
I/O
I/O
152
I/O
I/O
I/O
153
I/O
I/O
I/O
154
I/O
I/O
I/O
155
I/O
I/O
I/O
156
I/O
I/O
I/O
Notes:
1.
Pin 30 in RT54SX16 and RT54SX32-CQ208 are TRST pins.
2.
Pin 65 in A54SX32 and RT54SX32-CQ208 are No Connects.
RT54SX32
Function
Pin
Number
A54SX16
Function
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCCA
GND
VCCR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
GND
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLKA
CLKB
VCCR
GND
VCCA
GND
PRA, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
TCK, I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLKA
CLKB
VCCR
GND
VCCA
GND
PRA, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
TCK, I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLKA
CLKB
VCCR
GND
VCCA
GND
PRA, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
TCK, I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLKA
CLKB
VCCR
GND
VCCA
GND
PRA, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
TCK, I/O
v2.0
29
5 4 SX F a m ily F PG A s R a d To l e r a n t a n d Hi R e l
Pa c ka ge P i n A s si g nm e n t s (continued)
256- P in CQF P (T op Vie w)
256 255 254 253 252 251 250 249 248
200 199 198 197 196 195 194 193
Pin #1
Index
1
192
2
191
3
190
4
189
5
188
6
187
7
186
8
185
256-Pin
CQFP
56
137
57
136
58
135
59
134
60
133
61
132
62
131
63
130
64
129
65 66 67 68 69 70 71 72 73
30
121 122 123 124 125 126 127 128
v2.0
5 4 SX F a m ily F P GA s R a d T o le r a n t a n d H iR e l
256- P in CQF P
Pin
Number
A54SX16
Function
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
Pin
Number
A54SX16
Function
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
GND
TDI, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TMS
NC
NC
I/O
I/O
NC
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
GND
VCCA
GND
NC
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
VCCA
I/O
NC
I/O
I/O
NC
I/O
GND
TDI, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TMS
NC
NC
I/O
I/O
NC
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
GND
VCCA
GND
NC
I/O
TRST
I/O
NC
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
VCCA
I/O
NC
I/O
I/O
NC
I/O
GND
TDI, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TMS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
GND
VCCA
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
GND
TDI, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TMS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
GND
VCCA
GND
I/O
I/O
TRST
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
I/O
NC
I/O
I/O
NC
I/O
GND
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
GND
VCCI
GND
VCCA
I/O
HCLK
I/O
NC
I/O
I/O
I/O
NC
I/O
I/O
I/O
NC
I/O
I/O
NC
I/O
GND
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
GND
VCCI
GND
VCCA
I/O
HCLK
I/O
NC
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
GND
VCCI
GND
VCCA
I/O
HCLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
GND
VCCI
GND
VCCA
I/O
HCLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Note:
1. Pin 34 in RT54SX16 and RT54SX32-CQ256 are TRST pins.
v2.0
31
5 4 SX F a m ily F PG A s R a d To l e r a n t a n d Hi R e l
256- P in CQF P
Pin
Number
A54SX16
Function
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
Pin
Number
A54SX16
Function
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
I/O
NC
I/O
I/O
I/O
GND
I/O
I/O
I/O
NC
I/O
I/O
I/O
NC
I/O
I/O
I/O
NC
I/O
I/O
NC
TDO, I/O
NC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
I/O
NC
I/O
I/O
I/O
GND
I/O
I/O
I/O
NC
I/O
I/O
I/O
NC
I/O
I/O
I/O
NC
I/O
I/O
NC
TDO, I/O
NC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO, I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO, I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
GND
VCCR
GND
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
GND
GND
I/O
NC
I/O
I/O
NC
I/O
I/O
NC
I/O
I/O
NC
I/O
GND
I/O
NC
NC
I/O
I/O
NC
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
NC
I/O
I/O
I/O
NC
I/O
I/O
GND
VCCR
GND
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
GND
GND
I/O
NC
I/O
I/O
NC
I/O
I/O
NC
I/O
I/O
NC
I/O
GND
I/O
NC
NC
I/O
I/O
NC
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
NC
I/O
I/O
I/O
NC
I/O
I/O
GND
VCCR
GND
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCCR
GND
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Note:
1. Pin 34 in RT54SX16 and RT54SX32-CQ256 are TRST pins.
32
v2.0
5 4 SX F a m ily F P GA s R a d T o le r a n t a n d H iR e l
256- P in CQF P
Pin
Number
A54SX16
Function
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
Pin
Number
A54SX16
Function
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLKA
CLKB
VCCI
GND
VCCR
GND
PRA, I/O
I/O
NC
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLKA
CLKB
VCCI
GND
VCCR
GND
PRA, I/O
I/O
NC
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLKA
CLKB
VCCI
GND
VCCR
GND
PRA, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLKA
CLKB
VCCI
GND
VCCR
GND
PRA, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
I/O
I/O
NC
I/O
I/O
NC
GND
I/O
I/O
NC
I/O
I/O
I/O
NC
I/O
I/O
NC
I/O
I/O
NC
I/O
I/O
TCK, I/O
I/O
I/O
NC
I/O
I/O
NC
GND
I/O
I/O
NC
I/O
I/O
I/O
NC
I/O
I/O
NC
I/O
I/O
NC
I/O
I/O
TCK, I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK, I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK, I/O
Note:
1. Pin 34 in RT54SX16 and RT54SX32-CQ256 are TRST pins.
v2.0
33
5 4 SX F a m ily F PG A s R a d To l e r a n t a n d Hi R e l
L i s t o f C ha ng e s
The following table lists critical changes that were made in the current version of the document.
Previous version
Preliminary v1.5
Changes in current version (Preliminary v 1.5.1 (web-only))
Power up and down sequencing information was modified: damage to the device is
possible when 3.3V is powered up first and when 5.0V is powered down first.
Page
13
The last line of equation 2 was cut off in the previous version. It has been replaced in
14
the existing version.
The User I/Os changed.
1, 2, 3
The following sections are new or were updated: Clock Resources , Performance ,
I/O Modules , Power Requirements , Boundary Scan Testing (BST) , and Configuring
Diagnostic Pins , TRST pin , Dedicated Test Mode , and Flexible Mode ,
8-10
Development Tool Support , RT54SX Probe Circuit Control Pins , and Design
Preliminary v1.5.2 Considerations .
The “Pin Description” on page 26 has been updated.
26
Note that the “Package Characteristics and Mechanical Drawings” section has been
eliminated from the data sheet. The mechanical drawings are now contained in a
separate document, “Package Characteristics and Mechanical Drawings,” available
on the Actel web site.
D at a S he et Ca t e g o r i e s
In order to provide the latest information to designers, some data sheets are published before data has been fully
characterized. These data sheets are marked as “Advanced” or Preliminary” data sheets. The definition of these categories
are as follows:
Adv anc ed
The data sheet contains initial estimated information based on simulation, other products, devices, or speed grades. This
information can be used as estimates, but not for production.
P rel im i nar y
The data sheet contains information based on simulation and/or initial characterization. The information is believed to be
correct, but changes are possible.
Unm ar ked (pr odu ct ion)
The data sheet contains information that is considered to be final.
34
v2.0
5 4 SX F a m ily F P GA s R a d T o le r a n t a n d H iR e l
v2.0
35
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
http://www.actel.com
Actel Europe Ltd.
Maxfli Court, Riverside Way
Camberly, Surrey GU15 3YL
United Kingdom
Tel: +44 (0)1256 305600
Fax: +44 (0)1256 355420
Actel Corporation
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Sunnyvale, California 94086
USA
Tel: (408) 739-1010
Fax: (408) 739-1540
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EXOS Ebisu Bldg. 4F
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Tokyo 150 Japan
Tel: +81 03-3445-7671
Fax: +81 03-3445-7668
5172136-8/3.01