April 2000 Advance information AS7C3128PFD32A AS7C3128PFD36A ® 3.3V 128K × 32/36 pipeline burst synchronous SRAM • Organization: 32,768 words × 16 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4/5 ns • Fast OE access time: 3.5/3.5/3.8/5 ns • Fully synchronous operation • “Flow-through” mode • Double-cycle deselect - Single-cycle deselect also available (AS7C3128PFS36A/ AS7C3128PFS32A) • Pentium® -compatible architecture and timing • Synchronous and asynchronous output enable control • Economical 100-pin TQFP package • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • Automatic power down: 30 mW typical standby power • NTD™ pipeline architecture available (AS7C3128NTD36A/ AS7C3128NTD32A) LBO CLK Burst logic CLR 18 A[17:0] D Q CE CLK GWE BWE BWd D Q D Q D Q D Q DQc Byte Write registers CLK DQb Byte Write registers CLK BWb DQa Byte Write registers CLK BWa 16 256K×32/36 Memory array 18 Address register DQd Byte Write registers CLK BWc Q1 18 A6 A7 CE0 CE1 BWd BWc BWb BWa CE2 VDD VSS CLK GWE BWE OE ADSC ADSP ADV A8 A9 Q0 CE 36/32 DQPc/NC DQc DQc VDDQ VSSQ DQc DQc DQc DQc VSSQ VDDQ DQc DQc FT VDD NC VSS DQd DQd VDDQ VSSQ DQd DQd DQd DQd VSSQ VDDQ DQd DQd DQPd/NC 36/32 4 CE0 D CE2 Enable register Q OE Output registers CE CLK Power down Enable delay register CLK Input registers CLK Q DQPb/NC DQb DQb VDDQ VSSQ DQb DQb DQb DQb VSSQ VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa DQa DQa VSSQ VDDQ DQa DQa DQPa/NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 D ZZ CLK LE TQFP 14x20mm 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 OE FT LBO A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 A16 CE1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 CLK ADV ADSC ADSP 36/32 DATA [35:0] [31:0] Note: Pins 1,30,51,80 are NC for ×32 AS7C3128PFD36A AS7C3128PFD36A AS7C3128PFD36A AS7C3128PFD36A Units Minimum cycle time 6 6.7 7.5 10 ns Maximum pipelined clock frequency 166.7 150 133.3 100 MHz Maximum pipelined clock access time 3.5 3.8 4 5 ns Maximum operating current 450 400 350 300 mA Maximum standby current 60 60 60 60 mA 5 5 5 mA Maximum CMOS standby current (DC) 5 NTD™ is a trademark of Alliance Semiconductor Corporation. Pentium® is a registered trademark of Intel Corporation. DID 11-20011-A. 6/8/00 ALLIANCE SEMICONDUCTOR 1 Advance information AS7C3128PFD32A AS7C3128PFD36A ® The AS7C3128PFD36A and AS7C3128PFD32A are high-performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM) devices organized as 32,768 words × 16 bits and incorporate a pipeline for highest frequency on any given technology. Timing for these devices is compatible with existing Pentium synchronous cache specifications. This architecture is suited for ASIC, DSP (TMS320C6X), and PowerPC-based systems in computing, datacomm, instrumentation, and telecommunications systems. Fast cycle times of 6/6.7/7.5/10 ns with clock access times (tCD) of 3.5/3.5/3.8/5 ns enable 167, 150, 133 and 100 MHz bus frequencies. Three chip enable inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses. Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register. When ADSP is sampled Low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when WE is sampled High, ADV is sampled Low, and both address strobes are High. Burst operation is selectable with the MODE input. With MODE unconnected or driven High, burst operations use a Pentium count sequence. With MODE driven LOW the device uses a linear count sequence, suitable for PowerPC and many other applications. Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is High, one or more bytes may be written by asserting BWE and the appropriate individual byte BW signal(s). BWn is ignored on the clock edge that samples ADSP Low, but is sampled on all subsequent clock edges. Output buffers are disabled when BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled Low. Address is incremented internally to the next burst of address if BWn and ADV are sampled Low. Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow. • ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC. • WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP High). • Master chip select CE0 blocks ADSP, but not ADSC. The AS7C3128PFD36A and AS7C3128PFD32A operate from a 3.3V supply. I/O’s use a separate power supply that can operate at 2.5V or 3.3V. These devices are available in a 100-pin 14×20 mm TQFP packaging. 1 Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN Address and control pins Vin = 0V 4 pF I/O capacitance CI/O I/O pins Vin = Vout = 0V 5 pF GWE BWE BWn Function L X X Write all Bytes H L L Write Byte(s)n H H X Read H L H Read Key: X = Don’t Care, L = Low, H = High 2 ALLIANCE SEMICONDUCTOR DID 11-20011-A. 6/8/00 AS7C3128PFD32A AS7C3128PFD36A Advance information ® Signal I/O Properties Description CLK I CLOCK Clock. All inputs except OE are synchronous to this clock. A0–A17 I SYNC Address. Sampled when all chip enables are active and ADSC or ADSP are asserted. DQ[a,b,c,d] I/O SYNC Data. Driven as output when the chip is enabled and OE is active. CE0 I SYNC Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive, ADSP is blocked. Refer to the SYNCHRONOUS TRUTH TABLE for more information. CE1, CE2 I SYNC Synchronous chip enables. Active HIGH and active Low, respectively. Sampled on clock edges when ADSC is active or when CE1 and ADSP are active. ADSP I SYNC Address strobe (processor). Asserted LOW to load a new address or to enter standby mode. ADSC I SYNC Address strobe (controller). Asserted LOW to load a new address or to enter standby mode. ADV I SYNC Burst advance. Asserted LOW to continue burst read/write. GWE I SYNC Global write enable. Asserted LOW to write all 36 bits. When High, BWE and BW[a:d] control write enable. BWE I SYNC Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a:d] inputs. BW[a,b,c,d] I SYNC Write enables. Used to control write of individual bytes when GWE = HIGH and BWE = Low. If any of BW[a:d] is active with GWE = HIGH and BWE = LOW the cycle is a write cycle. If all BW[a:d] are inactive, the cycle is a read cycle. OE I ASYNC Asynchronous output enable. I/O pins are driven when OE is active and the chip is synchronously enabled. LBO I STATIC default = HIGH Count mode. When driven High, count sequence follows Intel XOR convention. When driven Low, count sequence follows linear convention. This signal is internally pulled High. FT I STATIC default = HIGH Flow-through mode.When low, enables single register flow-through mode. Connect to VDD if unused or for pipelined operation. This signal is internally pulled High ZZ I ASYNC Sleep. Places device in low power mode; data is retained. Connect to GND if unused. Parameter Symbol Min Max Unit Power supply voltage relative to GND VDD, VDDQ –0.5 +4.6 V Input voltage relative to GND (input pins) VIN –0.5 VDD + 0.5 V Input voltage relative to GND (I/O pins) VIN –0.5 VDDQ + 0.5 V Power dissipation PD – 1.4 W DC output current IOUT – 50 mA Storage temperature (plastic) Tstg –65 +150 oC Temperature under bias Tbias –65 +150 o C NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to absolute maximum rating conditions may affect reliability. DID 11-20011-A. 6/8/00 ALLIANCE SEMICONDUCTOR 3 Advance information AS7C3128PFD32A AS7C3128PFD36A ® CE0 CE1 CE2 ADSP ADSC ADV WRITEn† OE Address accessed CLK H X X X L X X X NA L to H Deselect Hi-Z L L X L X X X X NA L to H Deselect Hi-Z L L X H L X X X NA L to H Deselect Hi-Z L X H L X X X X NA L to H Deselect Hi-Z L X H H L X X X NA L to H Deselect Hi-Z L H L L X X F L External L to H Begin read Hi-Z L H L L X X F H External L to H Begin read Hi-Z L H L H L X F L External L to H Begin read Hi-Z L H L H L X F H External L to H Begin read Hi-Z X X X H H L F L Next L to H Cont. read DQ X X X H H L F H Next L to H Cont. read Hi-Z X X X H H H F L Current L to H Suspend read DQ X X X H H H F H Current L to H Suspend read Hi-Z H X X X H L F L Next L to H Cont. read DQ H X X X H L F H Next L to H Cont. read Hi-Z H X X X H H F L Current L to H Suspend read DQ H X X X H H F H Current L to H Suspend read Hi-Z L H L H L X T X External L to H Begin write Hi-Z X X X H H L T X Next L to H Cont. write Hi-Z H X X X H L T X Next L to H Cont. write Hi-Z X X X H H H T H Current L to H Suspend write Hi-Z H X X X H H T H Current L to H Suspend write Hi-Z Operation DQ Key: X = Don’t Care, L = Low, H = High. †See Write enable truth table for more information. Parameter Supply voltage 3.3V I/O supply voltage 2.5V I/O supply voltage 4 Symbol Min Nominal Max VDD 3.135 3.3 3.465 GND 0.0 0.0 0.0 VDDQ 3.135 3.3 3.465 GNDQ 0.0 0.0 0.0 VDDQ 2.35 2.5 2.65 GNDQ 0.0 0.0 0.0 ALLIANCE SEMICONDUCTOR Unit V V V DID 11-20011-A. 6/8/00 AS7C3128PFD32A AS7C3128PFD36A Advance information ® Parameter Address and control pins Input voltages† I/O pins Ambient operating temperature Symbol Min VIH 2.0 * Nominal Max Unit – VDD + 0.3 VIL –0.5 – 0.8 VIH 2.0 – VDDQ + 0.3 – 0.8 – 70 VIL -0.5 TA 0 * V V °C * VIL min = -2.0V for pulse width less than 0.2 × t RC. † Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications. Description Conditions Thermal resistance (Junction to Ambient)* Thermal resistance (Junction to Top of Case)* Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. Symbol Typical Units 1-layer θJA 40 °C/W 4-layer θJA 22 °C/W θJC 8 °C/W Symbol Typical Units 1-layer θJA 40 °C/W 4-layer θJA 25 °C/W θJC 9 °C/W θJB 17 °C/W *This parameter is sampled. Description Conditions Junction to Ambient (airflow of 1m/s)* Junction to Top of Case* Junction to Bottom of Bumps* Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. *This parameter is sampled. -166 -150 -133 -100 Parameter Symbol Test conditions Input leakage current | ILI | VDD = Max, Vin = GND to VDD – 2 – 2 – 2 – 2 µA Output leakage current | ILO | OE ≥ VIH, VDD = Max, Vout = GND to VDD – 2 – 2 – 2 – 2 µA Operating power supply current ICC CE = VIL, CE = VIH, CE = VIL, f = fmax, Iout = 0 mA – 450 – 400 – 350 – 300 mA ISB Deselected, f = fmax – 90 – 80 – 70 – 60 ISB1 Deselected, f = 0, all VIN ≤ 0.2V or ≥ VDD - 0.2V – 5 – 5 – 5 – 5 VOL IOL = 8 mA, VDDQ = 3.465V – 0.4 – 0.4 – 0.4 – 0.4 VOH IOH = –4 mA, VDDQ = 3.135V 2.4 – 2.4 – 2.4 – 2.4 – Standby power supply current Output voltage DID 11-20011-A. 6/8/00 Min Max Min Max Min Max Min Max Unit ALLIANCE SEMICONDUCTOR mA V 5 Advance information AS7C3128PFD32A AS7C3128PFD36A ® -166 -150 -133 -100 Parameter Symbol Test conditions Output leakage current | ILO | OE ≥ VIH, VDD = Max, Vout = GND to VDD -1 1 -1 1 -1 1 -1 1 VOL IOL = 2 mA, V DDQ = 2.65V – 0.7 – 0.7 – 0.7 – 0.7 VOH IOH = –2 mA, V DDQ = 2.35V 1.7 – 1.7 – 1.7 – 1.7 – Output voltage Min Max Min Max Min Max Min Max Unit -3.5 Parameter Symbol Clock frequency -3.8 -4 µA V -5 Min Max Min Max Min Max Min Max Unit Notes FMAX - 166 - 150 - 133 - 100 MHz 1 Cycle time (pipelined mode) tCYC 6 - 6.6 - 7.5 - 10 - ns Cycle time (flow-through mode) tCYCF 10 - 10 - 12 - 15 - ns Clock access time (pipelined mode) tCD - 3.5 - 3.8 - 4.0 - 5.0 ns Clock access time (flow-through mode) tCDF - 8 - 8 - 9 - 12 ns Output enable Low to data valid tOE - 3.5 - 3.5 - 3.8 - 5.0 ns Clock High to output Low Z tLZC 0 - 0 - 0 - 0 - ns 8 Data output invalid from clock High tOH 1.5 - 1.5 - 1.5 - 1.5 - ns 8 Output enable Low to output Low Z tLZOE 0 - 0 - 0 - 0 - ns 8 Output enable High to output High Z tHZOE - 3.0 - 3.0 - 3.8 - 5.0 ns 8 Clock High to output High Z tHZC - 3.0 - 3.3 - 3.3 - 4.5 ns 8 Clock High to output High Z tHZCN - 1.5 - 1.5 - 2 - 2.5 ns 1,9 Clock High pulse width tCH 2.0 - 2.0 - 2.0 - 2.5 - ns Clock Low pulse width tCL 2.0 - 2.0 - 2.0 - 2.5 - ns Address and Control setup to clock High tAS 1.5 - 1.5 - 1.5 - 1.5 - ns Data setup to clock High tDS 1.5 - 1.5 - 1.5 - 1.5 - ns Write setup to clock High tWS 1.5 - 1.5 - 1.5 - 1.5 - ns Chip select setup to clock High tCSS 1.5 - 1.5 - 1.5 - 1.5 - ns Address hold from clock High tAH 0.5 - 0.5 - 0.5 - 0.5 - ns Data hold from clock High tDH 0.5 - 0.5 - 0.5 - 0.5 - ns Write hold from clock High tWH 0.5 - 0.5 - 0.5 - 0.5 - ns Chip select hold from clock High tCSH 0.5 - 0.5 - 0.5 - 0.5 - ns Output rise time (0 pF load) tR 1.5 - 1.5 - 1.5 - 1.5 - V/ns 1 Output fall time (0 pF load) tF 1.5 - 1.5 - 1.5 - 1.5 - V/ns 1 See “Notes” on page 10. Rising input 6 Falling input Undefined/don’t care ALLIANCE SEMICONDUCTOR DID 11-20011-A. 6/8/00 AS7C3128PFD32A AS7C3128PFD36A Advance information ® tCYC tCH tCL CLK tAS tAH ADSP tAS tAH ADSC tAS LOAD NEW ADDRESS tAH Address A1 A2 A3 tWS tWH GWE, BWE tCSS tCSH CE0, CE2 CE1 tAS tAH ADV OE tCD tHZOE tLZOE tOH tOE tLZC Q(A1) DOUT (pipelined mode) Q(A2) ADV INSERTS WAIT STATES tHZC Q(A2Ý01) Q(A2Ý10) Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11) tOE tLZOE Q(A1) DOUT Q(A2Ý01) Q(A2Ý10) Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11) (flow-through mode) tHZC tCDF Note: ⊕ = XOR when MODE = High/No Connect; ⊕ = ADD when MODE = Low. [0:3] is don’t care. DID 11-20011-A. 6/8/00 ALLIANCE SEMICONDUCTOR 7 Advance information AS7C3128PFD32A AS7C3128PFD36A ® tCYC tCH tCL CLK tAS tAH ADSP tAS tAH ADSC ADSC LOADS NEW ADDRESS tAS tAH Address A1 A3 A2 tWS tWH BWE, BWa,b,c,d tCSS tCSH CE0, CE2 CE1 tAS ADV SUSPENDS BURST tAH ADV OE tDS tDH Data In D(A1) D(A2) D(A2Ý01) D(A2Ý01) D(A2Ý10) D(A2Ý11) D(A3) D(A3Ý01) D(A3Ý10) Note: ⊕ = XOR when MODE = High/No Connect; ⊕ = ADD when MODE = Low. 8 ALLIANCE SEMICONDUCTOR DID 11-20011-A. 6/8/00 AS7C3128PFD32A AS7C3128PFD36A Advance information ® tCYC tCH tCL CLK tAS tAH ADSP tAS tAH Address A2 A1 A3 tWS tWH GWE CE0, CE2 CE1 tADVS tADVH ADV OE tAS tAH D(A2) DIN tLZC tHZOE tCD Q(A1) DOUT tOH tLZOE tOE Q(A3) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11) (pipeline mode) tCDF DOUT Q(A1) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11) (flow-through mode) Note: ⊕ = XOR when MODE = High/No Connect; ⊕ = ADD when MODE = Low. DID 11-20011-A. 6/8/00 ALLIANCE SEMICONDUCTOR 9 Advance information AS7C3128PFD32A AS7C3128PFD36A ® 1 2 3 4 5 This parameter is guaranteed but not tested. For test conditions, see AC Test Conditions, Figures A, B, C. This parameter is sampled and not 100% tested. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled. Typical values measured at 3.3V, 25°C and 10 ns cycle time. 6 7 8 9 ICC given with no output loading. I CC increases with faster cycle times and greater output loading. Transitions are measured ±500 mV from steady state voltage. Output loading specified with C L = 5 pF as in Figure C. tHZOE is less than tLZOE; and tHZC is less than tLZC at any given temperature and voltage. tHZCN is a‘no load’ parameter to indicate exactly when SRAM outputs have stopped driving. • Output Load: see Figure B. except for tLZC, tLZOE, tHZOE, tHZC see Figure C. • Input pulse level: GND to 3V. See Figure A. • Input rise and fall time (Measured at 0.3V and 2.7V): 2 ns. See Figure A. • Input and output timing reference levels: 1.5V. +3.0V 90% 10% GND Z0=50Ω Dout 90% 10% +3.3V 50Ω Dout VL=1.5V 30 pF* Figure A: Input waveform 351Ω 317Ω 5 pF* GND *including scope and jig capacitance Figure C: Output load(B) Figure B: Output load (A) Package Width 166 MHz 150 MHz 133 MHz 100 MHz TQFP ×32 AS7C3128PFD32A3.5TQC AS7C3128PFD32A3.8TQC AS7C3128PFD32A4TQC AS7C3128PFD32A5TQC TQFP ×36 AS7C3128-3.5TQC AS7C3128PFD36A3.8TQC AS7C3128PFD36A4TQC AS7C3128PFD36A5TQC AS7C 3 128 P D Timing SRAM Operating Part number Z=NTD™ prefix voltage P=PBSRAM 6/8/00 32/36 –XX XX Package: D = Double-cycle Access time TQ = Organization (ns) deselect TQFP ALLIANCE SEMICONDUCTOR C Commercial temperature, 0°C to 70 °C 10 Copyright ©2000 Alliance Semiconductor Corporation (Alliance)'s three-point logo, our name, and Intelliwatt™ are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. 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