CA3140 S E M I C O N D U C T O R BiMOS Operational Amplifier with MOSFET Input/Bipolar Output April 1994 Features Description • MOSFET Input Stage - Very High Input Impedance (ZIN) -1.5TΩ (Typ.) - Very Low Input Current (Il) -10pA (Typ.) at ±15V - Wide Common Mode Input Voltage Range (VlCR) - Can be Swung 0.5V Below Negative Supply Voltage Rail - Output Swing Complements Input Common Mode Range The CA3140A and CA3140 are integrated circuit operational amplifiers that combine the advantages of high voltage PMOS transistors with high voltage bipolar transistors on a single monolithic chip. Because of this unique combination of technologies, this device can now provide designers, for the first time, with the special performance features of the CA3130 CMOS operational amplifiers and the versatility of the 741 series of industry standard operational amplifiers. • Directly Replaces Industry Type 741 in Most Applications Applications • Ground-Referenced Single Supply Amplifiers in Automobile and Portable Instrumentation • Sample and Hold Amplifiers • Long Duration Timers/Multivibrators (µseconds-Minutes-Hours) • Photocurrent Instrumentation • Peak Detectors The CA3140A and CA3140 BiMOS operational amplifiers feature gate protected MOSFET (PMOS) transistors in the input circuit to provide very high input impedance, very low input current, and high speed performance. The CA3140A and CA3140 operate at supply voltage from 4V to 36V (either single or dual supply). These operational amplifiers are internally phase compensated to achieve stable operation in unity gain follower operation, and additionally, have access terminal for a supplementary external capacitor if additional frequency roll-off is desired. Terminals are also provided for use in applications requiring input offset voltage nulling. The use of PMOS field effect transistors in the input stage results in common mode input voltage capability down to 0.5V below the negative supply terminal, an important attribute for single supply applications. The output stage uses bipolar transistors and includes built-in protection against damage from load terminal short circuiting to either supply rail or to ground. • Comparators The CA3140 Series has the same 8-lead pinout used for the “741” and other industry standard op amps. The CA3140A and CA3140 are intended for operation at supply voltages up to 36V (±18V). • Interface in 5V TTL Systems and Other Low Supply Voltage Systems Ordering Information • Active Filters • All Standard Operational Amplifier Applications • Function Generators • Tone Controls TEMP. RANGE PACKAGE CA3140AE PART NUMBER -55oC to +125oC 8 Lead Plastic DIP CA3140AM -55oC to +125oC 8 Lead SOIC 8 Pin Can, Lead Formed CA3140AS -55o • Power Supplies CA3140AT -55oC to +125oC 8 Pin Can • Portable Instruments CA3140BT -55oC to +125oC 8 Pin Can CA3140E -55oC 8 Lead Plastic DIP CA3140M -55oC to +125oC 8 Lead SOIC CA3140M96 -55oC to +125oC 8 Lead SOIC* CA3140T -55oC 8 Pin Can • Intrusion Alarm Systems o C to +125 C to to +125oC +125oC * Denotes Tape and Reel Pinouts CA3140 (TO-5 STYLE CAN) TOP VIEW TAB CA3140 (PDIP, SOIC) TOP VIEW STROBE 8 OFFSET NULL 1 – + INV. 2 INPUT NON-INV. INPUT 7 3 V+ 6 OUTPUT 5 OFFSET NULL 4 V- AND CASE OFFSET NULL 1 INV. INPUT 2 NON-INV. INPUT 3 V- 4 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright © Harris Corporation 1993 2-123 – + 8 STROBE 7 V+ 6 OUTPUT 5 OFFSET NULL File Number 957.2 Specifications CA3140, CA3140A Absolute Maximum Ratings Operating Conditions DC Supply Voltage (Between V+ and V- Terminals). . . . . . . . . . 36V Differential Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 8V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . .(V+ +8V) To (V- -0.5V) Input Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Output Short Circuit Duration* . . . . . . . . . . . . . . . . . . . . . . Indefinite Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Junction Temperature (Plastic Package) . . . . . . . . . . . . . . . +150oC Lead Temperature (Soldering 10 Sec.). . . . . . . . . . . . . . . . . +300oC OperatingTemperature Range (All Types). . . . . . . . -55oC to +125oC Storage Temperature Range (All Types). . . . . . . . . -65oC to +150oC * Short circuit may be applied to ground or to either supply. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications V+ = +15V, V- = -15V, TA = +25oC PARAMETERS SYMBOL Input Offset Voltage Adjustment Resistor TEST CONDITIONS CA3140A CA3140 UNITS Typical Value of Resistor Between Term. 4 and 5 or 4 and 1 to Adjust Max. VI0 18 4.7 kΩ Input Resistance RI 1.5 1.5 TΩ Input Capacitance CI 4 4 pF Output Resistance RO 60 60 Ω Equivalent Wideband Input Noise Voltage (See Figure 35) eN BW = 140kHz RS = 1 MΩ 48 48 µV Equivalent Input Noise Voltage (See Figure 7) eN f = 1kHz 40 40 nV/√Hz 12 12 nV/√Hz f = 10 kHz RS = 100Ω Short Circuit Current to Opposite Supply Source IOM+ 40 40 mA Sink IOM- 18 18 mA fT 4.5 4.5 MHz SR 9 9 V/µs 220 220 µA Gain-Bandwidth Product, (See Figures 2 & 15) Slew Rate, (See Figure 3) Sink Current From Terminal 8 To Terminal 4 to Swing Output Low Transient Response: RL = 2kΩ CL = 100pF Rise Time tR 0.08 0.08 µs Overshoot (See Figure 34) OS 10 10 % 4.5 4.5 µs 1.4 1.4 µs Settling Time at 10 VP-P, (See Figure 14) 1mV tS RL = 2kΩ CL = 100pF Voltage Follower 10mV 2-124 Specifications CA3140, CA3140A For Equipment Design. At V+ = 15V, V- = 15V, TA = +25oC, Unless Otherwise Specified Electrical Specifications LIMITS CA3140A PARAMETERS CA3140 SYMBOL MIN TYP MAX MIN TYP MAX UNITS Input Offset Voltage |VIO| - 2 5 - 5 15 mV Input Offset Current |IIO| - 0.5 20 - 0.5 30 pA II - 10 40 - 10 50 pA AOL 20 l00 - 20 100 - kV/V 86 100 - 86 100 - dB - 32 320 - 32 320 µV/V 70 90 - 70 90 - dB VICR -15 -15.5 to +12.5 12 -15 -15.5 to +12.5 11 V PSRR - 100 150 - 100 150 µV/V 76 80 - 76 80 - dB VOM+ +12 13 - +12 13 - V VOM- -14 -14.4 - -14 -14.4 - V Supply Current (See Figure 4) I+ - 4 6 - 4 6 mA Device Dissipation PD - 120 180 - 120 180 mW - 6 - - 8 - µV/oC Input Current Large Signal Voltage Gain (Note 1) (See Figures 1, 15) Common Mode Rejection Ratio (See Figure 6) CMRR Common Mode Input Voltage Range (See Figure 17) Power-Supply Rejection Ratio, ∆VIO/∆VS (See Figure 8) Max. Output Voltage (Note 2) (See Figures 10, 17) Input Offset Voltage Temp. Drift, ∆VIO/∆T NOTES: 1. At VO = 26Vp-p, +12V, 14V and RL = 2kΩ. 2. At RL = 2kΩ. Electrical Specifications For Design Guidance. At V+ = 5 V, V- = 0V, TA = +25oC PARAMETERS SYMBOL CA3140A CA3140 UNITS Input Offset Voltage |VIO| 2 5 mV Input Offset Current |IIO| 0.1 0.1 pA Input Current II 2 2 pA Input Resistance RI 1 1 TΩ AOL 100 100 kV/V 100 100 dB Large Signal Voltage Gain (See Figures 1, 15) 2-125 Specifications CA3140, CA3140A Electrical Specifications For Design Guidance. At V+ = 5 V, V- = 0V, TA = +25oC (Continued) PARAMETERS SYMBOL CA3140A CA3140 UNITS CMRR 32 32 µV/V 90 90 dB -0.5 -0.5 V 2.6 2.6 V 100 100 µV/V 80 80 dB VOM+ 3 3 V VOM- 0.13 0.13 V Source IOM+ 10 10 mA Sink IOM- 1 1 mA SR 7 7 V/µs Gain-Bandwidth Product (See Figure 2) fT 3.7 3.7 MHz Supply Current (See Figure 4) I+ 1.6 1.6 mA Device Dissipation PD 8 8 mW 200 200 µA Common Mode Rejection Ratio, Common Mode Input Voltage Range (See Figure 17) Power Supply Rejection Ratio VICR PSRR ∆VI0/∆VS Maximum Output Voltage (See Figures 10, 17) Maximum Output Current: Slew Rate (See Figure 3) Sink Current from Term. 8 to Term. 4 to Swing Output Low 2-126 CA3140A, CA3140 Block Diagram 2mA 4mA 7 V+ BIAS CIRCUIT CURRENT SOURCES AND REGULATOR 200µA + 3 1.6mA 2µA A≈ 10,000 A ≈ 10 INPUT 2 200µA 2mA A≈1 6 OUTPUT C1 12pF 5 1 4 V8 STROBE OFFSET NULL Schematic Diagram BIAS CIRCUIT INPUT STAGE SECOND STAGE OUTPUT STAGE DYNAMIC CURRENT SINK 7 V+ C1 D7 Q1 Q6 Q2 Q3 Q5 Q4 Q20 R9 50Ω D8 R10 1k Q19 R11 20Ω Q7 R1 8k R13 5k R12 12k Q21 Q17 R8 1k Q8 R14 20k Q18 6 OUTPUT D2 D3 D4 D5 INVERTING INPUT 2 NON-INVERTING INPUT 3 + Q9 Q10 C1 R2 500Ω R3 500Ω 12pF Q15 Q14 Q11 R4 500Ω Q12 D6 R5 500Ω 5 R6 50Ω 1 OFFSET NULL Q16 Q13 R7 30Ω 8 4 STROBE V- ALL RESISTANCE VALUES ARE IN Ω 2-127 CA3140A, CA3140 Circuit Description As shown in the block diagram, the input terminals may be operated down to 0.5V below the negative supply rail. Two class A amplifier stages provide the voltage gain, and a unique class AB amplifier stage provides the current gain necessary to drive low-impedance loads. A biasing circuit provides control of cascoded constant current flow circuits in the first and second stages. The CA3140 includes an on chip phase compensating capacitor that is sufficient for the unity gain voltage follower configuration. Input Stages The schematic diagram consists of a differential input stage using PMOS field-effect transistors (Q9, Q10) working into a mirror pair of bipolar transistors (Q11, Q12) functioning as load resistors together with resistors R2 through R5. The mirror pair transistors also function as a differential-to-singleended converter to provide base current drive to the second stage bipolar transistor (Q13). Offset nulling, when desired, can be effected with a 10kΩ potentiometer connected across terminals 1 and 5 and with its slider arm connected to terminal 4. Cascode connected bipolar transistors Q2, Q5 are the constant current source for the input stage. The base biasing circuit for the constant current source is described subsequently. The small diodes D3, D4, D5 provide gate oxide protection against high voltage transients, e.g., static electricity. Second Stage Most of the voltage gain in the CA3140 is provided by the second amplifier stage, consisting of bipolar transistor Q13 and its cascode connected load resistance provided by bipolar transistors Q3, Q4. On-chip phase compensation, sufficient for a majority of the applications is provided by C1. Additional Miller-Effect compensation (roll off) can be accomplished, when desired, by simply connecting a small capacitor between terminals 1 and 8. Terminal 8 is also used to strobe the output stage into quiescence. When terminal 8 is tied to the negative supply rail (terminal 4) by mechanical or electrical means, the output terminal 6 swings low, i.e., approximately to terminal 4 potential. Output Stage The CA3140 Series circuits employ a broad band output stage that can sink loads to the negative supply to complement the capability of the PMOS input stage when operating near the negative rail. Quiescent current in the emitter-follower cascade circuit (Q17, Q18) is established by transistors (Q14, Q15) whose base currents are “mirrored” to current flowing through diode D2 in the bias circuit section. When the CA3140 is operating such that output terminal 6 is sourcing current, transistor Q18 functions as an emitterfollower to source current from the V+ bus (terminal 7), via D7, R9, and R11. Under these conditions, the collector potential of Q13 is sufficiently high to permit the necessary flow of base current to emitter follower Q17 which, in turn, drives Q18. When the CA3140 is operating such that output terminal 6 is sinking current to the V- bus, transistor Q16 is the current sinking element. Transistor Q16 is mirror connected to D6, R7, with current fed by way of Q21, R12, and Q20. Transistor Q20, in turn, is biased by current flow through R13, zener D8, and R14. The dynamic current sink is controlled by voltage level sensing. For purposes of explanation, it is assumed that output terminal 6 is quiescently established at the potential midpoint between the V+ and V- supply rails. When output current sinking mode operation is required, the collector potential of transistor Q13 is driven below its quiescent level, thereby causing Q17, Q18 to decrease the output voltage at terminal 6. Thus, the gate terminal of PMOS transistor Q21 is displaced toward the V- bus, thereby reducing the channel resistance of Q21. As a consequence, there is an incremental increase in current flow through Q20, R12, Q21, D6, R7, and the base of Q16. As a result, Q16 sinks current from terminal 6 in direct response to the incremental change in output voltage caused by Q18. This sink current flows regardless of load; any excess current is internally supplied by the emitter-follower Q18. Short circuit protection of the output circuit is provided by Q19, which is driven into conduction by the high voltage drop developed across R11 under output short circuit conditions. Under these conditions, the collector of Q19 diverts current from Q4 so as to reduce the base current drive from Q17, thereby limiting current flow in Q18 to the short circuited load terminal. Bias Circuit Quiescent current in all stages (except the dynamic current sink) of the CA3140 is dependent upon bias current flow in R1. The function of the bias circuit is to establish and maintain constant current flow through D1, Q6, Q8 and D2. D1 is a diode connected transistor mirror connected in parallel with the base emitter junctions of Q1, Q2, and Q3. D1 may be considered as a current sampling diode that senses the emitter current of Q6 and automatically adjusts the base current of Q6 (via Q1) to maintain a constant current through Q6, Q8, D2. The base currents in Q2, Q3 are also determined by constant current flow D1. Furthermore, current in diode connected transistor Q2 establishes the currents in transistors Q14 and Q15. 2-128 CA3140, CA3140A Metallization Mask Layout 0 10 20 30 40 50 60 65 61 60 50 40 58-66 (1.473-1.676) 30 20 10 0 4-10 (0.102-0.254) 62-70 (1.575-1.778) Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). The photographs and dimensions represent a chip when it is part of the wafer. When the wafer is cut into chips, the cleavage angles are 57o instead of 90ο with respect to the face of the chip. Therefore, the isolated chip is actually 7 mils (0.17mm) larger in both dimensions. Typical Performance Curves 20 GAIN BANDWIDTH PRODUCT (MHz) OPEN-LOOP VOLTAGE GAIN (dB) RL = 2kΩ TA = -55oC +25oC 125 +125oC 100 75 50 25 0 0 5 10 15 SUPPLY VOLTAGE (V) 20 25 FIGURE 1. OPEN LOOP VOLTAGE GAIN vs SUPPLY VOLTAGE AND TEMPERATURE RL = 2kΩ CL = 100pF 10 8 +25oC 6 +125oC TA = -55oC 5 4 3 2 1 0 5 10 15 SUPPLY VOLTAGE (V) 20 FIGURE 2. GAIN BANDWIDTH PRODUCT vs SUPPLY VOLTAGE AND TEMPERATURE 2-129 25 CA3140, CA3140A Typical Performance Curves (Continued) RL = ∞ QUIESCENT SUPPLY CURRENT (mA) SLEW RATE (V/µs) RL = 2kΩ CL = 100pF +25oC +125oC TA = -55oC 20 15 10 5 0 0 5 10 15 SUPPLY VOLTAGE (V) FIGURE 3. SLEW RATE vs SUPPLY VOLTAGE AND TEMPERATURE COMMON-MODE REJECTION RATIO (dB) OUTPUT SWING (VP-P) 25 20 15 10 5 2 4 10K 6 8 2 4 6 100K FREQUENCY (Hz) 8 +25oC 4 3 2 1 4M POWER SUPPLY REJECTION RATIO (dB) EQUIVALENT INPUT NOISE VOLTAGE (nV√Hz) 100 8 6 4 2 10 8 6 4 2 101 102 103 FREQUENCY (Hz) 20 25 100 80 CA3140B 60 CA3140, CA3140A 40 20 102 103 104 105 106 107 FIGURE 6. COMMON MODE REJECTION RATIO vs FREQUENCY 2 1 10 15 SUPPLY VOLTAGE (V) FREQUENCY (Hz) SUPPLY VOLTAGE: V+ = 15V, V- = -15V TA = +25oC 1 5 120 SUPPLY VOLTAGE: V+ = 15V, V- = -15V TA = +25oC 1000 4 0 0 101 2 1M FIGURE 5. MAXIMUM OUTPUT VOLTAGE SWING vs FREQUENCY 8 6 +125oC 5 FIGURE 4. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE AND TEMPERATURE SUPPLY VOLTAGE: V+ = 15V, V- = -15V TA = +25oC 0 TA = -55oC 6 0 25 20 7 104 FIGURE 7. EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY SUPPLY VOLTAGE: V+ = 15V, V- = -15V TA = +25oC 100 CA3140B 80 CA3140A 60 40 -PSRR 20 POWER SUPPLY REJECTION RATIO (PSRR) = ∆VIO/∆VS 0 101 105 +PSRR CA3140, 102 103 104 105 106 107 FREQUENCY (Hz) FIGURE 8. POWER SUPPLY REJECTION RATIO vs FREQUENCY 2-130 CA3140, CA3140A Applications Considerations Wide dynamic range of input and output characteristics with the most desirable high input impedance characteristics is achieved in the CA3140 by the use of an unique design based upon the PMOS Bipolar process. Input common mode voltage range and output swing capabilities are complementary, allowing operation with the single supply down to 4V. The wide dynamic range of these parameters also means that this device is suitable for many single supply applications, such as, for example, where one input is driven below the potential of terminal 4 and the phase sense of the output signal must be maintained – a most important consideration in comparator applications. Figure 10 shows output current sinking capabilities of the CA3140 at various supply voltages. Output voltage swing to the negative supply rail permits this device to operate both power transistors and thyristors directly without the need for level shifting circuitry usually associated with the 741 series of operational amplifiers. Figure 13 shows some typical configurations. Note that a series resistor, RL, is used in both cases to limit the drive available to the driven device. Moreover, it is recommended that a series diode and shunt diode be used at the thyristor input to prevent large negative transient surges that can appear at the gate of thyristors, from damaging the integrated circuit. Output Circuit Considerations 7 OFFSET-VOLTAGE SHIFT (mV) Excellent interfacing with TTL circuitry is easily achieved with a single 6.2V zener diode connected to terminal 8 as shown in Figure 9. This connection assures that the maximum output signal swing will not go more positive than the zener voltage minus two base-to-emitter voltage drops within the CA3140. These voltages are independent of the operating supply voltage. V+ 5V TO 36V LOGIC SUPPLY 5V 7 8 2 6.2V 6 DIFFERENTIAL DC VOLTAGE (ACROSS TERMS 2 AND 3) = 2V OUTPUT STAGE TOGGLED 5 4 3 2 DIFFERENTIAL DC VOLTAGE (ACROSS TERMS 2 AND 3) = 0V OUTPUT VOLTAGE = V+ / 2 1 0 ≈5V 6 CA3140 TA = +125oC FOR TO-5 PACKAGES 0 500 1000 1500 2000 2500 3000 3500 4000 4500 TYPICAL TTL GATE TIME (HOURS) 3 4 FIGURE 11. TYPICAL INCREMENTAL OFFSET VOLTAGE SHIFT vs OPERATING LIFE Offset Voltage Nulling FIGURE 9. ZENER CLAMPING DIODE CONNECTED TO TERMINALS 8 AND 4 TO LIMIT CA3140 OUTPUT SWING TO TTL LEVELS OUTPUT STAGE TRANSISTOR (Q15, Q16) SATURATION VOLTAGE (mV) 1000 8 6 4 SUPPLY VOLTAGE (V-) = 0V TA = +25oC 2 100 SUPPLY VOLTAGE (V+) = +5V +15V 8 6 An alternate system is shown in Figure 12(C). This circuit uses only one additional resistor of approximately the value shown in the table. For potentiometers, in which the resistance does not drop to zero Ω at either end of rotation, a value of resistance 10% lower than the values shown in the table should be used. +30V 4 2 10 The input offset voltage can be nulled by connecting a 10kΩ potentiometer between terminals 1 and 5 and returning its wiper arm to terminal 4, see Figure 12(A). This technique, however, gives more adjustment range than required and therefore, a considerable portion of the potentiometer rotation is not fully utilized. Typical values of series resistors that may be placed at either end of the potentiometer, see Figure 12(B), to optimize its utilization range are given in the table “Electrical Specifications” shown in this bulletin. 8 6 4 Low Voltage Operation 2 1 0.01 2 4 6 8 0.1 2 4 6 8 2 1.0 4 6 8 10 LOAD (SINKING) CURRENT (mA) FIGURE 10. VOLTAGE ACROSS OUTPUT TRANSISTORS Q15 AND Q16 vs LOAD CURRENT Operation at total supply voltages as low as 4V is possible with the CA3140. A current regulator based upon the PMOS threshold voltage maintains reasonable constant operating current and hence consistent performance down to these lower voltages. The low voltage limitation occurs when the upper extreme of the input common mode voltage range extends down to the 2-131 CA3140, CA3140A V+ 2 V+ 2 7 CA3140 3 2 7 3 3 4 5 1 5 1 10kΩ 6 CA3140 4 5 7 6 CA3140 6 4 V+ 1 10kΩ 10kΩ V- VV- (A) BASIC (B) IMPROVED RESOLUTION (C) SIMPLER IMPROVED RESOLUTION FIGURE 12. THREE OFFSET VOLTAGE NULLING METHODS V+ RS 2 LOAD 30V NO LOAD 120VAC LOAD 6 CA3140 MT2 7 +HV 7 RL 2 3 4 6 CA3140 MT1 RL 3 4 FIGURE 13. METHODS OF UTILIZING THE VCE(SAT) SINKING CURRENT CAPABILITY OF THE CA3140 SERIES FOLLOWER +15V 7 0.1µF 3 LOAD RESISTANCE (RL) = 2kΩ LOAD CAPACITANCE (CL) = 100pF CA3140 SUPPLY VOLTAGE: V+ = +15V, V- = -15V TA = +25oC 6 2kΩ 100pF 2 4 0.1µF 10 1mV 1mV -15V 8 INPUT VOLTAGE (V) SIMULATED LOAD 10kΩ 10mV 6 10mV 2kΩ 4 0.05µF 2 FOLLOWER 0 INVERTING INVERTING -2 5kΩ -4 +15V -6 1mV -8 -10 0.1 10mV 2 4 6 1mV 7 10mV 8 2 1.0 SETTLING TIME (µs) 0.1µF 2 4 6 8 SIMULATED LOAD 5kΩ 10 CA3140 200Ω 6 100pF 3 4 (A) 0.1µF 4.99kΩ 5.11kΩ -15V SETTLING POINT D1 IN914 D2 IN914 (B) TEST CIRCUITS FIGURE 14. INPUT VOLTAGE vs SETTLING TIME 2-132 2kΩ CA3140, CA3140A voltage at terminal 4. This limit is reached at a total supply voltage just below 4V. The output voltage range also begins to extend down to the negative supply rail, but is slightly higher than that of the input. Figure 17 shows these characteristics and shows that with 2V dual supplies, the lower extreme of the input common mode voltage range is below ground potential. Bandwidth and Slew Rate For those cases where bandwidth reduction is desired, for example, broadband noise reduction, an external capacitor connected between terminals 1 and 8 can reduce the open loop -3dB bandwidth. The slew rate will, however, also be proportionally reduced by using this additional capacitor. Thus, a 20% reduction in bandwidth by this technique will also reduce the slew rate by about 20%. 100 φOL RL = 2kΩ, CL = 0pF -90 -105 -120 -135 80 -150 As mentioned previously, the amplifier inputs can be driven below the terminal 4 potential, but a series current limiting resistor is recommended to limit the maximum input terminal current to less than 1mA to prevent damage to the input protection circuitry. Moreover, some current limiting resistance should be provided between the inverting input and the output when the CA3140 is used as a unity gain voltage follower. This resistance prevents the possibility of extremely large input signal transients from forcing a signal through the input protection network and directly driving the internal constant current source which could result in positive feedback via the output terminal. A 3.9kΩ resistor is sufficient. 10K 8 6 4 60 RL = 2kΩ, CL = 100pF 40 SUPPLY VOLTAGE: V+ = 15V, V- = -15V 2 INPUT CURRENT (pA) SUPPLY VOLTAGE: V+ = 15V, V- = -15V TA = +25oC -75 Input Circuit Considerations OPEN LOOP PHASE (DEGREES) OPEN LOOP VOLTAGE GAIN (dB) Figure 14 shows the typical settling time required to reach 1mV or 10mV of the final value for various levels of large signal inputs for the voltage follower and inverting unity gain amplifiers. The exceptionally fast settling time characteristics are largely due to the high combination of high gain and wide bandwidth of the CA3140; as shown in Figure 15. 1K 8 6 4 2 100 8 6 4 2 10 8 6 4 20 2 0 101 102 103 104 105 106 107 1 108 -60 -40 -20 FREQUENCY (Hz) RL = ∞ 0 +125oC -0.5 +VICR AT TA = +VICR AT TA = +25oC -1.0 +V AT T = -55oC ICR A +VOUT AT TA = +125oC +VOUT AT TA = +25oC +VOUT AT TA = -55oC -1.5 -2.0 -2.5 -3.0 0 5 10 15 SUPPLY VOLTAGE (V+, V-) 20 120 140 FIGURE 16. INPUT CURRENT vs AMBIENT TEMPERATURE INPUT AND OUTPUT VOLTAGE EXCURSIONS FROM TERMINAL 4 (V-) INPUT AND OUTPUT VOLTAGE EXCURSIONS FROM TERMINAL 7 (V+) FIGURE 15. OPEN LOOP VOLTAGE GAIN AND PHASE vs FREQUENCY 0 20 40 60 80 100 AMBIENT TEMPERATURE (oC) 25 1.5 -VICR AT TA = +125oC 1.0 -VICR AT TA = +25oC 0.5 -VOUT FOR TA = oC -55 to -VICR AT TA = -55oC +125oC 0 -0.5 -1.0 -1.5 0 5 10 15 SUPPLY VOLTAGE (V+, V-) 20 25 FIGURE 17. OUTPUT VOLTAGE SWING CAPABILITY AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE AND TEMPERATURE 2-133 CA3140, CA3140A The typical input current is in the order of 10pA when the inputs are centered at nominal device dissipation. As the output supplies load current, device dissipation will increase, raising the chip temperature and resulting in increased input current. Figure 16 shows typical input terminal current versus ambient temperature for the CA3140. It is well known that MOSFET devices can exhibit slight changes in characteristics (for example, small changes in input offset voltage) due to the application of large differential input voltages that are sustained over long periods at elevated temperatures. Both applied voltage and temperature accelerate these changes. The process is reversible and offset voltage shifts of the opposite polarity reverse the offset. Figure 11 shows the typical offset voltage change as a function of various stress voltages at the maximum rating of +125oC (for TO-5); at lower temperatures (TO-5 and plastic), for example, at +85oC, this change in voltage is considerably less. In typical linear applications, where the differential voltage is small and symmetrical, these incremental changes are of about the same magnitude as those encountered in an operational amplifier employing a bipolar transistor input stage. Super Sweep Function Generator A function generator having a wide tuning range is shown in Figure 18. The 1,000,000/1 adjustment range is accomplished by a single variable potentiometer or by an auxiliary sweeping signal. The CA3140 functions as a non-inverting readout amplifier of the triangular signal developed across the integrating capacitor network connected to the output of the CA3080A current source. Buffered triangular output signals are then applied to a second CA3080 functioning as a high speed hysteresis switch. Output from the switch is returned directly back to the input of the CA3080A current source, thereby, completing the positive feedback loop The triangular output level is determined by the four 1N914 level limiting diodes of the second CA3080 and the resistor divider network connected to terminal No. 2 (input) of the CA3080. These diodes establish the input trip level to this switching stage and, therefore, indirectly determine the amplitude of the output triangle. Compensation for propagation delays around the entire loop is provided by one adjustment on the input of the CA3080. This adjustment, which provides for a constant generator amplitude output, is most easily made while the generator is sweeping. High frequency ramp linearity is adjusted by the single 7-to-6pF capacitor in the output of the CA3080A. It must be emphasized that only the CA3080A is characterized for maximum output linearity in the current generator function. Meter Driver and Buffer Amplifier Figure 19 shows the CA3140 connected as a meter driver and buffer amplifier. Low driving impedance is required of the CA3080A current source to assure smooth operation of the Frequency Adjustment Control. This low-driving impedance requirement is easily met by using a CA3140 connected as a voltage follower. Moreover, a meter may be placed across the input to the CA3080A to give a logarithmic analog indication of the function generators frequency. Analog frequency readout is readily accomplished by the means described above because the output current of the CA3080A varies approximately one decade for each 60mV change in the applied voltage, VABC (voltage between terminals 5 and 4 of the CA3080A of the function generator). Therefore, six decades represent 360mV change in VABC. Now, only the reference voltage must be established to set the lower limit on the meter. The three remaining transistors from the CA3086 Array used in the sweep generator are used for this reference voltage. In addition, this reference generator arrangement tends to track ambient temperature variations, and thus compensates for the effects of the normal negative temperature coefficient of the CA3080A VABC terminal voltage. Another output voltage from the reference generator is used to insure temperature tracking of the lower end of the Frequency Adjustment Potentiometer. A large series resistance simulates a current source, assuring similar temperature coefficients at both ends of the Frequency Adjustment Control. To calibrate this circuit, set the Frequency Adjustment Potentiometer at its low end. Then adjust the Minimum Frequency Calibration Control for the lowest frequency. To establish the upper frequency limit, set the Frequency Adjustment Potentiometer to its upper end and then adjust the Maximum Frequency Calibration Control for the maximum frequency. Because there is interaction among these controls, repetition of the adjustment procedure may be necessary. Two adjustments are used for the meter. The meter sensitivity control sets the meter scale width of each decade, while the meter position control adjusts the pointer on the scale with negligible effect on the sensitivity adjustment. Thus, the meter sensitivity adjustment control calibrates the meter so that it deflects 1/6 of full scale for each decade change in frequency. Sine Wave Shaper The circuit shown in Figure 20 uses a CA3140 as a voltage follower in combination with diodes from the CA3019 Array to convert the triangular signal from the function generator to a sine-wave output signal having typically less than 2% THD. The basic zero crossing slope is established by the 10kΩ potentiometer connected between terminals 2 and 6 of the CA3140 and the 9.1kΩ resistor and 10kΩ potentiometer from terminal 2 to ground. Two break points are established by diodes D1 through D4. Positive feedback via D5 and D6 establishes the zero slope at the maximum and minimum levels of the sine wave. This technique is necessary because the voltage follower configuration approaches unity gain rather than the zero gain required to shape the sine wave at the two extremes. 2-134 CA3140, CA3140A CENTERING -15V 10kΩ 7.5kΩ +15V 360Ω 3 7 + 15kΩ - 2 4 5 2MΩ 51 pF 7-60 pF -15V +15V 39Ω -15V 120Ω + CA3140 3 - 2 HIGH FREQ. SHAPE 0.1 µF FREQUENCY ADJUSTMENT +15V THIS NETWORK IS USED WHEN THE OPTIONAL BUFFER CIRCUIT IS NOT USED 5.1 kΩ +15V 62kΩ 10kΩ 5 6 CA3080 + 4 3 EXTERNAL OUTPUT EXTERNAL OUTPUT 7 - 2 11kΩ 11kΩ 10kΩ -15V 2kΩ 10kΩ 910 kΩ 6 4 100kΩ FROM BUFFER METER DRIVER (OPTIONAL) 0.1 µF 7 6 CA3080A 360Ω SYMMETRY -15V +15V HIGH FREQUENCY LEVEL 7-60pF 2.7kΩ -15V 13kΩ TO OUTPUT AMPLIFIER TO SINE WAVE SHAPER IN914 OUTPUT AMPLIFIER (A) CIRCUIT FREQUENCY ADJUSTMENT (B1) FUNCTION GENERATOR SWEEPING +15V METER DRIVER AND BUFFER AMPLIFIER Top Trace: Output at junction of 2.7Ω and 51Ω resistors 5V/Div and 500ms/Div Center Trace: External output of triangular function generator 2V/Div and 500ms/Div POWER SUPPLY ±15V M -15V FUNCTION GENERATOR Bottom Trace: Output of “Log” generator; 10V/Div and 500ms/Div WIDEBAND LINE DRIVER SINE WAVE SHAPER 51Ω FINE RATE SWEEP GENERATOR GATE DC LEVEL SWEEP ADJUST OFF INT. COARSE RATE V- EXT. SWEEP LENGTH V- (B2) FUNCTION GENERATOR WITH FIXED FREQUENCIES (C) INTERCONNECTIONS 1V/Div and 1sec/Div Three tone test signals, highest frequency ≥0.5MHz. Note the slight asymmetry at the three second/cycle signal. This asymmetry is due to slightly different positive and negative integration from the CA3080A and from the pc board and component leakages at the 100pA level. FIGURE 18. FUNCTION GENERATOR 2-135 EXTERNAL INPUT CA3140, CA3140A 500kΩ FREQUENCY ADJUSTMENT 10kΩ FREQUENCY CALIBRATION MAXIMUM 620kΩ 7 51kΩ 3 + 6 CA3140 SWEEP IN 3MΩ - 2 4.7kΩ 4 +15V 2kΩ 0.1µF 12 kΩ FREQUENCY 2.4kΩ CALIBRATION MINIMUM 2.5 kΩ 0.1µF 5.1kΩ 6 3/ 5 10kΩ D4 5 8 3.6kΩ 13 3 4 D5 CA3019 DIODE ARRAY OF CA3086 -15V FIGURE 19. METER DRIVER AND BUFFER AMPLIFIER FIGURE 20. SINE WAVE SHAPER 750kΩ “LOG” 100kΩ SAWTOOTH 18MΩ IN914 IN914 SAWTOOTH SYMMETRY 0.47µF 0.047µF FINE RATE 100kΩ 1MΩ 22MΩ 8.2kΩ +15V SAWTOOTH AND RAMP LOW LEVEL SET (-14.5V) COARSE RATE 4700pF 50kΩ 75kΩ 470pF +15V 2 - 3 + 7 “LOG” +15V +15V 36kΩ TRIANGLE 6 CA3140 51kΩ SAWTOOTH 0.1 µF 4 50kΩ LOG RATE ADJUST -15V 43kΩ TO OUTPUT AMPLIFIER 10kΩ 10kΩ 7 - 3 10kΩ 6 CA3140 100kΩ 30kΩ 0.1 µF + 2 4 -15V EXTERNAL OUTPUT TO FUNCTION GENERATOR “SWEEP IN” SWEEP WIDTH -15V 3 6 CA3140 2 LOGVIO +15V 7 + 5 1 51kΩ 4 6.8kΩ 91kΩ 10kΩ TRIANGLE 25kΩ 3.9Ω -15V 5 1 4 2 100Ω 390Ω 2 D3 D6 D2 1 9 12 METER POSITION ADJUSTMENT TO WIDEBAND OUTPUT AMPLIFIER 9.1kΩ R1 10kΩ 14 10 2kΩ 7 D1 -15V 7.5 kΩ EXTERNAL OUTPUT 1MΩ 100 kΩ 510Ω SUBSTRATE OF CA3019 7 -15V R3 10kΩ +15V 9 6 4 0.1µF 1kΩ 11 8 - 620Ω 5.6 kΩ 6 CA3140 200µA M METER 510Ω 7 + 3 2 METER SENSITIVITY ADJUSTMENT -15V +15V TO CA3080A OF FUNCTION CA3080A GENERATOR (FIGURE 18) 4 5 TRANSISTORS FROM CA3086 ARRAY 3 FIGURE 21. SWEEPING GENERATOR 2-136 SAWTOOTH “LOG” GATE PULSE OUTPUT 430Ω R2 1kΩ CA3140, CA3140A This circuit can be adjusted most easily with a distortion analyzer, but a good first approximation can be made by comparing the output signal with that of a sine wave generator. The initial slope is adjusted with the potentiometer R1, followed by an adjustment of R2. The final slope is established by adjusting R3, thereby adding additional segments that are contributed by these diodes. Because there is some interaction among these controls, repetition of the adjustment procedure may be necessary. REFERENCE VOLTAGE VOLTAGE ADJUSTMENT 3 + 7 CA3140 INPUT 2 - 6 REGULATED OUTPUT 4 Sweeping Generator Figure 21 shows a sweeping generator. Three CA3140's are used in this circuit. One CA3140 is used as an integrator, a second device is used as a hysteresis switch that determines the starting and stopping points of the sweep. A third CA3140 is used as a logarithmic shaping network for the log function. Rates and slopes, as well as sawtooth, triangle, and logarithmic sweeps are generated by this circuit. Wideband Output Amplifier Figure 22 shows a high slew rate, wideband amplifier suitable for use as a 50Ω transmission line driver. This circuit, when used in conjunction with the function generator and sine wave shaper circuits shown in Figures 18 and 20 provides 18V peak-to-peak output open circuited, or 9V peak-to-peak output when terminated in 50Ω. The slew rate required of this amplifier is 28V/µs (18V peak-to-peak x π x 0.5MHz). +15V + SIGNAL LEVEL ADJUSTMENT 2.5kΩ 3 7 + 2 - -15V 200Ω 4 + 2.4pF 2pF 1.8kΩ 2N3053 IN914 2.7Ω IN914 2.7Ω 51Ω OUT 2W 8 1 OUTPUT DC LEVEL +15V ADJUSTMENT 3kΩ 2.2 kΩ 6 CA3140 200Ω 50µF 25V 50µF 25V 2.2 kΩ 2N4037 -15V NOMINAL BANDWIDTH = 10MHz tr = 35ns FIGURE 22. WIDEBAND OUTPUT AMPLIFIER Power Supplies High input impedance, common mode capability down to the negative supply and high output drive current capability are key factors in the design of wide range output voltage supplies that use a single input voltage to provide a regulated output voltage that can be adjusted from essentially 0V to 24V. Unlike many regulator systems using comparators having a bipolar transistor input stage, a high impedance reference voltage divider from a single supply can be used in connection with the CA3140 (see Figure 23). FIGURE 23. BASIC SINGLE SUPPLY VOLTAGE REGULATOR SHOWING VOLTAGE FOLLOWER CONFIGURATION Essentially, the regulators, shown in Figures 24 and 25, are connected as non inverting power operational amplifiers with a gain of 3.2. An 8V reference input yields a maximum output voltage slightly greater than 25V. As a voltage follower, when the reference input goes to 0V the output will be 0V. Because the offset voltage is also multiplied by the 3.2 gain factor, a potentiometer is needed to null the offset voltage. Series pass transistors with high ICBO levels will also prevent the output voltage from reaching zero because there is a finite voltage drop (VCEsat) across the output of the CA3140 (see Figure 10). This saturation voltage level may indeed set the lowest voltage obtainable. The high impedance presented by terminal 8 is advantageous in effecting current limiting. Thus, only a small signal transistor is required for the current-limit sensing amplifier. Resistive decoupling is provided for this transistor to minimize damage to it or the CA3140 in the event of unusual input or output transients on the supply rail. Figures 24 and 25, show circuits in which a D2201 high speed diode is used for the current sensor. This diode was chosen for its slightly higher forward voltage drop characteristic, thus giving greater sensitivity. It must be emphasized that heat sinking of this diode is essential to minimize variation of the current trip point due to internal heating of the diode. That is, 1A at 1V forward drop represents one watt which can result in significant regenerative changes in the current trip point as the diode temperature rises. Placing the small signal reference amplifier in the proximity of the current sensing diode also helps minimize the variability in the trip level due to the negative temperature coefficient of the diode. In spite of those limitations, the current limiting point can easily be adjusted over the range from 10mA to 1A with a single adjustment potentiometer. If the temperature stability of the current limiting system is a serious consideration, the more usual current sampling resistor type of circuitry should be employed. A power Darlington transistor (in a heat sink TO-3 case), is used as the series pass element for the conventional current limiting system, Figure 24, because high power Darlington dissipation will be encountered at low output voltage and high currents. A small heat sink VERSAWATT transistor is used as the series pass element in the fold back current system, Figure 25, since dissipation levels will only approach 10W. In this system, the D2201 diode is used for current sampling. Fold- 2-137 CA3140, CA3140A back is provided by the 3kΩ and 100kΩ divider network connected to the base of the current sensing transistor. +30V 3 2N6385 CURRENT POWER DARLINGTON LIMITING ADJUST D2201 2 75Ω 1kΩ OUTPUT 0.1 ⇒ 24V AT 1A 1kΩ 1kΩ 2 2N2102 100Ω 1 8 Figure 28 (a) shows the turn ON and turn OFF characteristics of both regulators. The slow turn on rise is due to the slow rate of rise of the reference voltage. Figure 26 (B) shows the transient response of the regulator with the switching of a 20Ω load at 20V output. 1 3kΩ Both regulators, Figures 24 and 25, provide better than 0.02% load regulation. Because there is constant loop gain at all voltage settings, the regulation also remains constant. Line regulation is 0.1% per volt. Hum and noise voltage is less than 200µV as read with a meter having a 10MHz bandwidth. 3 1kΩ 56pF 7 180kΩ 2 6 2.7kΩ 10µF 5 - 1kΩ CA3140 + 1 100kΩ 82kΩ 3 4 INPUT + 2.2kΩ - 10 11 1 2 9 3 8 7 5 6 4 VOLTAGE ADJUST 5µF 50kΩ - 100kΩ 14 + 250µF 12 0.01µF 13 CA3086 1kΩ (A) SUPPLY TURN-ON AND TURNOFF CHARACTERISTICS 62kΩ HUM AND NOISE OUTPUT <200µVRMS (MEASUREMENT BANDWIDTH ~10MHz) LINE REGULATION 0.1%/VOLT 5V/Div and -1s/Div LOAD REGULATION (NO LOAD TO FULL LOAD) <0.02% FIGURE 24. REGULATED POWER SUPPLY OUTPUT ⇒ 0V TO 25V 25V AT 1A “FOLDS BACK” TO 40mA “FOLDBACK” CURRENT LIMITER 2N5294 D2201 2 3 +30V 1kΩ 200Ω 1 100kΩ 3kΩ 100kΩ 2N2102 8 1kΩ 56pF 7 180kΩ 2 2.7kΩ 10µF 5 - 1kΩ CA3140 6 + 1 100kΩ 82kΩ (B) TRANSIENT RESPONSE 3 4 Top Trace: Output voltage 200mV/Div and 5µs/Div INPUT + 2.2kΩ - 10 11 1 2 9 3 8 7 5 6 4 5µF 50kΩ 14 VOLTAGE ADJUST 100kΩ + - 250µF Bottom Trace: Collector of load switching transistor, load = 1A 5V/Div and 5µs/Div FIGURE 26. WAVEFORMS OF DYNAMIC CHARACTERISTICS OF POWER SUPPLY CURRENTS SHOWN IN FIGURES 24 AND 25 12 0.01µF 13 CA3086 Tone Control Circuits 1kΩ High slew rate, wide bandwidth, high output voltage capability and high input impedance are all characteristics required of tone control amplifiers. Two tone control circuits that exploit these characteristics of the CA3140 are shown in Figures 27 and 28. 62kΩ HUM AND NOISE OUTPUT <200µVRMS (MEASUREMENT BANDWIDTH ~10MHz) LINE REGULATION 0.1%/VOLT LOAD REGULATION (NO LOAD TO FULL LOAD) <0.02% FIGURE 25. REGULATED POWER SUPPLY WITH “FOLDBACK” CURRENT LIMITING 2-138 CA3140, CA3140A Figure 27 shows another tone control circuit with similar boost and cut specifications. The wideband gain of this circuit is equal to the ultimate boost or cut plus one, which in this case is a gain of eleven. For 20dB boost and cut, the input loading of this circuit is essentially equal to the value of the resistance from terminal No. 3 to ground. A detailed analysis of this circuit is given in “An IC Operational TransconductanceAmplifier (OTA) With Power Capability” by L. Kaplan and H. Wittlinger, IEEE Transactions on Broadcast and Television Receivers, Vol. BTR-18, No. 3, August, 1972. The first circuit, shown in Figure 28, is the Baxandall tone control circuit which provides unity gain at midband and uses standard linear potentiometers. The high input impedance of the CA3140 makes possible the use of low-cost, low-value, small size capacitors, as well as reduced load of the driving stage. Bass treble boost and cut are ±15dB at 100Hz and 10kHz, respectively. Full peak-to-peak output is available up to at least 20kHz due to the high slew rate of the CA3140. The amplifier gain is 3dB down from its “flat” position at 70kHz. FOR SINGLE SUPPLY 20dB Flat Position Gain ±15dB Bass and Treble Boost and Cut at 100Hz and 10kHz, respectively 25VP-P output at 20kHz -3dB at 24kHz from 1kHz reference +30V 2.2MΩ 7 0.005µF 5.1 MΩ 3 + CA3140 2 - 0.1µF 6 4 BOOST 2.2MΩ 0.1 µF 0.012µF TREBLE CUT 200kΩ (LINEAR) 0.001µF 18kΩ 100 pF FOR DUAL SUPPLIES +15V 3 7 + CA3140 2 - 0.005µF 100pF 5.1MΩ 4 0.022µF 2µF - + 0.0022µF 0.1µF 6 0.1µF -15V 10kΩ 1MΩ 100kΩ CCW (LOG) BOOST BASS CUT TONE CONTROL NETWORK TONE CONTROL NETWORK FIGURE 27. TONE CONTROL CIRCUIT USING CA3130 SERIES (20dB MIDBAND GAIN) FOR SINGLE SUPPLY BOOST 0.047µF BASS CUT (LINEAR) 240kΩ 5MΩ 240kΩ FOR DUAL SUPPLIES 2.2MΩ 750 pF +32V 750 pF +15V 7 3 2.2MΩ 0.1 µF 22 MΩ 2 + CA3140 0.1 µF 6 0.047µF 4 TONE CONTROL NETWORK 20pF 51kΩ 5MΩ 51kΩ (LINEAR) BOOST TREBLE CUT TONE CONTROL NETWORK 3 7 + CA3140 2 4 -15V ±15dB Bass and Treble Boost and Cut at 100Hz and 10kHz, respectively 25VP-P output at 20kHz -3dB at 70kHz from 1kHz reference 0dB Flat Position Gain FIGURE 28. BAXANDALL TONE CONTROL CIRCUIT USING CA3140 SERIES 2-139 0.1µF 6 0.1µF CA3140, CA3140A Wien Bridge Oscillator Another application of the CA3140 that makes excellent use of its high input impedance, high slew rate, and high voltage qualities is the Wien Bridge sine wave oscillator. A basic Wien Bridge oscillator is shown in Figure 29. When R1 = R2 = R and C1 = C2 = C, the frequency equation reduces to the familiar f = 1/2 π RC and the gain required for oscillation, AOSC is equal to 3. Note that if C2 is increased by a factor of four and R2 is reduced by a factor of four, the gain required for oscillation becomes 1.5, thus permitting a potentially higher operating frequency closer to the gain bandwidth product of the CA3140. C2 R2 NOTES: f 2π A Rf C1 OS C1 C2 RS C1 2 1000 pF R1 7 + CA3140 4 0.1µF CA3109 DIODE ARRAY 6 SUBSTRATE OF CA3019 8 9 1 2 6 0.1µF 3 7 0.1µF -15V 7.5kΩ 5 4 R1 = R2 = R 50Hz, R = 100Hz, R = 1kHz, R = 10kHz, R = 30kHz, R = 3.3MΩ 1.6MΩ 160MΩ 16MΩ 5.1MΩ 3.6kΩ 500Ω FIGURE 30. WIEN BRIDGE OSCILLATOR CIRCUIT USING CA3140 SERIES R2 R1 = 1 + ------- + ------- Simple Sample-and-Hold System R R1 3 R1C1R2C2 OUTPUT - 1000pF 1 = --------------------------- + +15V R2 C2 OUTPUT 19VP-P TO 22VP-P THD <0.3% A CL f = 1 + ------R S FIGURE 29. BASIC WIEN BRIDGE OSCILLATOR CIRCUIT USING AN OPERATIONAL AMPLIFIER Oscillator stabilization takes on many forms. It must be precisely set, otherwise the amplitude will either diminish or reach some form of limiting with high levels of distortion. The element, RS, is commonly replaced with some variable resistance element. Thus, through some control means, the value of RS is adjusted to maintain constant oscillator output. A FET channel resistance, a thermistor, a lamp bulb, or other device whose resistance is made to increase as the output amplitude is increased are a few of the elements often utilized. Figure 30 shows another means of stabilizing the oscillator with a zener diode shunting the feedback resistor (Rf of Figure 29). As the output signal amplitude increases, the zener diode impedance decreases resulting in more feedback with consequent reduction in gain; thus stabilizing the amplitude of the output signal. Furthermore, this combination of a monolithic zener diode and bridge rectifier circuit tends to provide a zero temperature coefficient for this regulating system. Because this bridge rectifier system has no time constant, i.e., thermal time constant for the lamp bulb, and RC time constant for filters often used in detector networks, there is no lower frequency limit. For example, with 1µF polycarbonate capacitors and 22MΩ for the frequency determining network, the operating frequency is 0.007Hz. As the frequency is increased, the output amplitude must be reduced to prevent the output signal from becoming slewrate limited. An output frequency of 180kHz will reach a slew rate of approximately 9V/µs when its amplitude is 16V peakto-peak. Figure 31 shows a very simple sample-and-hold system using the CA3140 as the readout amplifier for the storage capacitor. The CA3080A serves as both input buffer amplifier and low feed-through transmission switch.* System offset nulling is accomplished with the CA3140 via its offset nulling terminals. A typical simulated load of 2kΩ and 30pF is shown in the schematic. 0 30kΩ SAMPLE STROBE -15 IN914 HOLD +15V IN914 INPUT +15V 5 2kΩ + 3 CA3080A - 2 0.1µF 7 4 6 3 + CA3140 2 - 0.1µF 2kΩ 6 0.1 µF 4 5 -15V 3.5kΩ 7 1 100kΩ -15V 2kΩ 200pF 200pF 2kΩ 400Ω 0.1µF SIMULATED LOAD NOT REQUIRED 30pF FIGURE 31. SAMPLE AND HOLD CIRCUIT In this circuit, the storage compensation capacitance (C1) is only 200pF. Larger value capacitors provide longer “hold” periods but with slower slew rates. The slew rate i dv ------ = --- = 0.5mA ⁄ 200pF = 2.5V ⁄ µs c dt * ICAN-6668 “Applications of the CA3080 and CA 3080A High Performance Operational Transconductance Amplifiers”. Pulse “droop” during the hold interval is 170pA/200pF which is = 0.85µV/µs; (i.e., 170pA/200pF). In this case, 170pA 2-140 CA3140, CA3140A represents the typical leakage current of the CA3080A when strobed off. If C1 were increased to 2000 pF, the “hold-droop” rate will decrease to 0.085µV/µs, but the slew rate would decrease to 0.25V/µs. The parallel diode network connected between terminal 3 of the CA3080A and terminal 6 of the CA3140 prevents large input signal feedthrough across the input terminals of the CA3080A to the 200pF storage capacitor when the CA3080A is strobed off. Figure 32 shows dynamic characteristic waveforms of this sample-and-hold system. Current Amplifier The low input terminal current needed to drive the CA3140 makes it ideal for use in current amplifier applications such as the one shown in Figure 33.* In this circuit, low current is supplied at the input potential as the power supply to load resistor RL. This load current is increased by the multiplication factor R2/R1, when the load current is monitored by the power supply meter M. Thus, if the load current is 100nA, with values shown, the load current presented to the supply will be 100µA; a much easier current to measure in many systems. R1 10kΩ +15V IL R2 R1 0.1µF 3 M 2 POWER SUPPLY Top Trace: Output; 50mV/Div and 200ns/Div Bottom Trace: Input; 50mV/Div and 200ns/Div 7 + CA3140 5 4 1 R2 6 0.1µF 10MΩ IL RL 100kΩ 4.3kΩ -15V FIGURE 33. BASIC CURRENT AMPLIFIER FOR LOW CURRENT MEASUREMENT SYSTEMS Note that the input and output voltages are transferred at the same potential and only the output current is multiplied by the scale factor. The dotted components show a method of decoupling the circuit from the effects of high output load capacitance and the potential oscillation in this situation. Essentially, the necessary high frequency feedback is provided by the capacitor with the dotted series resistor providing load decoupling. LARGE SIGNAL RESPONSE AND SETTLING TIME Top Trace: Output Signal; 5V/Div and 2µs/Div Center Trace: Difference of Input and Output Signals through Tektronix Amplifier 7A13; 5mV/Div and 2µs/Div Bottom Trace: Input Signal; 5V/Div and 2µs/Div Figure 34 shows a single supply, absolute value, ideal fullwave rectifier with associated waveforms. During positive excursions, the input signal is fed through the feedback network directly to the output. Simultaneously, the positive excursion of the input signal also drives the output terminal (No. 6) of the inverting amplifier in a negative going excursion such that the 1N914 diode effectively disconnects the amplifier from the signal path. During a negative going excursion of the input signal, the CA3140 functions as a normal inverting amplifier with a gain equal to -R2/R1. When the equality of the two equations shown in Figure 34 is satisfied, the full wave output is symmetrical. SAMPLING RESPONSE * “Operational Amplifiers Design and Applications”, J. G. Graeme, McGraw-Hill Book Company, page 308 - “Negative Immittance Converter Circuits”. Top Trace: Output; 100mV/Div and 500ns/Div Bottom Trace: Input; 20V/Div and 500ns/Div FIGURE 32. SAMPLE AND HOLD SYSTEM DYNAMIC CHARACTERISTICS WAVEFORMS 2-141 CA3140, CA3140A +15V R2 5kΩ +15V 0.1µF R1 2 - 10kΩ + 8 3 1 5 6 4 2 1N914 SIMULATED LOAD + CA3140 CA3140 3 0.1µF 7 7 100kΩ 6 - 100pF 4 2kΩ 10kΩ R3 100kΩ OFFSET ADJUST 0.1µF PEAK ADJUST 10kΩ -15V 2kΩ R2 R3 GAIN = ------- = X = ---------------------------------R1 R1 + R2 + R3 BW (-3dB) = 4.5MHz SR = 9V/µs 0.05µF 2 X+X R3 = ---------------- R1 1–X 5kΩ R2 FORX = 0.5 ------------- = ------10kΩ R1 0.75 R3 = 10kΩ ---------- = 15kΩ 0.5 20Vp-p Input BW(-3dB) = 290kHz, DCOutput (Avg) = 3.2V (A) SMALL SIGNAL RESPONSE 50mV/Div and 200ns/Div OUTPUT 0 Top Trace: Output; 50mV/Div and 200ns/Div Bottom Trace: Input; 50mV/Div and 200ns/Div INPUT 0 FIGURE 34. SINGLE SUPPLY, ABSOLUTE VALUE, IDEAL FULL WAVE RECTIFIER WITH ASSOCIATED WAVEFORMS +15V 7 RS 3 1MΩ 0.01µF + 6 CA3140 2 - NOISE VOLTAGE OUTPUT (B) INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING SETTLING TIME (measurement made with Tektronix 7A13 differential amplifier) 4 0.01µF 30.1kΩ -15V BW (-3dB) = 140kHz TOTAL NOISE VOLTAGE (REFERRED TO INPUT ) = 48µV TYP. Top Trace: Output Signal; 5V/Div and 5µs/Div Center Trace: Difference Signal; 5mV/Div and 5µs/Div Bottom Trace: Input Signal; 5V/Div and 5µs/Div 1kΩ FIGURE 35. TEST CIRCUIT AMPLIFIER (30dB GAIN) USED FOR WIDEBAND NOISE MEASUREMENT FIGURE 36. SPLIT SUPPLY VOLTAGE FOLLOWER TEST CIRCUIT AND ASSOCIATED WAVEFORMS 2-142