[ /Title (CD74 HCT24 2, CD74 HC243 , CD74 HCT24 3) /Subject (High Speed CMOS Logic Quad- CD74HCT242 was not acquired from Harris Semiconductor. Data sheet acquired from Harris Semiconductor SCHS168A November 1997 - Revised May 2000 CD74HCT242, CD54/74HC243, CD54/74HCT243 High Speed CMOS Logic Quad-Bus Transceiver with Three-State Outputs Features Description • Typical Propagation Delay (A to B, B to A) of 7ns at VCC = 5V, CL = 15pF, TA = 25oC The CD74HCT242, ’HC243 and ’HCT243 silicon-gate CMOS three-state bidirectional inverting and non-inverting buffers are intended for two-way asynchronous communication between data buses. They have high drive current outputs which enable high-speed operation when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuits, and have speeds comparable to low power Schottky TTL circuits. They can drive 15 LSTTL loads. • Three-State Outputs • Buffered Inputs • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC The CD74HCT242 is an inverting buffer; the ’HC243 and ’HCT243 are non-inverting buffers. • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs The states of the output enables (OEB, OEA) determine both the direction of flow (A to B, B to A), and the three-state mode. • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V Ordering Information • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH PART NUMBER Pinout CD54HC243, CD54HCT243 (CERDIP) CD74HCT242, CD74HC243, CD74HCT243 (PDIP, SOIC) TOP VIEW OEB 1 14 VCC NC 2 13 OEA A0 3 12 NC A1 4 11 B0 A2 5 10 B1 A3 6 9 B2 GND 7 8 B3 TEMP. RANGE (oC) CD54HC243F -55 to 125 14 Ld CERDIP CD54HC243F3A -55 to 125 14 Ld CERDIP CD74HC243E -55 to 125 14 Ld PDIP CD74HC243M -55 to 125 14 Ld SOIC CD54HCT243F3A -55 to 125 14 Ld CERDIP CD74HCT243M -55 to 125 14 Ld SOIC NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer or die for this part number is available which meets all electrical specifications. Please contact your local TI sales office. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2000, Texas Instruments Incorporated PACKAGE 1 CD74HCT242, CD54/74HC243, CD54/74HCT243 Functional Diagrams CD74HCT242 A0 A1 ’HC243, ’HCT243 3 11 4 10 5 9 A2 6 A0 B1 A1 B2 A2 B3 A3 8 A3 1 OEB 13 OEA B0 3 11 4 10 5 9 B1 B2 6 OEB DIRECTION SELECT LOGIC OEA B0 8 B3 1 13 DIRECTION SELECT LOGIC TRUTH TABLE CONTROL INPUTS HCT242 SERIES HC, HCT243 SERIES DATA PORT STATUS DATA PORT STATUS OEB OEA An Bn An Bn H H O I O I L H Z Z Z Z H L Z Z Z Z L L I O I O NOTE: H = High Voltage Level L = Low Voltage Level I = Input O = Output (Same Level as Input) O = Output (Inversion of Input Level) Z = High Impedance To prevent excess currents in the High Z modes all I/O terminals should be terminated with 10kΩ to 1MΩ resistors. 2 CD74HCT242, CD54/74HC243, CD54/74HCT243 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±70mA Thermal Resistance (Typical, Note 3) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER SYMBOL VI (V) VIH - 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V -6 4.5 3.98 - - 3.84 - 3.7 - V -7.8 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V 6 4.5 - - 0.26 - 0.33 - 0.4 V 7.8 6 - - 0.26 - 0.33 - 0.4 V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads VOL VIH or VIL - - 3 CD74HCT242, CD54/74HC243, CD54/74HCT243 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) II VCC or GND - Quiescent Device Current ICC VCC or GND Three-State Leakage Current IOZ High Level Input Voltage 25oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 6 - - ±0.1 - ±1 - ±1 µA 0 6 - - 8 - 80 - 160 µA VIL or VIH - 6 - - ±0.5 - ±0.5 - ±10 µA VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -6 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 6 4.5 - - 0.26 - 0.33 - 0.4 V PARAMETER Input Leakage Current IO (mA) VCC (V) -40oC TO 85oC HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads II VCC to GND 0 5.5 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA Additional Quiescent Device Current Per Input Pin: 1 Unit Load (Note 4) ∆ICC VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA Three-State Leakage Current IOZ VIL or VIH - 5.5 - - ±0.5 - ±5.0 - ±10 µA Input Leakage Current Quiescent Device Current NOTE: 4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS An, Bn 1.1 OEA, OEB 0.6 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC. 4 CD74HCT242, CD54/74HC243, CD54/74HCT243 Switching Specifications PARAMETER HC TYPES Propagation Delay Data to Outputs (HC243) Output High-Z, to High Level to Low Level Output High Level, Output Low Level to High-Z Output Transition Times Input tr, tf = 6ns SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF tPZL, tPZH tPHZ, tPLZ tTLH, tTHL 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX UNITS 2 - 90 115 135 ns 4.5 - 18 23 27 ns CL = 15pF 5 7 - - - ns CL = 50pF 6 - 15 20 23 ns CL = 50pF 2 - 150 190 225 ns CL = 50pF 4.5 - 30 38 45 ns CL = 15pF 5 12 - - - ns CL = 50pF 6 - 26 33 38 ns CL = 50pF 2 - 150 190 225 ns CL = 50pF 4.5 - 30 38 45 ns CL = 15pF 5 12 - - - ns CL = 50pF 6 - 26 33 38 ns 2 - 60 75 90 ns 4.5 - 12 15 18 ns CL = 50pF 6 - 10 13 15 ns Input Capacitance CI - - - 10 10 10 pF Three-State Output Capacitance CO - - - 20 20 20 pF Power Dissipation Capacitance (HC243) (Notes 5, 6) CPD - 5 80 - - - pF 4.5 - 20 25 30 ns CL = 15pF 5 8 - - - ns CL = 50pF 4.5 - 22 28 33 ns CL = 15pF 5 9 - - - ns CL = 50pF 4.5 - 34 43 51 ns CL = 15pF 5 14 - - - ns CL = 50pF 4.5 - 35 44 53 ns CL = 15pF 5 14 - - - ns CL = 50pF 4.5 - 12 15 18 ns HCT TYPES Propagation Delay Data to Outputs (HCT242) tPLH, tPHL Propagation Delay Data to Outputs (HCT243) tPLH, tPHL Output High-Z to High Level to Low Level tPZH, tPZL Output High Level, Output Low Level to High-Z tPHZ, tPLZ Output Transition Times tTLH, tTHL CL = 50pF Input Capacitance CI - - - 10 10 10 pF Three-State Output Capacitance CO - - - 20 20 20 pF Power Dissipation Capacitance (Notes 5, 6) CPD HCT242 5 90 - - - pF HCT243 5 91 - - - pF NOTES: 5. CPD is used to determine the dynamic power consumption, per channel. 6. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. 5 CD74HCT242, CD54/74HC243, CD54/74HCT243 Test Circuits and Waveforms tr = 6ns tf = 6ns 90% 50% 10% INPUT GND tTLH tPHL 6ns 10% 2.7 1.3 OUTPUT LOW TO OFF 90% OUTPUT HIGH TO OFF 50% OUTPUTS DISABLED FIGURE 3. HC THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE IC WITH THREESTATE OUTPUT GND 1.3V tPZH 90% OUTPUTS ENABLED OUTPUTS ENABLED 0.3 10% tPHZ tPZH 3V tPZL tPLZ 50% OUTPUTS ENABLED 6ns GND 10% tPHZ tf OUTPUT DISABLE tPZL tPLZ OUTPUT HIGH TO OFF 6ns tr VCC 90% tPLH FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 6ns OUTPUT LOW TO OFF 1.3V 10% INVERTING OUTPUT FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 50% tTLH 90% tPLH tPHL GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL OUTPUT DISABLE tf = 6ns tr = 6ns VCC 1.3V OUTPUTS DISABLED OUTPUTS ENABLED FIGURE 4. HCT THREE-STATE PROPAGATION DELAY WAVEFORM OUTPUT RL = 1kΩ CL 50pF VCC FOR tPLZ AND tPZL GND FOR tPHZ AND tPZH NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to VCC, CL = 50pF. FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 6 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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