[ /Title (CD74 HC194, CD74H CT194) /Subject (HighSpeed CMOS Logic 4-Bit CD54/74HC194, CD74HCT194 Data sheet acquired from Harris Semiconductor SCHS164B High-Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register September 1997 - Revised March 2002 Features Description • Four Operating Modes - Shift Right, Shift Left, Hold and Reset • Synchronous Parallel or Serial Operation • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The ’HC194 and CD74HCT194 are 4-bit shift registers with Asynchronous Master Reset (MR). In the parallel mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the clock input (CP). During parallel loading serial data flow is inhibited. Shift left and shift right are accomplished synchronously on the positive clock edge with serial data entered at the shift left (DSL) serial input for the shift right mode, and at the shift right (DSR) serial input for the shift left mode. Clearing the register is accomplished by a Low applied to the Master Reset (MR) pin. • Wide Operating Temperature Range . . . -55oC to 125oC Ordering Information • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Asynchronous Master Reset • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs PART NUMBER • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH TEMP. RANGE (oC) PACKAGE CD54HC194F3A -55 to 125 16 Ld CERDIP CD74HC194E -55 to 125 16 Ld PDIP CD74HC194M -55 to 125 16 Ld SOIC CD74HC194NSR -55 to 125 16 Ld SOP CD74HCT194E -55 to 125 16 Ld PDIP NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. Pinout CD54HC194 (CERDIP) CD74HC194 (PDIP, SOIC, SOP) CD74HCT194 (PDIP, SOIC) TOP VIEW 16 VCC MR 1 DSR 2 15 Q0 D0 3 14 Q1 D1 4 13 Q2 D2 5 12 Q3 D3 6 11 CP DSL 7 10 S1 GND 8 9 S0 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2002, Texas Instruments Incorporated 1 CD54/74HC194, CD74HCT194 Functional Diagram D0 D1 D2 D3 DSL 3 15 4 14 5 13 6 12 7 2 9 10 1 DSR 11 Q0 Q1 Q2 Q3 GND = 8 VCC = 16 S0 S1 MR CP TRUTH TABLE INPUTS OPERATING MODE OUTPUT CP MR S1 S0 DSR DSL Dn Q0 Q1 Q2 Q3 Reset (Clear) X L X X X X X L L L L Hold (Do Nothing) X H l (Note 2) l (Note 2) X X X q0 q1 q2 q3 Shift Left ↑ H h l (Note 2) X l X q1 q2 q3 L ↑ H h l (Note 2) X h X q1 q2 q3 H ↑ H l (Note 2) h l X X L q0 q1 q2 ↑ H l (Note 2) h h X X H q0 q1 q2 ↑ H h h X X dn d0 d1 q2 d3 Shift Right Parallel Load NOTES: 1. H = High Voltage Level, h = High Voltage Level One Set-up Time Prior To The Low to High Clock Transition, L = Low Voltage Level, l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition, dn (qn) = Lower Case Letters Indicate the State of the Referenced Input (or output) One Set-up Time Prior to the Low To High Clock Transition, X = Don’t Care, ↑ = Transition from Low to High Level 2. The High to Low transition of the S0 and S1 Inputs on the ’HC194, CD74HCT194 should only take place while CP is High for Conventional Operation. 2 CD54/74HC194, CD74HCT194 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA Package Thermal Impedance, θJA (see Note 3): PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W SOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER SYMBOL VI (V) VIH - 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads VOL VIH or VIL - - 3 CD54/74HC194, CD74HCT194 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) II VCC or GND - ICC VCC or GND High Level Input Voltage VIH Low Level Input Voltage High Level Output Voltage CMOS Loads PARAMETER Input Leakage Current Quiescent Device Current 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 6 - - ±0.1 - ±1 - ±1 µA 0 6 - - 8 - 80 - 160 µA - - 4.5 to 5.5 2 - - 2 - 2 - V VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load (Note 4) II VCC to GND 0 5.5 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA ∆ICC VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: 4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS CP 0.6 MR 0.55 DSL, DSR, Dn 0.25 Sn 1.10 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g. 360µA max at 25oC. 4 CD54/74HC194, CD74HCT194 Prerequisite For Switching Function 25oC PARAMETER SYMBOL TEST CONDITIONS VCC (V) -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX MIN MAX UNITS 2 6 - 5 - 4 - MHz 4.5 30 - 24 - 20 - MHz 6 35 - 28 - 23 - MHz 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns 2 70 - 90 - 105 - ns 4.5 14 - 18 - 21 - ns 6 12 - 15 - 19 - ns 2 60 - 75 - 90 - ns 4.5 12 - 15 - 18 - ns 6 10 - 13 - 15 - ns 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns 2 70 - 90 - 105 - ns 4.5 14 - 18 - 21 - ns 6 12 - 15 - 18 - ns 2 0 - 0 - 0 - ns 4.5 0 - 0 - 0 - ns 6 0 - 0 - 0 - ns 2 0 - 0 - 0 - ns 4.5 0 - 0 - 0 - ns 6 0 - 0 - 0 - ns HC TYPES Max. Clock Frequency (Figure 1) MR Pulse Width (Figure 2) Clock Pulse Width (Figure 1) Set-up Time Data to Clock (Figure 3) Removal Time, MR to Clock (Figure 2) Set-Up Time S1, S0 to Clock (Figure 4) Set-up Time DSL, DSR to Clock (Figure 4) Hold Time S1, S0 to Clock (Figure 4 Hold Time Data to Clock (Figure 3) fMAX tW tW tSU tREM tSU tSU tH tH - - - - - - - - - HCT TYPES Max. Clock Frequency (Figure 1) fMAX - 4.5 27 - 22 - 18 - MHz MR Pulse Width (Figure 2) tW - 4.5 16 - 20 - 24 - ns Clock Pulse Width (Figure 1) tW - 4.5 16 - 20 - 24 - ns Set-up Time, Data to Clock (Figure 3) tSU - 4.5 14 - 18 - 21 - ns Removal Time MR to Clock (Figure 2) tREM - 4.5 12 - 15 - 18 - ns 5 CD54/74HC194, CD74HCT194 Prerequisite For Switching Function (Continued) 25oC PARAMETER SYMBOL TEST CONDITIONS VCC (V) -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX MIN MAX UNITS Set-up Time S1, S0 to Clock (Figure 4) tSU - 4.5 20 - 25 - 30 - ns Set-up Time DSL, DSR to Clock (Figure 4) tSU - 4.5 14 - 18 - 21 - ns Hold Time S1, S0 to Clock (Figure 4) tH - 4.5 0 - 0 - 0 - ns Hold Time Data to Clock (Figure 3) tH - 4.5 0 - 0 - 0 - ns Switching Specifications PARAMETER HC TYPES Propagation Delay, Clock to Output (Figure 1) Input tr, tf = 6ns SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF Propagation Delay, Clock to Q tPLH, tPHL Output Transition Time (Figure 1) tTLH, tTHL Propagation Delay, MR to Output (Figure 2) tPHL Input Capacitance CL = 50pF CL = 50pF 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX UNITS 2 - 175 220 265 ns 4.5 - 35 44 53 ns 6 - 30 37 45 ns 5 14 - - - ns 2 - 75 95 110 ns 4.5 - 15 19 22 ns 6 - 13 16 19 ns 2 - 140 175 210 ns 4.5 - 28 35 42 ns 6 - 24 30 36 ns CIN - - - 10 10 10 pF Maximum Clock Frequency fMAX - 5 60 - - - MHz Power Dissipation Capacitance (Notes 5, 6) CPD - 5 55 - - - pF 4.5 - 37 46 56 ns 5 15 - - - ns HCT TYPES Propagation Delay, Clock to Output (Figure 1) tPLH, tPHL CL = 50pF Propagation Delay, Clock to Q tPLH, tPHL Output Transition Times (Figure 1) tTLH, tTHL CL = 50pF 4.5 - 15 19 22 ns Propagation Delay, MR to Output (Figure 2) tPHL CL = 50pF 4.5 - 40 50 60 ns Input Capacitance CIN - - - 10 10 10 pF Maximum Clock Frequency fMAX - 5 50 - - - MHz Power Dissipation Capacitance (Notes 5, 6) CPD - 5 60 - - - pF - NOTES: 5. CPD is used to determine the dynamic power consumption, per gate. 6. PD = VCC2 fi + ∑ (CL VCC2) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. 6 CD54/74HC194, CD74HCT194 Test Circuits and Waveforms tr INPUT LEVEL CP 10% tf 90% VS VS 10% MR VS INPUT LEVEL VS GND tW tW tPLH tPHL 90% VS 10% tTLH VS tTHL tPHL VALID S OR DS CP VS INPUT LEVEL VS GND tH GND FIGURE 2. MASTER RESET PRE-REQUISITE TIMES AND PROPAGATION DELAYS INPUT LEVEL tSU INPUT LEVEL VS VALID VS tREM Q FIGURE 1. CLOCK PRE-REQUISITE TIMES AND PROPAGATION AND OUTPUT TRANSITION TIMES DATA GND VS CP Q VS tSU INPUT LEVEL CP GND FIGURE 3. DATA PRE-REQUISITE TIMES tH VS GND INPUT LEVEL GND FIGURE 4. PARALLEL LOAD OR SHIFT-LEFT/SHIFT-RIGHT PRE-REQUISITE TIMES 7 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. 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