CS8140, CS8141 5.0 V, 500 mA Linear Regulator with ENABLE, RESET, and Watchdog The CS8140 and CS8141 are linear regulators suited for microprocessor applications in automotive environments. These ON Semiconductor parts provide the power for the microprocessors along with many of the control functions needed in today’s computer based systems. Incorporating all of these features saves both cost, and board space. Packages are available for surface mounting as well as through hole mounting. The CS8141 has the same feature set as the CS8140 with the exception of the response to the watchdog signals (WDI). The CS8141 only responds to input signals (WDI) which are below the preset watchdog frequency threshold. http://onsemi.com TO–220 SEVEN LEAD T SUFFIX CASE 821E 1 7 TO–220 SEVEN LEAD TVA SUFFIX CASE 821J 1 Features • 5.0 V ±4.0%, 500 mA Output Voltage • µP Compatible Control Functions – Watchdog – RESET – ENABLE • Low Dropout Voltage (1.25 V @ 500 mA) • Low Quiescent Current (7.0 mA @ 500 mA) • Low Noise, Low Drift • Low Current SLEEP Mode (IQ = 250 µA) • Fault Protection – Thermal Shutdown – Short Circuit – 60 V Peak Transient Voltage 7 TO–220 SEVEN LEAD THA SUFFIX CASE 821H 1 D2PAK 7–PIN DPS SUFFIX CASE 936H 1 7 ORDERING INFORMATION Device Package Shipping CS8140YTVA7 TO–220* STRAIGHT TO–220* VERTICAL 50 Units/Rail CS8140YTHA7 TO–220* HORIZONTAL 50 Units/Rail CS8140YDPS7 D2PAK* 50 Units/Rail CS8140YDPSR7 D2PAK* 750 Tape & Reel CS8141YT7 TO–220* STRAIGHT 50 Units/Rail CS8141YTVA7 TO–220* VERTICAL 50 Units/Rail CS8141YTHA7 TO–220* HORIZONTAL 50 Units/Rail CS8141YDPS7 D2PAK* 50 Units/Rail CS8141YDPSR7 D2PAK* 750 Tape & Reel CS8140YT7 50 Units/Rail *7Lead/Pin DEVICE MARKING INFORMATION See general marking information in the device marking section on page 13 of this data sheet. Semiconductor Components Industries, LLC, 2001 April, 2001 – Rev. 11 1 Publication Order Number: CS8140/D CS8140, CS8141 PIN CONNECTIONS D2PAK SEVEN PIN TO–220 SEVEN LEAD Tab = GND Pin 1. VIN 2. ENABLE 3. RESET 4. GND 5. Delay 6. WDI 7. VOUT Tab = GND Pin 1. VIN 2. ENABLE 3. RESET 4. GND 5. Delay 6. WDI 7. VOUT 1 1 VIN Overvoltage Overtemperature Reference & Bias Regulation ENABLE WDI Control Logic ENABLE RESET Delay VOUT Short Circuit Undervoltage GND Watchdog RESET Delay Figure 1. Block Diagram ABSOLUTE MAXIMUM RATINGS* Rating Input Operating Range Value Unit –0.5 to 26 V Peak Transient Voltage (46 V Load Dump @ 14 V VBAT) 60 V Electrostatic Discharge (Human Body Model) 4.0 kV –0.3 to 7.0 V Internally Limited – Junction Temperature Range (TJ) –40 to +150 °C Storage Temperature Range –65 to +150 °C ENABLE –0.3 to VIN V 260 peak 230 peak °C WDI Input Signal Range Internal Power Dissipation Lead Temperature Soldering: Wave Solder (through hole styles only) (Note 1) Reflow (SMD styles only) (Note 2) 1. 10 second maximum. 2. 60 seconds max above 183°C. *The maximum package power dissipation must be observed. http://onsemi.com 2 CS8140, CS8141 ELECTRICAL CHARACTERISTICS (7.0 ≤ VIN ≤ 26 V, 5.0 mA ≤ IOUT ≤ 500 mA, –40°C ≤ TJ ≤ 150°C, –40°C ≤ TA ≤ 125°C, unless otherwise noted.) Note 3 Characteristic Test Conditions Min Typ Max Unit Output Voltage, VOUT 7.0 V ≤ VIN ≤ 26 V, 5.0 mA < IOUT < 500 mA 4.8 5.0 5.2 V Dropout Voltage (VIN – VOUT) IOUT = 500 mA – 1.25 1.50 V Line Regulation IOUT = 50 mA, 7.0 V ≤ VIN ≤ 26 V, – 5.0 25 mV Load Regulation VIN = 14 V, 50 mA ≤ IOUT ≤ 500 mA – 5.0 80 mV Output Impedance, ROUT 500 mA DC and 10 mA AC, 100 Hz ≤ f ≤ 10 kHz – 200 – mΩ 0 ≤ IOUT ≤ 500 mA, 7.0 V ≤ VIN ≤ 26 V IOUT = 0 mA, VIN = 13 V, ENABLE = 0 V – – 7.0 0.25 15 0.50 mA mA 7.0 V ≤ VIN ≤ 17 V, IOUT = 250 mA, f = 120 Hz 60 75 – dB Output Stage (VOUT) Quiescent Current, (IQ) Active Mode Sleep Mode Ripple Rejection Current Limit – 700 1200 2000 mA Thermal Shutdown – 150 180 – °C VOUT < 1.0 V 30 34 38 V Threshold HIGH LOW VOUT ≥ 0.5 V, (VOUT(ON)) VOUT < 0.5 V, (VOUT(OFF)) – 3.5 4.05 3.95 4.50 – V V Threshold Hysteresis (HIGH – LOW) – 100 – mV Overvoltage Shutdown ENABLE RESET Threshold HIGH VR(HI) VOUT Increasing 4.65 4.90 VOUT – 0.05 V Threshold LOW VR(LOW) VOUT Decreasing 4.50 4.70 4.90 V Threshold Hysteresis (VRH) (HIGH – LOW) 150 200 250 mV RESET Output Leakage RESET = HIGH VOUT ≥ VR(HI) – – 25 µA Output Voltage Low (VL(LOW)) 1.0 V ≤ VOUT ≤ VR(LOW), RP = 2.7 kΩ, Note 4 – 0.1 0.4 V Output Voltage Low (VRpeak) VOUT, Power up, Power down – 0.6 1.0 V Delay Times tPOR CDELAY = 0.1 µF 30 47.5 65 ms Delay Times tWDI(RESET) CDELAY = 0.1 µF 0.5 1.0 1.5 ms Watchdog Input Voltage High – 2.0 – – V Input Voltage Low – – – 0.8 V Input Current WDI ≤ VOUT – 0 10 µA Threshold Frequency fWDI(LOWER) CDELAY = 0.1 µF 64 77 96 Hz Threshold Frequency fWDI(UPPER) (Note 5.) CDELAY = 0.1 µF 218 262 326 Hz 3. To observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable. 4. RP is connected to RESET and VOUT. 5. CS8140 only. http://onsemi.com 3 CS8140, CS8141 PACKAGE LEAD DESCRIPTION PACKAGE LEAD # D2PAK TO–220 LEAD SYMBOL 1 1 VIN 2 2 ENABLE 3 3 RESET 4 4 GND Ground Connection. 5 5 Delay Timing capacitor for Watchdog and RESET functions. 6 6 WDI CMOS compatible input lead. The Watchdog function monitors the falling edge of the incoming digital pulse train. The signal is usually generated by the system microprocessor. 7 7 VOUT Regulated output voltage, 5.0 V (typ). FUNCTION Supply voltage to IC, usually direct from the battery. CMOS compatible logical input. VOUT is disabled when ENABLE is LOW and WDI is beyond its preset limits. CMOS compatible output lead. RESET goes low whenever VOUT drops below 4.5% of it’s typical value for more than 2.0 µs or WDI signal falls outside it’s window limits. TYPICAL PERFORMANCE CHARACTERISTICS 5.5 5.0 5.5 VENABLE = VIN RLOAD = NO LOAD 4.5 4.5 RLOAD = 6.67 Ω 3.5 RLOAD 10 Ω 2.5 1.5 1.0 1.0 0.5 0.5 1 2 3 4 5 6 7 8 9 0 10 0 1 3.5 1600 0 Load Regulation (mV) 1200 –40°C 125°C 600 4 5 6 7 8 9 10 –40°C 25°C –3.5 1400 800 3 Figure 7. VOUT vs. VIN Over Temperature; RLOAD = 25 Ω Figure 6. VOUT vs. VIN over RLOAD; T = 25°C 1000 2 VIN (V) 1800 25°C 400 –7 VIN = 14 V –10.5 –14 –17.5 –21 125°C –24.5 –28 200 0 TEMP = 25°C 2.5 2.0 VIN (V) Dropout Voltage (mV) 3.0 1.5 0 TEMP = –40°C 3.5 2.0 0 TEMP = 125°C 4.0 VOUT (V) VOUT (V) 4.0 3.0 VENABLE = VIN 5.0 –31.5 0 100 200 300 400 500 600 700 –35 800 0 100 200 300 400 500 600 700 IOUT (mV) IOUT (mA) Figure 9. Load Regulation vs. Output Current Over Temperature Figure 8. Dropout Voltage vs. Output Current Over Temperature http://onsemi.com 4 800 CS8140, CS8141 TYPICAL PERFORMANCE CHARACTERISTICS (continued) 18 10 6 4 –40°C 8 –40°C 8 25°C 7 125°C 6 2 0 25°C –2 5 125°C –4 4 –6 0 20 18 100 200 300 400 500 600 700 800 0 300 400 500 600 700 Figure 10. Line Regulation vs. Output Current Over Temperature Figure 11. Quiescent Current vs. Output Current Over Temperature 800 20 VENABLE = VIN 14 14 12 RLOAD = 6.67 10 8 RLOAD = 25 6 RLOAD = NO LOAD 10 6 TEMP = 125°C 2 2 3 4 5 6 7 8 TEMP = –40°C 8 4 2 TEMP = 25°C 12 4 1 VENABLE = VIN 18 16 0 200 IOUT (mA) 16 0 100 IOUT (mA) IQ (mA) IQ (mA) VIN = 14 V 9 14 12 IQ (mA) Line Regulation (mV) 10 VIN = 14 V 16 9 0 10 0 1 2 3 4 5 6 7 8 9 VIN (V) VIN (V) Figure 12. Quiescent Current vs. VIN Over RLOAD; T = 25°C Figure 13. Quiescent Current vs. VIN Over Temperature; RLOAD = 25 Ω 10 107 300 280 260 106 Upper Threshold 220 200 WDI Threshold Frequency (Hz) 240 CDELAY = 0.1 µF 180 160 140 120 105 Upper Threshold 104 103 Lower Threshold 102 Lower Threshold 100 101 80 100 60 –40 –30 –20–10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 101 102 103 104 105 106 Capacitance (pF) TJ (°C) Figure 15. Watchdog Frequency Threshold vs. CDELAY Figure 14. Watchdog Frequency Thresholds vs. Temperature http://onsemi.com 5 107 CS8140, CS8141 TYPICAL PERFORMANCE CHARACTERISTICS (continued) 2000 90 IO = 250 mA 80 RESET Output Voltage (mV) 70 Rejection (dB) 1800 CO = 10 µF, ESR = 1.0 & 0.1 µF, ESR = 0 60 50 40 COUT = 10 µF, ESR = 1.0 Ω 30 20 COUT = 10 µF, ESR = 1.0 Ω 10 0 100 101 102 103 104 105 106 VIN = 5.0 V 1600 1400 1200 1000 800 600 400 200 107 0 108 1 5 Frequency (Hz) 10 15 20 25 30 35 40 RESET Output Current (mA) Figure 16. Ripple Rejection vs. Frequency Figure 17. RESET Output Voltage vs. Output Current DEFINITION OF TERMS such that the average chip temperature is not significantly affected. Load Regulation: The change in output voltage for a change in load current at constant chip temperature. Quiescent Current: The part of the positive input current that does not contribute to the positive load current. The regulator ground lead current. Ripple Rejection: The ratio of the peak–to–peak input ripple voltage to the peak–to–peak output ripple voltage. Current Limit: Peak current that can be delivered to the output. Dropout Voltage: The input–output voltage differential at which the circuit ceases to regulate against further reduction in input voltage. Measured when the output voltage has dropped 100 mV from the nominal value obtained at 14 V input, dropout voltage is dependent upon load current and junction temperature. Input Voltage: The DC voltage applied to the input terminals with respect to ground. Line Regulation: The change in output voltage for a change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques CIRCUIT DESCRIPTION The CS8140 is a 5.0 V Watchdog Regulator with protection circuitry and three logic control functions that allow a microprocessor to control its own power supply. The CS8140 is designed for use in automotive, switch mode power supply post regulator, and battery powered systems. Basic regulator performance characteristics include a low noise, low drift, 5.0 V ±4.0% precision output voltage with low dropout voltage (1.25 V @ IOUT = 500 mA) and low quiescent current (7.0 mA @ IOUT = 500 mA). On board short circuit, thermal, and overvoltage protection make it possible to use this regulator in particularly harsh operating environments. The Watchdog logic function monitors an input signal (WDI) from the microprocessor or other signal source. When the signal frequency moves outside externally programmable window limits, a RESET signal is generated (RESET). An external capacitor (CDELAY) programs the watchdog window frequency limits as well as the power on reset (POR) and RESET delay. The RESET function is activated by any of three conditions: the watchdog signal moves outside of its preset limits; the output voltage drops out of regulation by more than 4.5%; or the IC is in its power up sequence. The RESET signal is independent of VIN and reliable down to VOUT = 1.0 V. In conjunction with the Watchdog, the ENABLE function controls the regulator’s power consumption. The CS8140’s output stage and its attendant circuitry are enabled by setting the ENABLE lead high. The regulator goes into sleep mode when the ENABLE lead goes low and the watchdog signal moves outside its preset window limits. This unique combination of control functions in the CS8140 gives the microprocessor control over its own power down sequence: http://onsemi.com 6 CS8140, CS8141 Using an emitter sense scheme, the amount of current through the NPN pass transistor is monitored. Feedback circuitry insures that the output current never exceeds a preset limit. i.e. it gives the microprocessor the flexibility to perform housekeeping functions before it powers down. The CS8141 has the same features as the CS8140, except that the CS8141 only responds to input signals (WDI) which are below the preset watchdog frequency threshold. > 30 V VOLTAGE REFERENCE AND OUTPUT CIRCUITRY VIN Precision Voltage Reference VOUT The regulated output voltage depends on the precision band gap voltage reference in the IC. By adding an error amplifier into the feedback loop, the output voltage is maintained within ±4.0% over temperature and supply variation. IO Load Dump Output Stage The composite PNP–NPN output structure (Figure 18) provides 500 mA (min) of output current while maintaining a low drop out voltage (1.25 V) and drawing little quiescent current (7.0 mA). Short Circuit Thermal Shutdown Figure 19. Typical Circuit Waveforms for Output Stage Protection Should the junction temperature of the power device exceed 180°C (typ), the power transistor is turned off. Thermal shutdown is an effective means to prevent die overheating since the power transistor is the principle heat source in the IC. VIN REGULATOR CONTROL FUNCTIONS The CS8140 differs from all other linear regulators in its unique combination of control features. VOUT Watchdog and ENABLE Function Figure 18. Composite Output Stage of the CS8140/1 VOUT is controlled by the logic functions ENABLE and Watchdog (Table 1). The NPN pass device prevents deep saturation of the output stage which in turn improves the IC’s efficiency by preventing excess current from being used and dissipated by the IC. Table 1. VOUT as a Function of ENABLE and Watchdog VOUT (V) WDI Output Stage Protection The output stage is protected against overvoltage, short circuit and thermal runaway conditions (Figure 19). If the input voltage rises above 30 V (e.g. load dump), the output shuts down. This response protects the internal circuitry and enables the IC to survive unexpected voltage transients. ENABLE Slow Normal Fast High Low H 5 5 5 5 5 L 0 5 0 0 0 http://onsemi.com 7 CS8140, CS8141 Batt VIN VOUT When Watchdog is Held High and ENABLE = HIGH Batt ENABLE WDI 0 V RESET 0 V VOUT 0 V POR Normal Operation WDI held High Batt VIN VOUT When Watchdog is Held Low and ENABLE = HIGH Batt ENABLE WDI 0 V RESET 0 V VOUT 0 V POR Normal Operation WDI held Low Batt VIN VOUT When Watchdog is too Slow and ENABLE = HIGH Batt ENABLE WDI 0 V RESET 0 V VOUT 0 V POR Normal Operation Slow WDI signal Batt VIN VOUT When Watchdog is too Fast and ENABLE = HIGH Batt ENABLE WDI 0 V RESET 0 V VOUT 0 V POR Normal Operation Fast WDI signal Batt Batt VIN WDI Held High After a Normal Period of Operation; ENABLE = LOW ENABLE WDI 0 V RESET 0 V VOUT 0 V POR Normal Operation WDI Sleep Mode high POR Normal Operation Batt VIN WDI Held Low or is too Slow after a Normal Period of Operation; ENABLE = LOW Batt ENABLE WDI 0 V RESET 0 V VOUT 0 V POR Normal Operation WDI low Sleep Mode POR Normal Operation Batt WDI Frequency Rises Above the Upper Frequency Threshold After a Normal Period of Operation; ENABLE = LOW (for CS8140 only) Batt VIN ENABLE WDI 0 V RESET 0 V VOUT 0 V POR Normal Operation Sleep Mode Figure 20. Timing Diagrams for Watchdog and ENABLE Functions http://onsemi.com 8 POR Normal Operation CS8140, CS8141 RESET CIRCUIT WAVEFORMS WITH DELAYS INDICATED As long as ENABLE is high or ENABLE is low and the Watchdog signal is normal, VOUT will be at 5.0 V (typ). If ENABLE is low and the Watchdog signal moves outside programmable limits, the output transistor turns off and the IC goes into SLEEP mode. Only the ENABLE circuitry in the IC remains powered up, drawing a quiescent current of 250 µA. The Watchdog monitors the frequency of an incoming WDI signal. If the signal falls outside of the WDI window, a frequency programmable pulse train is generated at the RESET lead (Figure 20) until the correct Watchdog input signal reappears at the lead (ENABLE = HIGH). The lower and upper window threshold limits of the watchdog function are set by the value of CDELAY. The limits are determined according to the following equations for the CS8140: (a) VOUT VR(HI) VR(LO) RESET VR(LO) VR(PEAK) tPOR Figure 21. Power RESET and Power Down VOUT VOUT –4.5% tWDI(LOWER) (1.3 105)CDELAY or < 2.0 µs ≥ 2.0 µs fWDI(LOWER) (7.69 10–6)CDELAY–1 (b) tWDI(UPPER) (3.82 10–4)CDELAY or RESET 5.0 V fWDI(UPPER) (2.62 10–5)CDELAY–1 For the CS8141 the lower limit is determined by the equations in (a) above. The capacitor CDELAY also determines the frequency of the RESET signal and the POWER–ON–RESET (POR) delay period. tPOR Figure 22. Undervoltage Triggered RESET If an undervoltage condition exists, the voltage on the RESET lead goes low and the delay capacitor, CDELAY, is discharged. RESET remains low until output is in regulation, the voltage on CDELAY exceeds the upper switching threshold and the Watchdog input signal is within its set window limits (Figures 21 and 22). The delay after the output is in regulation is: RESET Function The RESET function is activated when the Watchdog signal is outside of its preset window (Figure 20), when the regulator is in its power up state (Figure 21) or when VOUT drops below VOUT –4.5% for more than 2.0 µs (Figure 22) If the Watchdog signal falls outside of the preset voltage and frequency window, a frequency programmable pulse train is generated at the RESET lead (Figure 20) until the correct Watchdog input signal reappears at the lead. The duration of the RESET pulse is determined by CDELAY according to the following equation: tPOR(typ) (4.75 105)CDELAY The RESET delay circuit is also programmed with the external cap CDELAY. The output of the reset circuit is an open collector NPN. RESET is operational down to VOUT = 1.0 V. Both RESET and its delay are governed by comparators with hysteresis to avoid undesirable oscillations. tWDI(RESET) (1.0 104)CDELAY http://onsemi.com 9 CS8140, CS8141 APPLICATION NOTES CS8140 DESIGN EXAMPLE tWDI(LOWER) (1.3 105) 0.8 0.9 CDELAY The CS8140 with its unique integration of linear regulator and control features: RESET, ENABLE and WATCHDOG, provides a single IC solution for a microprocessor power supply. The reset delay, reset duration and watchdog frequency limits are all determined by a single capacitor. For a particular microprocessor the overriding requirement is usually the reset delay (also known as power on reset). The capacitor is chosen to meet this requirement and the reset duration and watchdog frequency follow. The reset delay is given by: tWDI(UPPER) (3.82 104) 1.2 1.1 CDELAY tWDI(LOWER) 76 ms (min) tWDI(UPPER) 41 ms (min) The software must be written so that a watchdog signal arrives at least every 76 ms but not faster than every 41 ms (Figure 23). tPOR(typ) (4.75 105)CDELAY PASS FAIL Assume that the reset delay must be 200 ms minimum. From the CS8140 data sheet the reset delay has a ±37% tolerance due to the regulator. Assume the capacitor tolerance is ±10%. Hz ms 7 141 9 107 13 76 FAIL 24 41 32 31 44 22.5 C = 0.1 µF ±10% tPOR(min) (4.75 105 0.63) CDELAY 0.9 Figure 23. WDI Signal for CDelay = 0.82 µF using CS8140 t (min) CDELAY(min) POR 2.69 105 The CS8141 is identical to the CS8140 except that the CS8141 only has a lower watchdog frequency threshold. The designer using this part need only be concerned with tWDI(LOWER) as shown in Figure 24. CDELAY(min) 0.743 F Closest standard value is 0.82 µF. Minimum and maximum delays using 0.82 µF are 220 ms and 586 ms. The duration of the reset pulse is given by: FAIL TWDI(RESET)(typ) (1.0 104) CDELAY PASS This has a tolerance of ±50% due to the IC, and ±10% due to the capacitor. The duration of the reset pulse ranges from 3.69 ms to 13.5 ms. The watchdog signal can be expressed as a frequency or time. From a programmers point of view, time is more useful since they must ensure that a watchdog signal is issued consistently several times per second. The maximum and minimum watchdog times are given by: Hz ms 7 141 13 76 Figure 24. WDI Signal for CDelay = 0.82 µF using CS8141 ENERGY CONSERVATION AND SMART FEATURES Energy conservation is another benefit of using a regulator with integrated microprocessor control features. Using the CS8140 or CS8141 as indicated in Figure 25, the microprocessor can control its own power down sequence. The momentary contact switch quickly charges C1 through R1. When the voltage across C1 reaches 3.95 V ( the enable threshold), the output switches on and VOUT rises to 5.0 V. After a delay period determined by CDelay, a frequency programmable reset pulse train is generated at the reset output. The pulse train continues until the correct watchdog signal appears at the WDI lead. C1 is now left to discharge through the input impedance of the enable lead (approximately 150 kΩ) and the enable signal disappears. The output voltage remains at 5.0 V as long as the CS8140 continues to receive the correct watchdog signal. tWDI(LOWER) (1.3 105)CDELAY tWDI(UPPER) (3.82 104)CDELAY There is a tolerance of ±20% due to the CS8140. With a capacitor tolerance of ±10%: tWDI(LOWER) (1.3 105) 1.2 1.1 CDelay tWDI(UPPER) (3.82 104) 0.8 0.9 CDelay tWDI(LOWER) 141 ms (max) tWDI(UPPER) 22.5 ms (max) http://onsemi.com 10 CS8140, CS8141 9.0 V VOUT VIN CS8140/1 Switch R1 110 K RESET WDI ENABLE C1 0.1 µF CDELAY GND C2 0.1 µF VCC 10 µF 2.7 kΩ Microprocessor RESET WATCHDOG PORT Figure 25. Application Diagram for CS8140. The CS8140 Provides a 5.0 V Tightly Regulated Supply and Control Function to the Microprocessor. In this Application, the Microprocessor Controls its own Power Down Sequence (see text). ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (–25°C to –40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor C2 shown in Figure 26 should work for most applications, however it is not necessarily the optimized solution. To determine an acceptable value for C2 for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. The microprocessor can power itself down by terminating its watchdog signal. When the microprocessor finishes its housekeeping or power down software routine, it stops sending a watchdog signal. In response, the regulator generates a reset signal and goes into a sleep mode where VOUT drops to 0 V, shutting down the microprocessor. STABILITY CONSIDERATIONS The output or compensation capacitor C2 in Figure 26 helps determine three main characteristics of a linear regulator: start–up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or http://onsemi.com 11 CS8140, CS8141 Battery VOUT VIN C1 * 0.1 µF (optional) Ignition CS8140 ENABLE VCC RESET RESET DELAY 0.1 µF C2 * 10 µF* 2.7 kΩ WATCHDOG PORT WDI GND R*** Microprocessor *C1 is required if regulator is located far from the power source filter. **C2 is required for stability. ***R ≤ 80 kΩ. Figure 26. Application Diagram capacitors have a tolerance of ± 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Increase the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations. CALCULATING POWER DISSIPATION IN A SINGLE OUTPUT LINEAR REGULATOR The maximum power dissipation for a single output regulator (Figure 27) is: PD(max) VIN(max) VOUT(min)IOUT(max) VIN(max)IQ (1) where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). IIN VIN SMART REGULATOR IOUT VOUT Control Features IQ Figure 27. Single Output Regulator With Key Performance Parameters Labeled Once the value of PD(max) is known, the maximum permissible value of RΘJA can be calculated: Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic RJA http://onsemi.com 12 150°C TA PD (2) CS8140, CS8141 series electrical resistances, these resistances are summed to determine the value of RΘJA. The value of RΘJA can then be compared with those in the package section of the data sheet. Those packages with RΘJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. RJA RJC RCS RSA HEAT SINKS A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like MARKING DIAGRAMS D2PAK SEVEN PIN TO–220 SEVEN LEAD CS814x AWLYWW CS814x AWLYWW 1 1 x A WL, L YY, Y WW, W (3) where: RΘJC = the junction–to–case thermal resistance, RΘCS = the case–to–heatsink thermal resistance, and RΘSA = the heatsink–to–ambient thermal resistance. RΘJC appears in the package section of the data sheet. Like RΘJA, it too is a function of package type. RΘCS and RΘSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers. = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week http://onsemi.com 13 CS8140, CS8141 PACKAGE DIMENSIONS TO–220 SEVEN LEAD T SUFFIX CASE 821E–04 ISSUE C Q NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.003 (0.076) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. A G B D L DIM A B C D G H J K L M Q U V U K OPTIONAL CHAMFER M M SEATING PLANE C H M V INCHES MIN MAX 0.600 0.610 0.386 0.403 0.170 0.180 0.028 0.037 0.045 0.055 0.088 0.102 0.018 0.026 1.028 1.042 0.355 0.365 5 NOM 0.142 0.148 0.490 0.501 0.045 0.055 MILLIMETERS MIN MAX 15.24 15.49 9.80 10.23 4.32 4.56 0.71 0.94 1.15 1.39 2.24 2.59 0.46 0.66 26.11 26.47 9.02 9.27 5 NOM 3.61 3.75 12.45 12.72 1.15 1.39 M J TO–220 SEVEN LEAD THA SUFFIX CASE 821H–02 ISSUE A NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. 1. LEADS MAINTAIN A RIGHT ANGLE WITH RESPECT TO THE PACKAGE BODY TO WITH 0.020". –T– C B –Q– E W A U F L K M D 0.356 (0.014) M J 7 PL T Q M N G S http://onsemi.com 14 DIM A B C D E F G J K L M N Q S U W INCHES MIN MAX 0.560 0.590 0.385 0.415 0.160 0.190 0.023 0.037 0.045 0.055 0.568 0.583 0.050 BSC 0.015 0.022 0.728 0.743 0.322 0.337 0.101 0.116 0.090 0.115 0.146 0.156 0.150 0.200 0.460 0.475 3° MILLIMETERS MIN MAX 14.22 14.99 9.77 10.54 4.06 4.82 0.58 0.94 1.14 1.40 14.43 14.81 1.27 BSC 0.38 0.56 18.49 18.87 8.18 8.56 2.57 2.95 2.28 2.91 3.70 3.95 3.81 5.08 11.68 12.07 3° CS8140, CS8141 TO–220 SEVEN LEAD TVA SUFFIX CASE 821J–02 ISSUE A –T– C B –Q– E W A U H F L K M D 0.356 (0.014) M N S 7 PL T Q M G NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. DIM A B C D E F G H J K L M N Q R S U W INCHES MIN MAX 0.560 0.590 0.385 0.415 0.160 0.190 0.023 0.037 0.045 0.055 0.540 0.555 0.050 BSC 0.570 0.595 0.014 0.022 0.785 0.800 0.322 0.337 0.073 0.088 0.090 0.115 0.146 0.156 0.289 0.304 0.164 0.179 0.460 0.475 3° MILLIMETERS MIN MAX 14.22 14.99 9.77 10.54 4.06 4.82 0.58 0.94 1.14 1.40 13.72 14.10 1.27 BSC 14.48 15.11 0.36 0.56 19.94 20.32 8.18 8.56 1.85 2.24 2.28 2.91 3.70 3.95 7.34 7.72 4.17 4.55 11.68 12.07 3° R J D2PAK 7–PIN DPS SUFFIX CASE 936H–01 ISSUE O –T– SEATING PLANE B M U C E 8 NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS B AND M. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH OR GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED 0.025 (0.635) MAX. V DIM A B C D E F G H J K M N U V A 1 2 34 5 6 7 K F G D 7 PL 0.13 (0.005) M T B H J M N http://onsemi.com 15 INCHES MIN MAX 0.326 0.336 0.396 0.406 0.170 0.180 0.026 0.036 0.045 0.055 0.058 0.078 0.050 BSC 0.100 0.110 0.018 0.025 0.204 0.214 0.055 0.066 0.000 0.004 0.256 REF 0.305 REF MILLIMETERS MIN MAX 8.28 8.53 10.05 10.31 4.31 4.57 0.66 0.91 1.14 1.40 1.41 1.98 1.27 BSC 2.54 2.79 0.46 0.64 5.18 5.44 1.40 1.68 0.00 0.10 6.50 REF 7.75 REF CS8140, CS8141 PACKAGE THERMAL DATA Parameter TO–220 SEVEN LEAD D2PAK SEVEN PIN Unit RΘJC Typical 1.6 1.5 °C/W RΘJA Typical 50 10–50* °C/W *Depending on thermal properties of substrate RθJA = RθJC + RθCA. http://onsemi.com 16 CS8140, CS8141 Notes http://onsemi.com 17 CS8140, CS8141 Notes http://onsemi.com 18 CS8140, CS8141 Notes http://onsemi.com 19 CS8140, CS8141 SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). 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