CXD2932AGA-2 GPS Base Band LSI Description The CXD2932AGA-2 is a dedicated LSI for the GPS (Global Positioning System) satellite-based position measurement system. This LSI contains a 32-bit RISC CPU, satellite tracking circuit, 2M-bit mask ROM, RAM, UART, interval timer, and others. This LSI, used together with the RF LSI, enables the configuration of a 2-chip system capable of measuring its position anywhere on the globe. Features • 16-channel GPS receiver capable of simultaneously receiving 16 satellites • Supports differential GPS — Conforms to RTCM SC-104 Ver. 2.1 — Supports DARC • All-in-view measurement • Timer supporting GPS time • 32-bit RISC CPU • 256K-byte program ROM • 40K-byte RAM • Power management function • 1PPS supported • 2-channel UART • 4-channel interval timer • 16-bit general-purpose I/O port • 12-bit successive approximation system A/D converter (4-channel analog switch) 144 pin LFLGA (Plastic) Absolute Maximum Ratings • Supply voltage VDD VSS – 0.5 to 4.6 V V V • Input voltage VI VSS – 0.5 to VDD + 0.5 • Output voltage VO VSS – 0.5 to VDD + 0.5 • Operating temperature Topr –40 to +85 °C • Storage temperature Tstg –50 to +150 °C Recommended Operating Conditions 3.0 to 3.6 • Supply voltage VDD • Operating temperature Topr –40 to +85 °C Input/Output Pin Capacitance • Input capacitance CIN 9 (Max.) • Output capacitance COUT 11 (Max.) • I/O capacitance CI/O 11 (Max.) pF pF pF V Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E03202-PS CXD2932AGA-2 Performance • 16-channel GPS receiver • 32-bit RISC CPU • Receiver frequency: 1575.42MHz (L1 band, CA code) • Reception sensitivity Tracking sensitivity: –145dBm or less (typ.) when using the antenna of 25dBi, NF = 2dB and the RF amplifier with the 25dB gain for the RF block ∗ Reference data using the Sony's reference board. This value is not guaranteed, depending on the conditions. • Time to First Fix (time until initial measurement after power-on) Cold Start (without both ephemeris and almanac): 27 to 58s Warm Start (without ephemeris with almanac): 23 to 45s Hot Start (with both ephemeris and almanac): 6 to 17s ∗ Reference data with elevation angle of 5° or more and no interception environment on June, 2002. Positioning time with 90% possibility. These values are not guaranteed, depending on the conditions. • Positioning accuracy 2DRMS: approx. 5m ∗ Reference data with elevation angle of 5° or more and no interception environment on June, 2002. This value is not guaranteed, depending on the conditions. • Measurement data update time: 1s • Communication format: Sony Binary NMEA-0183 Customized NMEA (9600bps) • All-in-view –2– CXD2932AGA-2 Block Diagram JTAG (ARM-CORE) TAP-CTL (DFTC6) JTAG TCXO/XTCXO (OSC) CLKGEN (CLKGEN) CLKI/CLKO (OSC) CLKOUT BIST (SRAM) SCAN System (SYS_REG) 9 to 18MHz (ARM) 18MHz (TCXO) 6MHz (USB) Interrupt (INT_CNTL) SSD1: 17ch (SSD1) ARM-CORE (A7TDMI) XRS ARBITER (ARBITER) SRAM: 40KB (DMEM_40KB) 32k-Timer (ITU32K) DECODER (DECODER) ROM: 256KB (IMEM_M) UART: 2ch (DUART) TIC (TIC) CLKS[2:0] XCS[3:0] XOE XWE[3:0] ED[31:0] EA[19:0] ADDR: 20 bit DATA: 32 bit TEST[1:0] PORT (PORT) APB-Bridge (APBIF) BUS-I/F (SMI) ROMW USB/DRV (USB) ADDR: 32 bit DATA: 32 bit XGBE XROMI REFCK Timer: 3ch (TMITU) ARM7TDMI XPWRS IFI/IFO(OSC) A/D APB AHB XINT[1:0] RXD[1:0] TXD[1:0] USB-I/F PORT[15:0] ADDR: 20 bit DATA: 32 bit AHB: AMBA High Performance Bus APB: AMBA Peripheral Bus TIC: Test Interface Controller –3– CXD2932AGA-2 Pin Configuration (Top View) 70 67 64 62 59 58 55 54 51 50 47 45 42 39 34 XWE2 XINT1 XRS GBE CLKO CLKI CLKS0 VDD1 VSS1 AVS3 AVD3 AVD1 VRB VIN1 TDO 75 71 68 66 63 60 56 53 49 46 43 41 38 35 31 ROMW XWE3 XWE0 VDD2 XPWRS VSS2 AVS1 VRT VIN3 VIN0 TMS TRST 65 61 78 74 72 69 VDD3 XROMI VSS3 XWE1 CLKS1 XTCXO USBDP 57 XINT0 CLKOUT CLKS2 52 48 TCXO USBDM 44 40 37 36 32 28 AVS2 VIN2 AVD2 VDD11 TCK CCKO 30 26 81 77 73 33 ED4 ED1 XOE TDI REFCK TEST1 83 79 76 29 27 23 ED6 ED2 ED0 VSS11 CCKI IFI 86 82 80 25 24 22 ED8 ED5 ED3 TEST0 IFO VDD10 87 85 84 21 20 19 ED9 ED7 VSS4 RXD1 TXD1 RXD0 16 17 18 90 89 88 VDD4 ED11 ED10 PORT14 PORT15 TXD0 91 92 93 ED12 ED13 ED14 12 94 96 97 8 ED15 VSS5 ED17 VDD9 95 99 101 4 ED16 ED19 ED21 13 15 PORT11 PORT12 VSS10 10 14 PORT9 PORT13 7 11 PORT4 PORT7 PORT10 98 102 105 1 ED18 VDD5 ED24 VSS9 100 104 108 109 112 116 120 124 129 133 137 141 ED20 ED23 VSS6 ED27 ED30 EA1 VSS7 EA8 EA12 EA15 EA19 XCS2 103 107 110 113 115 118 121 125 128 132 135 138 140 ED22 ED26 ED28 ED31 EA0 EA3 EA5 EA9 EA11 VSS8 EA17 VDD8 XCS1 144 5 9 PORT5 PORT8 2 6 PORT1 PORT2 PORT6 143 3 PORT0 PORT3 106 111 114 117 119 122 123 126 127 130 131 134 136 139 142 ED25 ED29 VDD6 EA2 EA4 EA6 EA7 VDD7 EA10 EA13 EA14 EA16 EA18 XCS0 XCS3 –4– CXD2932AGA-2 Pin Description Pin No. Symbol I/O — Description 1 VSS9 2 PORT2 I/O/Z I/O port 2 (See the Application Circuit for setting.) 3 PORT3 I/O/Z I/O port 3 (See the Application Circuit for setting.) 4 PORT4 I/O/Z I/O port 4 (See the Application Circuit for setting.) 5 PORT5 I/O/Z I/O port 5 (See the Application Circuit for setting.) 6 PORT6 I/O/Z I/O port 6 (See the Application Circuit for setting.) 7 PORT7 I/O/Z I/O port 7 (See the Application Circuit for setting.) 8 VDD9 9 PORT8 I/O/Z I/O port 8 (See the Application Circuit for setting.) 10 PORT9 I/O/Z I/O port 9 (See the Application Circuit for setting.) 11 PORT10 I/O/Z I/O port 10 (See the Application Circuit for setting.) 12 PORT11 I/O/Z I/O port 11 (See the Application Circuit for setting.) 13 PORT12 I/O/Z I/O port 12 (See the Application Circuit for setting.) 14 PORT13 I/O/Z I/O port 13 (See the Application Circuit for setting.) 15 VSS10 16 PORT14 I/O/Z I/O port 14 17 PORT15 I/O/Z I/O port 15 18 TXD0 O/Z 19 RXD0 I 20 TXD1 O/Z 21 RXD1 I 22 VDD10 — 23 IFI I 24 IFO O 25 TEST0 I Test (Low level fixed) 26 TEST1 I Test (Low level fixed) 27 CCKI I 28 CCKO O 29 VSS11 — 30 REFCK I Test (Low level fixed) 31 TRST I Test (Open) 32 TCK I Test (Open) 33 TDI I Test (Open) 34 TDO O/Z 35 TMS I 36 VDD11 — VDD 37 AVD2 — A/D converter VDD — — VSS VDD VSS UART transmission data (CH0) UART reception data (CH0) UART transmission data (CH1) UART reception data (CH1) VDD IF signal binary conversion circuit Timer oscillation circuit (32.768kHz ± 100ppm) VSS Test Test (Open) –5– CXD2932AGA-2 Pin No. Symbol I/O Description 38 VIN0 I Analog input (CH0) 39 VIN1 I Analog input (CH1) 40 VIN2 I Analog input (CH2) 41 VIN3 I Analog input (CH3) 42 VRB I Reference input (Bottom) 43 VRT I Reference input (Top) 44 AVS2 — A/D converter VSS 45 AVD1 — PLL VDD 46 AVS1 — PLL VSS 47 AVD3 — USB VDD 48 USBDM I/O/Z USB data + (Not supported in this IC. Pull down with 15kΩ) 49 USBDP I/O/Z USB data – (Not supported in this IC. Pull down with 15kΩ) 50 AVS3 — USB VSS 51 VSS1 — VSS 52 TCXO I 53 XTCXO O 54 VDD1 — 55 CLKS0 I 56 CLKS1 I 57 CLKS2 I 58 CLKI I 59 CLKO O 60 VSS2 — 61 CLKOUT 62 GBE I External bus enable (H-Active) 63 XPWRS I Oscillator enable (H-Active) 64 XRS I Reset (L-Active) 65 XINT0 I External interruption 0 (L-Active) 66 VDD2 67 XINT1 I External interruption 1 (L-Active) 68 XWE0 O External expansion write signal 0 69 XWE1 O External expansion write signal 1 70 XWE2 O External expansion write signal 2 71 XWE3 O External expansion write signal 3 72 VSS3 — VSS 73 XOE O External expansion read signal 74 XROMI I Program area selection (Low: Internal / High: External) O/Z — TCXO crystal oscillator (18.414MHz ± 3ppm) VDD CPU clock selection (CLKS2, CLKS1, CLKS0) = (0, 0, 1): 18.414MHz (TCXO) (CLKS2, CLKS1, CLKS0) = (0, 1, 0): 27.671MHz (TCXO × 1.5) CPU clock oscillator VSS 1PPS output VDD –6– CXD2932AGA-2 Pin No. Symbol I/O I Description 75 ROMW 76 ED0 I/O/Z External expansion data 0 77 ED1 I/O/Z External expansion data 1 78 VDD3 79 ED2 I/O/Z External expansion data 2 80 ED3 I/O/Z External expansion data 3 81 ED4 I/O/Z External expansion data 4 82 ED5 I/O/Z External expansion data 5 83 ED6 I/O/Z External expansion data 6 84 VSS4 85 ED7 I/O/Z External expansion data 7 86 ED8 I/O/Z External expansion data 8 87 ED9 I/O/Z External expansion data 9 88 ED10 I/O/Z External expansion data 10 89 ED11 I/O/Z External expansion data 11 90 VDD4 91 ED12 I/O/Z External expansion data 12 92 ED13 I/O/Z External expansion data 13 93 ED14 I/O/Z External expansion data 14 94 ED15 I/O/Z External expansion data 15 95 ED16 I/O/Z External expansion data 16 96 VSS5 97 ED17 I/O/Z External expansion data 17 98 ED18 I/O/Z External expansion data 18 99 ED19 I/O/Z External expansion data 19 100 ED20 I/O/Z External expansion data 20 101 ED21 I/O/Z External expansion data 21 102 VDD5 103 ED22 I/O/Z External expansion data 22 104 ED23 I/O/Z External expansion data 23 105 ED24 I/O/Z External expansion data 24 106 ED25 I/O/Z External expansion data 25 107 ED26 I/O/Z External expansion data 26 108 VSS6 109 ED27 I/O/Z External expansion data 27 110 ED28 I/O/Z External expansion data 28 111 ED29 I/O/Z External expansion data 29 — — — — — — Test (Low level fixed) VDD VSS VDD VSS VDD VSS –7– CXD2932AGA-2 Pin No. Symbol I/O Description 112 ED30 I/O/Z External expansion data 30 113 ED31 I/O/Z External expansion data 31 114 VDD6 — 115 EA0 O/Z External expansion address 0 116 EA1 O/Z External expansion address 1 117 EA2 O/Z External expansion address 2 118 EA3 O/Z External expansion address 3 119 EA4 O/Z External expansion address 4 120 VSS7 — 121 EA5 O/Z External expansion address 5 122 EA6 O/Z External expansion address 6 123 EA7 O/Z External expansion address 7 124 EA8 O/Z External expansion address 8 125 EA9 O/Z External expansion address 9 126 VDD7 — 127 EA10 O/Z External expansion address 10 128 EA11 O/Z External expansion address 11 129 EA12 O/Z External expansion address 12 130 EA13 O/Z External expansion address 13 131 EA14 O/Z External expansion address 14 132 VSS8 — 133 EA15 O/Z External expansion address 15 134 EA16 O/Z External expansion address 16 135 EA17 O/Z External expansion address 17 136 EA18 O/Z External expansion address 18 137 EA19 O/Z External expansion address 19 138 VDD8 — VDD 139 XCS0 O External expansion chip select 0 140 XCS1 O External expansion chip select 1 141 XCS2 O External expansion chip select 2 142 XCS3 O External expansion chip select 3 143 PORT0 I/O/Z I/O port 0 (See the Application Circuit for setting.) 144 PORT1 I/O/Z I/O port 1 (See the Application Circuit for setting.) VDD VSS VDD VSS –8– CXD2932AGA-2 Analog Characteristics (1) A/D Converter Characteristics Item Symbol (AVD = 3.0 to 3.6V, Topr = –40 to +85°C) Conditions Min. Typ. Resolution Channel Max. Unit 12 Bit 4 Differential linearity error (DLE) AVD = 3.0V Integral linearity error (ILE) Sampling time f = 18.414MHz Conversion time Applicable pins Ch –1.0 +1.0 LSB –1.0 +1.0 LSB 5 µs 15 µs Reference power (Top) VRT VRB AVD V ∗1 Reference power (Bottom) VRB 0 VRT V ∗2 Analog input power VIN0-3 VRB VRT V ∗3 Current consumption AVD = 3.0V 5 mA Applicable pins ∗1 Pin 43 ∗2 Pin 42 ∗3 Pins 38 to 41 (2) USB Characteristics Item (AVD = 3.0 to 3.6V, Topr = –40 to +85°C) Symbol Conditions Min. — Typ. Max. Unit 28 43 Ω Output impedance Zdrv Output voltage (Low) VOL RL = 1.5kΩ to 3.6V — 0.3 V Output voltage (High) VOH RL = 1.5kΩ to GND 2.8 3.6 V Data rise delay time Tr CL = 50pF 75 — ns CL = 350pF — 300 ns Data fall delay time Tf CL = 50pF 75 — ns 300 ns Data delay time ratio Tr/Tf CL = 50pF or 350pF 0.8 1.2 — Crossover voltage Vcrs CL = 50pF or 350pF 1.3 2.0 V Current consumption (during operation) Ica CL = 50pF and VCC = 3.6V — 20 mA Current consumption (during suspension) Icb VCC = 3.6V — 2 mA CL = 350pF Applicable pins Pins 48, 49 –9– CXD2932AGA-2 DC Characteristics (VDD = 3.0 to 3.6V, Topr = –40 to +85°C) Item Symbol Conditions Input voltage (1) (COMS level) High level VIH Low level VIL Input voltage (2) (5V interface) High level VIH Low level VIL Input voltage (3) (Schmitt) High level VIH Low level VIL High level VOH IOH = –4.0mA Low level VOL IOL = 4.0mA High level VOH IOH = –8.0mA Low level VOL IOL = 8.0mA High level VOH IOH = –2.0mA Low level VOL IOL = 8.0mA High level VOH IOH = –2.0mA Low level VOL IOL = 4.0mA Output voltage (1) Output voltage (2) Output voltage (3) Output voltage (4) (5V interface) Min. Typ. Max. Unit V 0.7VDD 0.7VDD 0.2VDD V 5.5 V 0.2VDD V V 0.7VDD 0.2VDD VDD – 0.4 0.4 0.4 0.4 63 mA 3.0V, 27.671MHz 75 mA When external Istb1 timer used 3.0V 3 60 µA Istb2 3.0V 5 100 µA Current consumption (In backup mode) When internal timer used Icur ∗5 ∗6 ∗7 V 3.0V, 18.414MHz Current consumption When GPS (During normal measurement operation) ∗4 V V VDD – 0.8 ∗3 V V VDD – 0.8 ∗2 V V VDD – 0.4 ∗1 V V 0.4 Applicable pins Applicable pins ∗1 Pins 25, 26, 31 to 33, 35, 55 to 57, 74 to 77, 79 to 83, 85 to 89, 91 to 95, 97 to 101, 103 to 107, 109 to 113 ∗2 Pins 2 to 7, 9 to 14, 16, 17, 19, 21, 30, 62, 65, 67, 143, 144 (Use the resistor of 4.7kΩ or less when the pull-down is performed.) ∗3 Pins 63, 64 ∗4 Pins 34, 61 ∗5 Pins115 to 119, 121 to 125, 133 to 137, 139 to 142, 68 to 71, 73, 76, 77, 79 to 83, 85 to 89, 91 to 95, 97 to 101, 103 to 107, 109 to 113 ∗6 Pins 2 to 7, 9 to 14, 16, 17, 143, 144 ∗7 Pins 18, 20 – 10 – CXD2932AGA-2 AC Characteristics (1) External Memory Read Timing (VDD = 3.0 to 3.6V, CL = 40pF, Topr = –40 to +85°C, CPU clock = 18.4MIPS) Item Symbol Read cycle time (0WAIT)∗1 Read cycle time (1WAIT)∗1 Min. Typ. Max. Unit Trcy0 54 ns Trcy1 108 ns Read cycle time (2WAIT)∗1 Trcy2 162 ns Read cycle time (3WAIT)∗1 Trcy3 216 ns Address delay time Tca 0 4 ns Read signal fall delay time Tcfo 2 10 ns Read signal rise delay time Tcro 2 10 ns Read data setup time Tds 22 Read data hold time Tdh ns 0 ∗1 0WAIT (normal), 1 to 3WAIT (settable according to the program) Tsys∗ (1 to 4) Tsys Trcy0 to 3 XCS Tca Tca EA Tcfo Tcro XOE ED Tds ∗ Tsys: CPU clock cycle – 11 – Tdh ns CXD2932AGA-2 (2) External Memory Write Timing (VDD = 3.0 to 3.6V, CL = 40pF, Topr = –40 to +85°C, CPU clock = 18.4MIPS) Symbol Item Write cycle time (0WAIT)∗1 Write cycle time (1WAIT)∗1 Write cycle time (2WAIT)∗1 Write cycle time (3WAIT)∗1 Min. Typ. Max. Unit Twcy0 162 ns Twcy1 216 ns Twcy2 270 ns Twcy3 324 ns Address delay time Tca 0 4 ns Write signal fall delay time Tcfo 2 6 ns Write signal rise delay time Tcro 2 8 ns Write data setup time Tds 2 15 ns Write data hold time Tdh 2 10 ns ∗1 0WAIT (normal), 1 to 3WAIT (settable according to the program) Tsys Tsys∗ (1 to 4) Tsys' Twcy0 to 3 XCS Tca Tca EA Tcfo Tcro XWE ED Tds Tdh ∗ Tsys: CPU clock cycle – 12 – CXD2932AGA-2 Backup Mode When the power supply of the GPS receiver system is off (XPWRS = low: the external pull-down is necessary) and the reset state (XRS = low) is established, the device goes into the low power consumption state (backup mode) where the all oscillators except for the timer stop. The whole internal memory status at this time is retained and the Hot Start/Warm Start can be achieved. In order to cancel this mode, set the XRS pin to high after XPWRS is set to high and then the oscillation stabilization time and the PLL lock-in time are waited. (Normal operation / reset : VDD = 3.0 to 3.6V, backup mode : VDD = 2.0 to 3.6V) Normal Backup Reset Normal OSC output XPWRS XRS Oscillation stabilization time PLL lock-in time (max. 1.0ms) ED[31:0], EA[19:0] Pull-down output PORT[15:0] Hi-Z output XCS[3:0], XWE[3:0], XOE, XTCXO High output TXD[1:0], CLKOUT Low output – 13 – CXD2932AGA-2 Initialization Setting The device initialization is started by setting the reset pin (XRS) to low level. The timing should satisfy the conditions noted below. (1) During power-on (VDD = 3.0 to 3.6V, Topr = –40 to +85°C) XPWRS should rise simultaneously with the power supply. XRS should rise 100ms or more after the power supply and XPWRS have risen. VDD Power supply XPWRS XRS 100ms or more VDD/2 VSS (2) Initialization during operation (VDD = 3.0 to 3.6V, Topr = –40 to +85°C) The internal registers can be initialized during operation by setting the XRS signal to low level for 100µs or more. Keep the XPWRS signal at high level at this time. (The internal memory value is held.) VDD Power supply XPWRS XRS 1µs or more VDD/2 VSS – 14 – CXD2932AGA-2 Application Notes The constants shown in the circuits below are the examples, and do not guarantee the circuit operation. (1) TCXO input (a) When inputting the binary-converted signal The TCXO input signal should be 18.414MHz ± 3ppm. 52 Input Open 53 (b) When performing the self-oscillation with the TCXO and XTCXO pins The TCXO input signal should be 18.414MHz ± 3ppm. For inputting the signal which is not binary converted, the signal should go through the DC cut capacitor. 0.01µF 52 Input 1MΩ 53 (2) CPU clock generation (a) CPU clock selector The CLKS2, CLKS1 and CLKS0 pins are used to select that the TCXO clock is used or that the selfoscillation is performed with the CLKI and CLKO pins. Set the CLKI pin to low when the TCXO clock is used. (CLKS[2:0] = 001: recommendation) CLKS[2:0] CLKI, CLKO CPU frequency 001 — TCXO × 1.0 (18.414MHz) 010 — TCXO × 1.5 (27.671MHz) 101 18 to 27MHz CLKI × 1.0 (18 to 27MHz) 110 12 to 18MHz CLKI × 1.5 (18 to 27MHz) (b) When performing the self-oscillation with the CLKI and CLKO pins The crystal oscillator frequency should be within the values shown above. 22pF 58 12 to 27MHz 1MΩ 59 22pF – 15 – CXD2932AGA-2 (3) Timer clock setting When using the real-time clock (RTC) circuit in the device, connect the crystal oscillator of 32.768kHz ± 100ppm to the CCKI and CCKO pins. When using the external RTC circuit, set the CCKI pin to the low level. See the Port setting for the RTC internal/external selection. 22pF 27 32.768kHz ±100ppm 28 22pF (4) IF signal input This device's IF signal supports only 1.023MHz. When the signal which is not binary-converted is input, the signal should go through the DC cut capacitor. 0.01µF Input 23 1MΩ 24 (5) Serial input/output communication system See the corresponding data sheet for communication because the communication specification differs according to the communication format. See the Port setting for the communication format selection. The transmission data (TXD0 and TXD1) amplitude is 0.4V or less for the low level and VDD – 0.4V or more for the high level. When the LSI and others connected to this operate at 5V and the CMOS level input is used, convert 3V to 5V for input. – 16 – CXD2932AGA-2 (6) Port setting When the power turns on or initialization setting is performed by the reset input, the system starts operation according to the selected port setting. Perform initialization after the setting is changed because the setting can not be changed during operation. Port I/O Description For reset For operation 0 I I Test pin (Low = Normal mode) 1 I I 2 I I Communication format selection PORT[2:1] = (00: Sony Binary, 01: NMEA4800, 10: NMEA9600, 11: Unused) 3 I I RTC selection (High = Internal / Low = External) 4 I I Test pin (High = Normal mode) 5 I I Test pin (Low = Normal mode) 6 I O Unused 7 I O Unused 8 I O Unused 9 I I Antenna sense (Low = Disable / High = Enable) 10 I O Antenna shutdown (Low = Cut) 11 I I Test pin (Low = Normal mode) 12 I O Unused 13 I I/O RTC SIO (Leave open when the internal RTC is selected.) 14 I O RTC SCL (Leave open when the internal RTC is selected.) 15 I O RTC CE (Leave open when the internal RTC is selected.) (7) A/D setting The antenna sense function can be realized by connecting the antenna power supply of the GPS receiver to the A/D channel pins shown below. See the Application Circuit for the resistance value and others. See the Port setting for the antenna sense function disable/enable selection. VIN I/O Description For reset For operation 0 I I Antenna power supply (before current value detection resistor) 1 I I Antenna power supply (after current value detection resistor) 2 I I Test pin (Low level fixed) 3 I I Test pin (Low level fixed) – 17 – Application Circuit VSS VSS 0.1µ VDD 0.1µ 0.1µ VDD TC55V16256FTI <TOSHIBA> XOE ED0 XROMI ED1 ROMW ED2 ED3 VDD3 ED4 ED5 ED7 ED6 ED8 VSS4 ED9 VDD4 ED10 ED11 ED12 ED13 ED14 ED15 VSS5 ED17 ED16 ED18 ED19 VDD5 ED20 ED22 ED21 ED23 ED24 ED25 VSS6 ED26 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 109 ED27 VSS3 72 110 ED28 XWE3 71 111 ED29 XWE2 70 113 ED31 XWE0 68 114 VDD6 XINT1 67 115 EA0 VDD2 66 116 EA1 XINT0 65 117 EA2 XRS 64 118 EA3 XPWRS 63 119 EA4 GBE 62 120 VSS7 EA2 EA1 XCS0 ED16 ED17 0.1µ ED18 122 EA6 CLKO 59 123 EA7 CLKI 58 124 EA8 CLKS2 57 0 ED21 ED22 ED23 XWE1 EA16 CLKS0 55 CXD2932AGA-2 127 EA10 VDD1 54 128 EA11 EA15 1M EA14 0.1µ XTCXO 53 129 EA12 EA13 TCXO 52 VSS1 51 131 EA14 AVS3 50 132 VSS8 USBDP 49 133 EA15 USBDM 48 134 EA16 AVD3 47 135 EA17 AVS1 46 136 EA18 AVD1 45 137 EA19 AVS2 44 A6 43 3 A2 A7 42 4 A1 OE 41 5 A0 UB 40 6 CE I/O16 38 8 I/O2 I/O15 37 9 I/O3 I/O14 36 0.01µ 15k EA17 13 I/O5 I/O10 30 16 I/O8 I/O9 29 A8 27 19 A14 A9 26 20 A13 A10 25 21 A12 22 A16 47µH REFCK PORT14 PORT15 PORT13 PORT11 PORT12 4.7k ED29 ED2 ED28 0.1µ A11 24 A17 23 3 A2 A7 42 4 A1 OE 41 5 A0 UB 40 6 CE 7 I/O1 I/O16 38 8 I/O2 I/O15 37 9 I/O3 I/O14 36 I/O13 35 GND 34 12 GND ED27 ED4 ED26 ED5 ED25 ED6 ED24 ED7 XWE1 EA9 EA16 EA10 EA15 EA11 EA14 EA12 EA13 EA13 EA17 EA6 EA7 EA8 XOE LB 39 ED3 10 I/O4 0.1µ 11 VDD VDD 33 13 I/O5 I/O12 32 14 I/O6 I/O11 31 15 I/O7 I/O10 30 16 I/O8 I/O9 29 17 WE NU 28 18 A15 A8 27 19 A14 A9 26 20 A13 A10 25 21 A12 A11 24 22 A16 A17 23 ED15 ED14 ED13 ED12 0.1µ ED11 ED10 ED9 ED8 EA9 EA10 EA11 EA12 EA13 47k When using antenna sense function (PORT9 = H) VDD 2 OUT 1 47k 0.1µ 1 RESET 2 GND 32.768k 1M VDD ED1 A6 43 MAX6364LUT26 3 RESETIN 4.7k ED0 ED30 0.1µ 47µH VDD11 TMS TDO TDI TCK TRST VSS11 CCKI CCKO TEST1 TEST0 IFO IFI VDD10 RXD1 TXD1 RXD0 TXD0 VSS10 PORT8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PORT9 PORT7 8 XCS0 ED31 A5 44 A3 RN3112Q291A AVD2 37 VDD9 VSS9 PORT2 PORT10 VIN0 38 PORT6 VIN1 39 143 PORT0 PORT3 142 XCS3 PORT4 4 CD 7 EA1 A4 2 PORT10 VIN2 40 6 EA2 15 141 XCS2 5 EA3 XOE 0.1µ 3 GND 4 EA8 1 0.1µ VIN3 41 3 EA4 In external program mode (XROMI = H, GBE = H) 15k 140 XCS1 2 EA5 EA7 NU 28 18 A15 VRT 43 1 VDD 33 I/O12 32 15 I/O7 VRB 42 144 PORT1 GND 34 I/O11 31 139 XCS0 4.7k I/O13 35 14 I/O6 17 WE EA6 LB 39 7 I/O1 138 VDD8 PORT5 – 18 – 130 EA13 A5 44 2 A3 12 GND ED20 CLKS1 56 126 VDD7 1 A4 ED19 10 I/O4 0.1µ 11 VDD VSS2 60 125 EA9 0.1µ EA3 CLKOUT 61 121 EA5 0.1µ EA4 XWE1 69 112 ED30 0.1µ EA5 TC55V16256FTI <TOSHIBA> BATT 6 OUT 5 VCC 4 3.0V VDD ANT PWR 4.7k 22p 0.1µ 22p VSS 0.1µ 0.1µ VSS 0.1µ PORT10 0.01µ RESET TCXO (18.414MHz) CE OSCI VDD 7 8 22p 100 IF (1.023MHz) RXD1 6 22p GND 1PPS 1 5 32.768k 47k VDD (3.3V) RXD0 TXD0 RS5C313 <RICOH> 0.1µ When using on external timer (PORT3 = L) Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXD2932AGA-2 SCL 2 OSCO SIO 3 INT VSS 4 When using on internal timer (PORT3 = H) 10µH CXD2932AGA-2 Package Outline Unit: mm 144PIN LFLGA 0.2 S A 0.10 S 13.0 1.4MAX X PIN 1 INDEX 0.2 S B 0.20 S 13.0 0.01 x4 0.15 S A 0.55 DETAIL X 144 – φ0.40 ± 0.05 R P N M L K J H G F E D C B A φ0.08 M S A B 0.8 B 1 2 3 4 5 6 7 8 9 101112131415 0.5 0.55 0.8 0.9 0.9 0.55 0.5 0.55 3 – φ0.50 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE LFLGA-144P-01 TERMINAL TREATMENT P-LFLGA144-13x13-0.8 TERMINAL MATERIAL JEDEC CODE PACKAGE MASS – 19 – ORGANIC SUBSTRATE NICKEL & GOLD PLATING COPPER 0.5g Sony Corporation