1.8V 12Bit9Bit 30MSPS 40MSPS DAC DAC DAC1267X DAC1233 GENERAL DESCRIPTION The dac1267x is a CMOS 9Bit D/A converter for general applications. Its maximum conversion rate is 40MSPS and supply voltage is 1.8V single. An external 0.7V voltage reference(VBIAS) and a single resistor (RSET) control the full-scale output current. FEATURES · 40MSPS pipeline operation · 1.8V CMOS monolithic construction · ±0.3LSB differential linearity error (typical) · ±1.5LSB integral linearity error (typical) · External voltage reference · 9-Bit voltage parallel input TYPICAL APPLICATION · · · · High Definition Television (HDTV) Hard Disk Drive High Resolution Color Graphics CAE/CAD/CAM FUNCTIONAL BLOCK DIAGRAM AVDD18A AVSS18A AVDD18D AVSS18D Decoder D[8:0] 1st Latch 2nd Latch Buffer CK1 CLK Clock Generator CK2 AVBB18A Current Cell Array CCOMP CK1 + Amp CK2 _ VBIAS IREF Rev 2.4 (Apr. 2002) No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this datasheet is subject to change without any notice. SAMSUNG ELECTRONICS Co. LTD CM Block CCOMP PD CCOMP IO IOB DAC1267X 1.8V 9Bit 40MSPS DAC CORE PIN DESCRIPTION NAME I/O TYPE I/O PAD PIN DESCRIPTION D[8:0] DI picc_abb Digital Input CLK DI picc_abb Clock Input PD DI picc_abb High=power saving standby mode (normally = gnd) VBIAS AI pia_abb External Bias (0.7V) IREF AO poa_abb Full Sale Adjust Control CCOMP AI pia_abb Using Compensation Capacitor IO AO poa_abb Analog Output (output Range : 0.66Vpp) IOB AO poa_abb Analog Output (output Range : 0.66Vpp) AVDD18A AP vdd1t_abb Analog Power AVSS18A AG vss1t_abb Analog Ground AVDD18D DP vdd1t_abb Digital Power AVSS18D DG vss1t_abb Digital Ground AVBB18A AG vbb_abb I/O TYPE ABBR. · · · · · · · · · · AI : DI : AO: DO: AP : DP : AG: DG: AB: DB: Analog Digital Analog Digital Analog Digital Analog Digital Analog Digital Input Input Output Output Power Power Ground Ground Bidirection Bidirection Analog Ground ( bulk bias ) CORE CONFIGURATION AVDD18A AVSS18A AVDD18D AVSS18D AVBB18A IO dac1267x D[8:0] IOB CLK SEC ASIC PD VBIAS IREF CCOMP 2 / 11 ANALOG DAC1267X 1.8V 9Bit 40MSPS DAC ABSOLUTE MAXIMUM RATINGS CHARACTERISTICS SYMBOL VALUE UNIT Supply Voltage AVDD18D, AVDD18A +2.5 V Digital Input Voltage Vin AVSS18D-0.2 to AVDD18D+0.2 V Operating Temperature Range Topr 0 to +70 °C Storage Temperature Range Tstg -55 to +150 °C NOTE: 1. Absolute maximum rating values applied individually while another parameters are within specified operating condition. Function operation under any of these conditions is not implied. 2. Applied voltage must be current limited to specified range. 3. Absolute maximum ratings are value beyond which the device may be damaged permanently. Normal operation is not guaranteed. RECOMMENDED OPERATING CONDITIONS CHARACTERISTICS SYMBOL MIN TYP MAX UNIT 1.6 1.8 2.0 V AVDD18A-AVSS18A Operating Supply Voltage AVDD18D-AVSS18D Digital Input Voltage High VIH 0.8×VDD - - V Digital Input Voltage Low VIL - - 0.2×VDD V Operating Temperature Range TOPR 0 - 70 °C Output Load (effective) RL 150 Ω Reference Voltage VBIAS 0.7 V Clock Cycle Time Tclk 25 - - ns Clock Pulse Width High Tpwh 12 - - ns Clock Pulse Width Low Tpwl 12 - - ns IREF Current Iref 291.6 uA NOTE : 1. It is strongly recommended that to avoid power latch-up all the supply pins (AVDD18A, AVDD18D) be driven from the same source. 2. Voltage on any digital pin that goes below AVSS18D (Digital Ground) by less than 0.2V can induce destructive latch-up. SEC ASIC 3 / 11 ANALOG DAC1267X 1.8V 9Bit 40MSPS DAC DC ELECTRICAL CHARACTERISTICS CHARACTERISTICS SYMBOL MIN TYP MAX UNIT Resolution - - 9 - Bits Differential Linearity Error DLE - 0.3 ±1 LSB Integral Linearity Error ILE - 1.5 ±2 LSB Monotonicity - Zero level Vz 0 - 3 mV Full Scale FS 0.55 0.678 0.75 V Maximum Output Compliance VOC 0 - +0.8 V External Reference Voltage VBIAS - 0.7 - V Guaranteed - NOTES 1. Converter Specifications (unless otherwise specified) AVDD18A=1.8V AVDD18D=1.8V AVSS18A=GND AVSS18D=GND AVBB18A=GND Ta=25°C RL=150Ω , VBIAS=0.7V AC ELECTRICAL CHARACTERISTICS CHARACTERISTICS SYMBOL MIN TYP MAX UNIT Clock Rate fc - - 40 MHz Digital Data Setup Time ts 2 - - ns Digital Data Hold Time th 2 - - ns Analog Output Delay Time Td - 3 - ns Analog Output Rise Time Tr - 12 15 ns Analog Output Fall Time Tf - 13 15 ns Analog Output Settling Time Ts - 91 115 ns Clock and Data Feedthrough FDTHR -29 -27 -25 dB Glitch Impulse GI 90 114 146 pv-sec Pipeline Delay Tpd - 2 - Clocks VDD Supply Current Idd - 6 8 mA Spurious Free Dynamic Range SFDR -45 -50 -60 dB NOTE : · The above parameters are not tested through the temperature range, but these are guaranteed over the full temperature range. · Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Settling time does not include clock and data feedthrough. Glitch impulse include clock and data feedthrough. SEC ASIC 4 / 11 ANALOG DAC1267X 1.8V 9Bit 40MSPS DAC TIMING DIAGRAM Tclk Tpwh Tpwl CLK data D[8:0] Ts Tset Td Th 1LSB 90% 50% IO 10% Tr Tf 111111111 111111111 50% 000000000 Power Down on time typ=100usec Power Down off time typ=200usec PD NOTES : · Output delay measured from the 50% point of the rising edge of CLK to the full scale trasition · Settling time measured from the 50% point of full scale transition to the output remaining within ±1,±2LSB. · Output rise/fall time measured between the 10% and 90% points of full scale transition. SEC ASIC 5 / 11 ANALOG DAC1267X 1.8V 9Bit 40MSPS DAC CORE EVALUATION GUIDE 1.8V 1.8V Cc Cc + Cc + Ct Ct AVBB18A AVSS18D AVDD18D AVSS18A AVDD18A IO MAIN PATH D[8:0] dac1267x IOB R2 PD CCOMP VBIAS CLK R3 IREF R1 0.7V SELECT TEST PATH LOCATION DESCRIPTION Cc 0.1mF Ct 10mF R1 2.4kΩ R2,R3 150Ω 1. Testability Whether you use MUX or the internal logic for testability, it is required to be able to select the values of digital inputs ( D[0] ~ D[8] ) See above figure. Only if it is, you can check the main function (Linearity) ,and output (IO, IOB), VBIAS, IREF and CCOMP pins are reserved for external use. 2. Analysis The voltage applied to VBIAS is measured at IREF node . And the voltage value is proportioned to the reference current value of resistor which is connected to IREF node. So you can estimate the full scale current value by measuring the voltage, and check the DC characteristics of the OPAMP. For reference, as VREF applied to VBIAS node is given at IREF node, the current flowing through RSET is given as VREF/RSET. The full scale current is given as the decimal value equivalent to the digital code. SEC ASIC 6 / 11 ANALOG DAC1267X 1.8V 9Bit 40MSPS DAC PACKAGE CONFIGURATION L1 Ct VDD Cc Ct Cc GND L2 Digital input 01 NC NC 48 02 NC NC 47 03 NC NC 46 04 NC NC 45 05 NC AVSS18A 44 06 D[8] AVSS18A 43 07 D[7] AVDD18A 42 08 D[6] AVDD18A 41 09 D[5] NC 40 10 D[4] AVBB 39 11 D[3] 12 D[2] dac1267x AVDD18A 37 13 D[1] AVDD18A 36 14 D[0] CCOMP 35 15 GND 34 16 GND IREF 33 17 GND IREF 32 18 NC Fclk=40MHz AVBB 38 R1 VBIAS 31 19 CLK DC=0.7V IO 30 20 PD IOB 29 21 AVSS18D AVSS18A 28 22 AVDD18D AVSS18A 27 23 NC NC 26 24 NC NC 25 LOCATION DESCRIPTION Ct 10µF TANTALUM CAPACITOR Cc 0.1µF CERAMIC CAPACITOR L1,L2 FERRITE BEAD ( 0.1mh ) R1 2.4KΩ R2,R3 150Ω SEC ASIC Cc 7 / 11 R3 R2 ANALOG DAC1267X 1.8V 9Bit 40MSPS DAC PACKAGE PIN DESCRIPTION NAME PIN NO I/O TYPE PIN DESCRIPTION AVDD18A 36,37,41,42 AP Analog Power AVBB18A 38,39 AG Analog Ground AVSS18A 27,28,43,44 AG Analog Ground D[0] ~ D[8] 6~14 DI Digital Input Data PD 20 DI Digital Input Data(Low) AVDD18D 22 DP Digital Power AVSS18D 21 DG Digital Ground CLK 19 DI Digital Input Data Analog Voltage Output This chip was developed for 12bit DAC, but finished to develop with 9bit DAC. When you may want to probe IOB, This chip will have the offset error corresponding to 7/8 LSB. IOB 29 AO IO 30 AO Analog Voltage Output VBIAS 31 AI Voltage Reference(0.7V) IREF 32,33 AO CCOMP 34,35 AI Compensation capacitor DO No Connection Analog DC current output Need an termination resistor 1,2,3,4,5,18,23, NC 24,25,26,40,45,46 47,48 SEC ASIC 8 / 11 ANALOG DAC1267X 1.8V 9Bit 40MSPS DAC PC BOARD LAYOUT CONSIDERATIONS 1. PC Board Considerations To minimize Noise On The Power Lines And The Ground Lines, The Digital Inputs Need To Be Shielded And Decoupled. This Trace Length Between Groups Of VDD (AVDD18A,AVDD18D) pins short as possible so as to minimize inductive ringing. 2. Supply Decoupling and Planes For the decoupling capacitor between the power line and the ground line, 0.1µFceramic capacitor is used in parallel with a 10µF tantalum capacitor. The digital power plane (AVDD18D) and analog power plane (AVDD18A) are connected through a ferrite bead, and also the digital ground plane (AVSS18D) and the analog ground plane (AVSS18A). This ferrite bead should be located within 3inches of the dac1267x. The analog power plane supplies power to the dac1267x of the analog output pin and related devices. 3. Analog Signal Interconnection To minimized noise pickup and reflections due to impedance mismatch, the dac1267x should be located as close as possible to the output connector. The line between DAC output and monitor input should also be regarded as a transmission line. Due to the fact, it can cause problems in transmission line mismatch. As a solution to these problems, the double-termination methods used. By using this, both ends of the termination lines are matched, providing an ideal, non-reflective system. SEC ASIC 9 / 11 ANALOG DAC1267X 1.8V 9Bit 40MSPS DAC PHANTOM CELL INFORMATION IREF CCOMP AVDD18A AVDD18A IO IOB AVDD18A VBIAS AVSS18A AVBB18A DAC1267X AVSS18A AVSS18A AVBB18A PD AVDD18D AVDD18D AVSS18D AVSS18D CLK D[2] D[3] Property D[4] D[5] D[6] D[7] D[8] D[1] D[0] Pin Pin Name Pin Layout Guide Usage AVDD18A External AP 1.It is recommended that you use thick analog power metal(more than 10um each). AVSS18A External AG When connected to PAD, each path should be kept as short as possible. 2. Digital Power and analog power must be used separately. AVDD18D External / Internal DP AVSS18D External / Internal DG 3. In Phantom cell in case of many ports of one power name , you must drag the ports individually to PAD in parallel. AVBB18A External / Internal AG 4. Customer must use two PAD's individually for analog power ports because of PAD's current limitation. D[8:0] External / Internal DI PD External / Internal DI IREF External AB VBIAS External AB 1.Digital input Signal lines must have same length to reduce propagation delay. 1.Analog Bi-direction line must be kept as short as possible. 2.Any other should not across these lines except power metal. CCOMP External AB IO External AO 1. Analog output line should be kept as short as possible. 2. These lines must have the same metal length because of voltage drop through the IOB External AO metal line 1. Separated from the analog clean signals if possible. CLK External / Internal DI 2. Do not exceed the length by 100um.- SEC ASIC 10 / 11 ANALOG DAC1267X 1.8V 9Bit 40MSPS DAC FEEDBACK REQUEST We appreciate your interest in out products. If you have more questions, please specify in the attached form. Thank you very much. DC / AC ELECTRICAL CHARACTERISTIC Characteristics Min Typ Max Unit Supply Voltage V Power dissipation mW Resolution Bits Analog Output Voltage V Operating Temperature °C Output Load Capacitor pF Output Load Resistor Ω Integral Non-Linearity Error LSB Differential Non-Linearity Error LSB Maximum Conversion Rate MHz Remarks VOLTAGE OUTPUT DAC Reference Voltage TOP V BOTTOM Analog Output Voltage Range Digital Input Format V Binary Code or 2's Complement Code CURRENT OUTPUT DAC - Analog Output Maximum Current mA Analog Output Maximum Signal Frequency MHz Reference Voltage V External Resistor for Current Setting(RSET) Ω Pipeline Delay sec Do you want to Power down mode? Do you want to Internal Reference Voltage (BGR)? Which do you want to Serial Input TYPE or parallel Input TYPE? Do you need 3.3v and 1.8V power supply in your system? SEC ASIC 11 / 11 ANALOG DAC1267X 1.8V 9Bit 40MSPS DAC HISTORY CARD Version Date Modified Items Ver 2.0 Modified Version DAC1267X was developed for 12bit 40MHz DAC, but test result 01.06.21 didn't meet 12bit performance. So, the specifications of DAC1267X are modified to 9bit 40MHz DAC and datasheet is also modified. Ver 2.1 01.07.04 Ver 2.2 01.07.05 Typo correction. Ver 2.3 01.07.09 Ver 2.4 02.04.22 Phantom Cell information update Comments Modified Version Typo and wrong information are corrected. Modified Version Newly Updated SEC ASIC ANALOG