Surface Mount RF PIN Low Distortion Attenuator Diodes Technical Data HSMP-381x Series and HSMP-481x Series Features • Diodes Optimized for: – Low Distortion Attenuating – Microwave Frequency Operation • Surface Mount Packages – Single and Dual Versions – Tape and Reel Options Available • Low Failure in Time (FIT) Rate[1] Note: 1. For more information see the Surface Mount PIN Reliability Data Sheet. Package Lead Code Identification, SOT-23 (Top View) SINGLE 3 SERIES 3 1 1 #0 2 COMMON ANODE 3 1 #3 2 DUAL CATHODE 3 #2 2 COMMON CATHODE 3 1 #4 2 Package Lead Code Identification, SOT-323 (Top View) SINGLE SERIES B C COMMON ANODE COMMON CATHODE E F DUAL CATHODE Description/Applications The HSMP-381x series is specifically designed for low distortion attenuator applications. The HSMP-481x products feature ultra low parasitic inductance in the SOT-23 and SOT-323 packages. They are specifically designed for use at frequencies which are much higher than the upper limit for conventional diodes. A SPICE model is not available for PIN diodes as SPICE does not provide for a key PIN diode characteristic, carrier lifetime. 1 2 4810 481B 2 Absolute Maximum Ratings[1] TC = +25°C Symbol Parameter If PIV Tj Tstg θjc Forward Current (1 µs Pulse) Peak Inverse Voltage Junction Temperature Storage Temperature Thermal Resistance[2] Unit SOT-23 SOT-323 Amp V °C °C °C/W 1 Same as VBR 150 -65 to 150 500 1 Same as VBR 150 -65 to 150 150 Notes: 1. Operation in excess of any one of these conditions may result in permanent damage to the device. 2. TC = +25°C, where TC is defined to be the temperature at the package pins where contact is made to the circuit board. Electrical Specifications TC = +25°C (Each Diode) Conventional Diodes Part Number HSMP- Package Marking Code 3810 3812 3813 3814 381B 381C 381E 381F E0[1] E2[1] E3[1] E4[1] E0[2] E2[2] E3[2] E4[2] Lead Code Configuration 0 2 3 4 B C E F Single Series Common Anode Common Cathode Single Series Common Anode Common Cathode Test Conditions Minimum Maximum Maximum Minimum Breakdown Total Total High Voltage Resistance Capacitance Resistance VBR (V) RT (Ω) CT (pF) RH (Ω) Maximum Low Resistance RL (Ω) 100 3.0 0.35 1500 10 VR = VBR Measure IR ≤ 10 µA IF = 100 mA f = 100 MHz VR = 50 V f = 1 MHz IR = 0.01 mA f = 100 MHz IF = 20 mA f= 100 MHz High Frequency (Low Inductance, 500 MHz – 3 GHz) PIN Diodes Part Number HSMP- Package Marking Code Lead Code 4810 481B EB EB B[1] B[2] Configuration Dual Cathode Dual Cathode Test Conditions Notes: 1. Package marking code is white. 2. Package laser marked. Minimum Maximum Typical Maximum Typical Breakdown Series Total Total Total Voltage Resistance Capacitance Capacitance Inductance VBR (V) RS (Ω) CT (pF) CT (pF) LT (nH) 100 3.0 0.35 0.4 1.0 VR = VBR Measure IR ≤ 10 µA IF = 100 mA VR = 50 V f = 1 MHz VR = 50 V f = 1 MHz VR = 0 V f = 500 MHz – 3 GHz 3 Typical Parameters at TC = 25°C Part Number HSMP- Series Resistance RS (Ω) Carrier Lifetime τ (ns) Reverse Recovery Time Trr (ns) Total Capacitance CT (pF) 381x 75 1500 300 0.27 @ 50 V IF = 1 mA f = 100 MHz IF = 50 mA IR = 250 mA VR = 10 V IF = 20 mA 90% Recovery f = 1 MHz Test Conditions Typical Parameters at TC = 25°C (unless otherwise noted), Single Diode 0.35 1 MHz 0.30 0.25 30 MHz 0.20 INPUT INTERCEPT POINT (dBm) 0.40 RF RESISTANCE (OHMS) TOTAL CAPACITANCE (pF) 120 10000 0.45 TA = +85°C TA = +25°C TA = –55°C 1000 100 10 frequency>100 MHz 0.15 0 2 4 6 8 1 0.01 10 12 14 16 18 20 1 10 100 IF – FORWARD BIAS CURRENT (mA) REVERSE VOLTAGE (V) Figure 1. RF Capacitance vs. Reverse Bias. 100 IF – FORWARD CURRENT (mA) 0.1 Figure 2. RF Resistance vs. Forward Bias Current. Diode Mounted as a 110 Series Attenuator in a 50 Ohm Microstrip 100 and Tested at 123 MHz 90 80 70 60 50 40 1000 100 10 DIODE RF RESISTANCE (OHMS) Figure 3. 2nd Harmonic Input Intercept Point vs. Diode RF Resistance. Typical Applications for Multiple Diode Products VARIABLE BIAS 10 1 RF IN/OUT INPUT 0.1 125°C 25°C –50°C 0.01 0 0.2 0.4 0.6 0.8 1.0 1.2 VF – FORWARD VOLTAGE (mA) Figure 4. Forward Current vs. Forward Voltage. FIXED BIAS VOLTAGE Figure 5. Four Diode π Attenuator. See Application Note 1048 for Details. 4 Typical Applications for HSMP-481x Low Inductance Series Microstrip Series Connection for HSMP-481x Series In order to take full advantage of the low inductance of the HSMP-481x series when using them in series applications, both lead 1 and lead 2 should be connected together, as shown in Figure 7. Microstrip Shunt Connections for HSMP-481x Series In Figure 8, the center conductor of the microstrip line is interrupted and leads 1 and 2 of the HSMP-481x series diode are placed across the resulting gap. This forces the 1.5 nH lead inductance of leads 1 and 2 to appear as part of a low pass filter, reducing the shunt parasitic inductance and increasing the maximum available attenuation. The 0.3 nHof shunt inductance external to the diode is created by the via holes, and is a good estimate for 0.032" thick material. 3 1 2 HSMP-481x Figure 6. Internal Connections. Figure 7. Circuit Layout. 50 OHM MICROSTRIP LINES 1.5 nH Rj PAD CONNECTED TO GROUND BY TWO VIA HOLES Figure 8. Circuit Layout. 1.5 nH 0.3 pF 0.3 nH Rj ≈ 0.08 I b0.9 + 2.5 0.3 nH Figure 9. Equivalent Circuit. 5 Typical Applications for HSMP-481x Low Inductance Series (continued) Co-Planar Waveguide Groundplane Co-Planar Waveguide Shunt Connection for HSMP-481x Series Center Conductor Groundplane Co-Planar waveguide, with ground on the top side of the printed circuit board, is shown in Figure 10. Since it eliminates the need for via holes to ground, it offers lower shunt parasitic inductance and higher maximum attenuation when compared to a microstrip circuit. Figure 10. Circuit Layout. Rj 0.3 pF 0.75 nH Figure 11. Equivalent Circuit. Equivalent Circuit Model HSMS-381x Chip* Rs Rj 2.5 Ω Cj RT = 2.5 + R j 0.18 pF* CT = CP + Cj * Measured at -20 V 80 R j = 0.9 Ω I I = Forward Bias Current in mA *See AN1124 for package models. 6 Assembly Information SOT-323 PCB Footprint A recommended PCB pad layout for the miniature SOT-323 (SC-70) package is shown in Figure 12 (dimensions are in inches). This layout provides ample allowance for package placement by automated assembly equipment without adding parasitics that could impair the performance. 0.026 0.07 Agilent’s diodes have been qualified to the time-temperature profile shown in Figure 14. This profile is representative of an IR reflow type of surface mount assembly process. 0.035 0.016 Figure 12. PCB Pad Layout (dimensions in inches). SOT-23 PCB Footprint 0.037 0.95 0.037 0.95 SMT Assembly Reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., IR or vapor phase reflow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. Components with a low mass, such as the SOT-323/-23 package, will reach solder reflow temperatures faster than those with a greater mass. After ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. The preheat zones increase the temperature of the board and components to prevent thermal shock and begin evaporating solvents from the solder paste. The reflow zone briefly elevates the temperature sufficiently to produce a reflow of the solder. The rates of change of temperature for the ramp-up and cooldown zones are chosen to be low enough to not cause deformation of the board or damage to components due to thermal shock. The maximum temperature in the reflow zone (TMAX) should not exceed 235°C. These parameters are typical for a surface mount assembly process for Agilent diodes. As a general guideline, the circuit board and components should be exposed only to the minimum temperatures and times necessary to achieve a uniform reflow of solder. 250 TMAX 0.079 2.0 0.035 0.9 0.031 0.8 DIMENSIONS IN inches mm Figure 13. PCB Pad Layout. TEMPERATURE (°C) 200 150 Reflow Zone 100 Preheat Zone Cool Down Zone 50 0 0 60 120 180 TIME (seconds) Figure 14. Surface Mount Assembly Profile. 240 300 7 Package Dimensions Outline SOT-323 (SC-70) Outline 23 (SOT-23) PACKAGE MARKING CODE (XX) 1.30 (0.051) REF. 1.02 (0.040) 0.89 (0.035) 2.20 (0.087) 2.00 (0.079) XXX DATE CODE (X) 0.54 (0.021) 0.37 (0.015) PACKAGE MARKING CODE (XX) 1.35 (0.053) 1.15 (0.045) 3 1.40 (0.055) 1.20 (0.047) XXX 1 0.650 BSC (0.025) 0.425 (0.017) TYP. 2.20 (0.087) 1.80 (0.071) DATE CODE (X) 0.50 (0.024) 0.45 (0.018) 2.65 (0.104) 2.10 (0.083) 2 2.04 (0.080) 1.78 (0.070) TOP VIEW 0.10 (0.004) 0.00 (0.00) 0.30 REF. 0.25 (0.010) 0.15 (0.006) 1.00 (0.039) 0.80 (0.031) 10° 0.152 (0.006) 0.066 (0.003) 3.06 (0.120) 2.80 (0.110) 0.30 (0.012) 0.10 (0.004) 1.02 (0.041) 0.85 (0.033) 0.20 (0.008) 0.10 (0.004) 0.69 (0.027) 0.45 (0.018) 0.10 (0.004) 0.013 (0.0005) DIMENSIONS ARE IN MILLIMETERS (INCHES) SIDE VIEW DIMENSIONS ARE IN MILLIMETERS (INCHES) Package Characteristics Lead Material ................................... Copper (SOT-323); Alloy 42 (SOT-23) Lead Finish ............................................................................ Tin-Lead 85-15% Maximum Soldering Temperature .............................. 260°C for 5 seconds Minimum Lead Strength .......................................................... 2 pounds pull Typical Package Inductance .................................................................. 2 nH Typical Package Capacitance .............................. 0.08 pF (opposite leads) Ordering Information Specify part number followed by option. For example: HSMP - 381x - XXX Bulk or Tape and Reel Option Part Number; x = Lead Code Surface Mount PIN Option Descriptions -BLK = Bulk, 100 pcs. per antistatic bag -TR1 = Tape and Reel, 3000 devices per 7" reel -TR2 = Tape and Reel, 10,000 devices per 13" reel Tape and Reeling conforms to Electronic Industries RS-481, “Taping of Surface Mounted Components for Automated Placement.” END VIEW Device Orientation REEL TOP VIEW END VIEW 4 mm 8 mm CARRIER TAPE USER FEED DIRECTION ### ### ### ### Note: “###” represents Package Marking Code, Date Code. COVER TAPE Tape Dimensions For Outline SOT-323 (SC-70 3 Lead) P P2 D P0 E F W C D1 t1 (CARRIER TAPE THICKNESS) Tt (COVER TAPE THICKNESS) K0 8° MAX. A0 DESCRIPTION 5° MAX. B0 SYMBOL SIZE (mm) SIZE (INCHES) CAVITY LENGTH WIDTH DEPTH PITCH BOTTOM HOLE DIAMETER A0 B0 K0 P D1 2.24 ± 0.10 2.34 ± 0.10 1.22 ± 0.10 4.00 ± 0.10 1.00 + 0.25 0.088 ± 0.004 0.092 ± 0.004 0.048 ± 0.004 0.157 ± 0.004 0.039 + 0.010 PERFORATION DIAMETER PITCH POSITION D P0 E 1.55 ± 0.05 4.00 ± 0.10 1.75 ± 0.10 0.061 ± 0.002 0.157 ± 0.004 0.069 ± 0.004 CARRIER TAPE WIDTH THICKNESS W t1 8.00 ± 0.30 0.255 ± 0.013 0.315 ± 0.012 0.010 ± 0.0005 COVER TAPE WIDTH TAPE THICKNESS C Tt 5.4 ± 0.10 0.062 ± 0.001 0.205 ± 0.004 0.0025 ± 0.00004 DISTANCE CAVITY TO PERFORATION (WIDTH DIRECTION) F 3.50 ± 0.05 0.138 ± 0.002 CAVITY TO PERFORATION (LENGTH DIRECTION) P2 2.00 ± 0.05 0.079 ± 0.002 www.semiconductor.agilent.com Data subject to change. Copyright © 1999 Agilent Technologies 5968-5427E (11/99)