GSM31P256KB-I66 GSM31P512KB-I66 GSI TECHNOLOGY GSM31P256KB-I66 GSM31P512KB-I66 256KB / 512KB Modules COASt 3.1 Specification Features Functional Description (cont’d) • • • • The GSM31P256KB-I66, and 256KB module, use GSI’s GS81132Q 32KX32 synchronous burst SRAM and a single 5V 8Kx8 SRAM for the tag. The GSM14P512K-I66, a 512KB module, use GSI’s GS82032Q 64KX32 synchronous burst SRAM and a single 5V 32Kx8 SRAM for the tag. For Intel Pentium CPU based systems Operates with clock speeds up to 66MHz Separate 5V and 3.3V power supplies Low cost and low profile card design using 160 gold plated leads • Multiple ground pin and decopling capacitors provide maximum noise protection. • Conform to Intel COASt 3.1 specification Pentium is a trademark of Intel Corp. Functional Description The GSM31P256KB-I66 and the GSM31P512KB-I66 are the secondary cache module designed for use with Intel Pentium CPU based system. These modules use GSI’s Synchronous Burst SRAMs in plastic surface mount packages mounted on a multilayer epoxy laminate (FR-4) board. The 3.3V data RAM and the 5V tag RAM provide an exact interface between the module and PC chip set. Four presence detect bits (PD) allow the system to recognize the type of cache configuration present. The low profile card edge package allows 160 signal leads to be placed on a module, measuring 4.35 inches long, a maximum of 0.310 inches thick and a maximum of 1.14 inches tall. This compact design allows the OEM to make better use of the real estate on the mother-board for added functions or smaller design for cost reduction. All inputs and outputs and TTL compatible and operate from two separate 5V and 3.3V power supplies. The use of multiple ground pins and decoupling capacitors on-board reduces failure due to noise. Functional Block Diagram - GSM31P256KB-I66 TIO[7:0] TWE A[17:5] TIO[7:0] TWE A[18:5] D[7:0] 8kx8 WE 5V A[12:0] OE CE CE ECS2 ECS1 A[17:3] COE CWE[3:0] D[31:0] ADSP ADSC ADV CCS GWE BWE D[7:0] 16kx8 WE 5V A[13:0] OE CE CE ECS2 ECS1 A[18:3] COE CWE[3:0] D[31:0] ADSP ADSC ADV CCS GWE BWE Vcc5 A[14:0] OE WE[3:0] D[31:0] ADSP ADSC ADV CS GWE BWE Functional Block Diagram - GSM31P512KB-I66 32Kx32 Pipelined Burst SRAM CE2 CE2 Vcc5 A[15:0] OE WE[3:0] D[31:0] ADSP ADSC ADV CS GWE BWE 64Kx32 Pipelined Burst SRAM CE2 CE2 Vcc3 Vcc3 CWE[7:4] D[63:32] CLK0 PD[3:0] CLK NC GND Vcc3,Vcc5 GSI Technology A[14:0] OE WE[3:0] D[31:0] ADSP ADSC ADV CS GWE BWE Power Supplies 32Kx32 Pipelined Burst SRAM CWE[7:4] D[63:32] CLK0 PD[3:0] CE2 CE2 Vcc3,Vcc5 Vcc3 1/4 CLK NC GND Power Supplies A[15:0] OE WE[3:0] D[31:0] ADSP ADSC ADV CS GWE BWE 64Kx32 Pipelined Burst SRAM CE2 CE2 Vcc3 09/15/97 GSM31P256KB-I66 GSM31P512KB-I66 GSI TECHNOLOGY GSM31P256KB-I66 GSM31P512KB-I66 256KB / 512KB Modules Pin Configuration Pin Description GND TIO1 TIO7 TIO5 TIO3 NC VCC5 NC ADV GND COE CWE5 CWE7 CWE1 VCC5 CWE3 NC NC GND NC A4 A6 A8 A10 VCC5 A17 GND A9 A14 A15 NC PD0 PD2 NC GND CLK0 GND D63 VCC5 D61 D59 D57 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 GND TIO0 TIO2 TIO6 TIO4 NC VCC3 TWE ADSC GND CWE4 CWE6 CWE0 CWE2 VCC3 CCS GWE BWE GND A3 A7 A5 A11 A16 VCC3 A18(1) GND A12 A13 ADSP ECS1 ECS2 PD1 PD3 GND NC GND D62 VCC3 D60 D58 D56 GND D55 D53 D51 D49 GND D47 D45 D43 VCC5 D41 D39 D37 GND D35 D33 D31 VCC5 D29 D27 D25 GND D23 D21 D19 VCC5 D17 D15 D13 GND D11 D9 D7 VCC5 D5 D3 D1 GND 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 GND D54 D52 D50 D48 GND D46 D44 D42 VCC3 D40 D38 D36 GND D34 D32 D30 VCC3 D28 D26 D24 GND D22 D20 D18 VCC3 D16 D14 D12 GND D10 D8 D6 VCC3 D4 D2 D0 GND GSI Technology COASt 3.1 Specification Pin Name Type Description A[18:3] I Cache Address Inputs ADSC I Cache Address Status ADSP I Processor Address Status ADV I Burst Address Advance BWE I Byte Write Enable CCS I Chip Select CLK0 I System Clock COE I Cache Output Enable CWE[7:0] I Cache Write Enables D[63:0] I/O Cache Data Input/Output ECS[1:0] I External Chip Select GWE I Global Write Enable PD[3:0] O Presence Detect Outputs TIO[7:0] I/O Tag Inputs/Outputs TWE I Tag Write Enable Vcc3 - 3.3V Power Supply Vcc5 - 5V Power Supply GND - Ground NC - No Connect Notes: 1. Pin 26, A18, is a no connect in the GSM14P256K-I66 version Presence Detect Table PD3 PD2 PD1 PD0 Device Indicated NC NC NC NC No Module Present NC GND NC NC GSM14P256K-I66 GND NC NC NC GSM14P512K-I66 2/4 09/15/97 GSM31P256KB-I66 GSM31P512KB-I66 GSI TECHNOLOGY GSM31P256KB-I66 GSM31P512KB-I66 256KB / 512KB Modules COASt 3.1 Specification Absolute Maximum Ratings Parameter Symbol Value Unit Vcc3 Vcc5 -0.5 to +4.6 -0.5 to 6.0 V V Ta 0 to +70 Supply Voltage 3.3V Vcc Pins 5.0V Vcc Pins Operating Temperature Storage Temperature Ts o C oC -55 to +125 Recommended Operating Conditions Parameter Supply Voltage 3.3V Vcc Pins 5.0V Vcc Pins Symbol Min Typ Max Unit Vcc3 Vcc5 3.135 4.75 3.3 5.0 3.6 5.25 V V Ta 0 - +70 o Operating Temperature Input High Voltage Vih 2.0 - Vcc+0.3 Input Low Voltage Vil -0.3 - 0.8 Symbol Max Unit Address Input Capacitance CIN1 20 pF Control Signal Input Capacitance CIN2 10 pF TAG Input Capacitance CIN3 10 pF Output Enable Capacitance CIN4 15 pF Data I/O Capacitance CI/O 10 pF C oC Capacitance Parameter Note: These parameters are guaranteed by design, but not tested. DC Electrical Characteristics Over the Operating Range Parameter Test Condition Symbol Min Max Unit Input Leakage Current (Data & Control) VIN=0 to Vcc3 ILI - ± 20 uA Output Leakage Current (Data & Control) VOUT=0 to Vcc3, CS≥VIH IOUT - ± 20 uA Output High Voltage IOH=-4.0mA VOH 2.4 - V Output Low Voltage IOL=8.0mA VOL - 0.4 V Operating Supply Current, 5V Power Vcc5=Max, IOUT=0mA, f=Max Icc5 - 180 mA Operating Supply Current, 3.3V Power Vcc3=Max, IOUT=0mA, f=Max Icc3 - 500 mA AC Standby Supply Current, 3.3V Power Vcc=Max, CS≥VIH, f=max ISB3 - 80 mA Full CMOS Standby Current Vcc=Max, CS≥Vcc3-0.2, f=0MHz, VIN>Vcc3-0.2 or VIN<0.2 ISB31 - 40 mA GSI Technology 3/4 09/15/97 GSM31P256KB-I66 GSM31P512KB-I66 GSI TECHNOLOGY GSM31P256KB-I66 GSM31P512KB-I66 256KB / 512KB Modules COASt 3.1 Specification Ordering Information Part Number GSM31P256KB-I66 GSM31P512KB-I66 Cache Size 256KB 512KB Speed 66MHz 66MHz Package Dimension Front View 1.13 ± 0.01 4.34 ± 0.01 .482 min. .500 max. Component Area 2.16 ± 0.01 .05 ± 0.01 TYP. 2 Places 1.95 ± 0.01 .295 min. .305 max. PIN 160 PIN 81 Back View No Component .15. .074 ± .002 PIN 80 GSI Technology 4/4 PIN 1 09/15/97