HCF4096B GATED J-K MASTER SLAVE FLIP-FLOP ■ ■ ■ ■ ■ ■ ■ 16MHz TOGGLE RATE (Typ.) at VDD - VSS = 10V GATED INPUTS QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DESCRIPTION HCF4096B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF4096B is a J-K Master-Slave Flip-Flop featuring separate AND gating of multiple J and K inputs. The gated J-K input control transfers DIP SOP ORDER CODES PACKAGE TUBE T&R DIP SOP HCF4096BEY HCF4096BM1 HCF4096M013TR information into the master section during clocked operation. Information on the J-K inputs is transferred to the Q and Q outputs on the positive edge of the clock pulse. SET and RESET inputs (active high) are provided for asynchronous operation. PIN CONNECTION September 2002 1/10 HCF4096B INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 3, 4, 5 11, 10, 9 8 6 13 2 12 1 J Inputs K Inputs Q Output Q Output Set Inputs(Active High) Reset Inputs(Active High) Clock Inputs Not Connected 7 J1, J2, J3 K1, K2, K3 Q Q SET (S) RESET (R) CLOCK NC VSS 14 VDD Negative Supply Voltage Positive Supply Voltage TRUTH TABLE : SYNCHRONOUS OPERATION (S=0 R=0) INPUTS BEFORE POSITIVE CLOCK TRANSITION OUTPUTS AFTER POSITIVE CLOCK TRANSITION J* K* Q L L H H L H L H L H Q NO CHANGE H L TOGGLES (*) : J=J1 • J2 • J3, K=K1 • K2 • K3 TRUTH TABLE : ASYNCHRONOUS OPERATION (J and K DON’T CARE) INPUTS BEFORE POSITIVE CLOCK TRANSITION S R Q L L H H L H L H L H L (*) : L = Vss, H = Vdd 2/10 OUTPUTS AFTER POSITIVE CLOCK TRANSITION Q NO CHANGE H L L HCF4096B FUNCTIONAL DIAGRAM LOGIC DIAGRAM 3/10 HCF4096B ABSOLUTE MAXIMUM RATINGS Symbol VDD Parameter Supply Voltage VI DC Input Voltage II DC Input Current PD Value Unit -0.5 to +22 V -0.5 to VDD + 0.5 ± 10 V mA 200 100 mW mW Top Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature -55 to +125 °C Tstg Storage Temperature -65 to +150 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol VDD Parameter Supply Voltage VI Input Voltage Top Operating Temperature Value Unit 3 to 20 V 0 to VDD V -55 to 125 °C DC SPECIFICATIONS Test Condition Symbol IL VOH VOL VIH VIL IOH IOL 4/10 Parameter Quiescent Current High Level Output Voltage Low Level Output Voltage VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 High Level Input Voltage Low Level Input Voltage Output Drive Current Output Sink Current VO (V) 0/5 0/5 0/10 0/15 0/5 0/10 0/15 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 Value |IO| VDD (µA) (V) <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 TA = 25°C Min. Typ. Max. 0.02 0.02 0.02 0.04 1 2 4 20 4.95 9.95 14.95 -40 to 85°C -55 to 125°C Min. Min. 30 60 120 600 4.95 9.95 14.95 0.05 0.05 0.05 4.95 9.95 14.95 3.5 7 11 1.5 3 4 -3.2 -1 -2.6 -6.8 1 2.6 6.8 3.5 7 11 V V 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 µA V 0.05 0.05 0.05 1.5 3 4 -1.15 -0.36 -0.9 -2.4 0.36 0.9 2.4 Max. 30 60 120 600 0.05 0.05 0.05 3.5 7 11 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 Max. Unit V mA mA HCF4096B Test Condition Symbol II CI Parameter Input Leakage Current Input Capacitance VI (V) 0/18 VO (V) Value |IO| VDD (µA) (V) Any Input Any Input 18 TA = 25°C Min. Typ. Max. ±10-5 ±0.1 5 7.5 -40 to 85°C -55 to 125°C Min. Min. Max. ±1 Unit Max. ±1 µA pF The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns) Test Condition Symbol Parameter tPLH tPHL Propagation Delay Time tPLH tPHL Propagation Delay Time (Set or Reset) tTLH tTHL Transition Time fCL tW tr, tf tW tsetup Maximum Clock Input Frequency Clock Pulse Width Clock input Rise or Fall Time Set or Reset Pulse Width Data Setup Time VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Value (*) Unit Min. Typ. Max. 500 200 150 300 150 100 200 100 80 3.5 8 12 140 60 40 250 100 75 150 75 50 100 50 40 7 16 24 70 30 20 100 50 25 200 80 50 ns ns MHz ns 15 5 5 200 100 50 400 160 100 ns µs ns ns (*) Typical temperature coefficient for all VDD value is 0.3 %/°C. 5/10 HCF4096B TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200KΩ RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM : PROPAGATION DELAY TRANSITION AND SETUP TIME 6/10 HCF4096B WAVEFORM : CLOCK PULSE, RISE AND FALL TIME TYPICAL APPLICATION : D - TYPE FLIP FLOP 7/10 HCF4096B Plastic DIP-14 MECHANICAL DATA mm. inch DIM. MIN. a1 0.51 B 1.39 TYP MAX. MIN. TYP. MAX. 0.020 1.65 0.055 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 15.24 0.600 F 7.1 0.280 I 5.1 0.201 L Z 3.3 1.27 0.130 2.54 0.050 0.100 P001A 8/10 HCF4096B SO-14 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45˚ (typ.) D 8.55 E 5.8 8.75 0.336 6.2 0.228 0.344 0.244 e 1.27 0.050 e3 7.62 0.300 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.68 0.026 8 ˚ (max.) PO13G 9/10 HCF4096B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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