Surface Mount RF PIN Switch and Limiter Diodes Technical Data HSMP-382x Series and HSMP-482x Series Features • Diodes Optimized for: Low Current Switching Low Distortion Attenuating • Power Limiting /Circuit Protection • Surface Mount SOT-23 and SOT-323 Packages Single and Dual Versions Tape and Reel Options Available Package Lead Code Identification, SOT-23 (Top View) SINGLE SERIES #0 #2 COMMON ANODE COMMON CATHODE #3 #4 Package Lead Code Identification, SOT-323 (Top View) DUAL ANODE HSMP-482B • Low Failure in Time (FIT) Rate[1] Note: 1. For more information see the Surface Mount PIN Reliability Data Sheet. DUAL ANODE HSMP-4820 Description/Applications The HSMP-382x series is optimized for switching applications where ultra-low resistance is required. The HSMP-482x diode is ideal for limiting and low inductance switching applications up to 1.5 GHz. A SPICE model is not available for PIN diodes as SPICE does not provide for a key PIN diode characteristic, carrier lifetime. Absolute Maximum Ratings[1] TC = +25°C Symbol Parameter If PIV Tj Tstg θjc Forward Current (1 µs Pulse) Peak Inverse Voltage Junction Temperature Storage Temperature Thermal Resistance[2] Unit SOT-23 SOT-323 Amp V °C °C °C/W 1 50 150 -65 to 150 500 1 50 150 -65 to 150 150 Notes: 1. Operation in excess of any one of these conditions may result in permanent damage to the device. 2. TC = +25°C, where TC is defined to be the temperature at the package pins where contact is made to the circuit board. 2 Electrical Specifications TC = 25°C Part Number HSMP- Package Marking Code[1] Lead Code Configuration 3820 3822 3823 3824 F0 F2 F3 F4 0 2 3 4 Single Series Common Anode Common Cathode Test Conditions Minimum Maximum Maximum Breakdown Series Resistance Total Capacitance Voltage VBR (V) RS (Ω) CT (pF) 50 0.6 0.8 VR = VBR Measure IR ≤ 10 µA f = 100 MHz f = 1 MHz VR = 20 V IF = 10 mA High Frequency (Low Inductance, 500 MHz – 3 GHz) PIN Diodes Part Number HSMP- Package Marking Code Lead Code 4820 482B FA FA A A Configuration Dual Anode Dual Anode Test Conditions Minimum Breakdown Voltage VBR (V) Maximum Series Resistance RS (Ω) Typical Total Capacitance CT (pF) Maximum Total Capacitance CT (pF) Typical Total Inductance LT (nH) 50 0.6 0.75 1.0 1.0 VR = VBR Measure IR ≤ 10 µA IF = 10 mA f = 1 MHz VR = 20 V f = 1 MHz VR = 0 V f = 500 MHz – 3 GHz Note: 1. Package marking code is white, except for HSMP-482B, which is laser marked. Typical Parameters at TC = 25°C Part Number HSMP- Series Resistance RS (Ω) Carrier Lifetime τ (ns) Reverse Recovery Time Trr (ns) Total Capacitance CT (pF) 382x 1.5 70 7 0.60 @ 20 V f = 100 MHz IF = 10 mA IF = 10 mA VR = 10 V IF = 20 mA 90% Recovery Test Conditions 3 Typical Parameters at TC = 25°C (unless otherwise noted), Single Diode 10 1 0.1 125°C 25°C –50°C 0 0.2 0.4 0.6 0.8 1.0 1.2 100 VR = 2V VR = 5V 10 VR = 10V 1 10 0.1 0.01 0.1 1 10 100 IF – FORWARD BIAS CURRENT (mA) 30 Figure 2. Reverse Recovery Time vs. Forward Current for Various Reverse Voltages. Figure 3. RF Resistance at 25°C vs. Forward Bias Current. 120 INPUT INTERCEPT POINT (dBm) 1.4 CAPACITANCE (pF) 1 FORWARD CURRENT (mA) VF – FORWARD VOLTAGE (mA) Figure 1. Forward Current vs. Forward Voltage. 1.2 1.0 0.8 0.6 20 10 0 10 20 30 40 50 105 100 95 25 15 85 0 10 30 1.0 GHz 10 5 1 1.5 GHz 20 90 VR – REVERSE VOLTAGE (V) Figure 4. Capacitance vs. Reverse Voltage. 30 Diode Mounted as a Series Attenuator in a 115 50 Ohm Microstrip and Tested at 123 MHz 110 CW POWER OUT (dBm) 0.01 100 RF RESISTANCE (OHMS) Trr – REVERSE RECOVERY TIME (ns) IF – FORWARD CURRENT (mA) 100 Measured with external bias return 0 5 Figure 5. 2nd Harmonic Input Intercept Point vs. Forward Bias Current. 10 15 20 25 30 35 40 CW POWER IN (dBm) IF – FORWARD BIAS CURRENT (mA) Figure 6. Large Signal Transfer Curve of the HSMP-482x Limiter. Typical Applications for Multiple Diode Products RF COMMON RF COMMON RF 1 BIAS 1 RF 2 RF 1 RF 2 BIAS 2 BIAS Figure 7. Simple SPDT Switch, Using Only Positive Current. Figure 8. High Isolation SPDT Switch, Dual Bias. BIAS 4 Typical Applications for Multiple Diode Products, continued RF COMMON RF COMMON BIAS RF 1 RF 2 RF 2 RF 1 BIAS Figure 9. Switch Using Both Positive and Negative Bias Current. Figure 10. Very High Isolation SPDT Switch, Dual Bias. BIAS Figure 11. High Isolation SPST Switch (Repeat Cells as Required. Figure 12. Power Limiter Using HSMP-3822 Diode Pair. See Application Note 1050 for details. 5 Typical Applications for HSMP-482x Low Inductance Series Microstrip Series Connection for HSMP-482x Series In order to take full advantage of the low inductance of the HSMP-482x series when using them in series applications, both lead 1 and lead 2 should be connected together, as shown in Figure 14. 3 Microstrip Shunt Connections for HSMP-482x Series In Figure 15, the center conductor of the microstrip line is interrupted and leads 1 and 2 of the HSMP-482x diode are placed across the resulting gap. This forces the 0.5 nH lead inductance of leads 1 and 2 to appear as part of a low pass filter, reducing the shunt parasitic inductance and increasing the maximum available attenuation. The 0.3 nH of shunt inductance external to the diode is created by the via holes, and is a good estimate for 0.032" thick material. Co-Planar Waveguide Shunt Connection for HSMP-482x Series Co-Planar waveguide, with ground on the top side of the printed circuit board, is shown in Figure 17. Since it eliminates the need for via holes to ground, it offers lower shunt parasitic inductance and higher maximum attenuation when compared to a microstrip circuit. See AN1050 for details. Co-Planar Waveguide Groundplane Center Conductor Groundplane 50 OHM MICROSTRIP LINES 1 2 HSMP-482x Figure 13. Internal Connections. Figure 17. Circuit Layout. PAD CONNECTED TO GROUND BY TWO VIA HOLES 0.8 pF Figure 15. Circuit Layout, HSMP-482x Limiter. Figure 14. Circuit Layout. 0.75 nH 1.5 nH 1.5 nH Figure 18. Equivalent Circuit. 0.8 pF 0.3 nH 0.3 nH Figure 16. Equivalent Circuit. 6 Assembly Information SOT-323 PCB Footprint A recommended PCB pad layout for the miniature SOT-323 (SC-70) package is shown in Figure 19 (dimensions are in inches). This layout provides ample allowance for package placement by automated assembly equipment without adding parasitics that could impair the performance. 0.026 0.07 Agilent’s diodes have been qualified to the time-temperature profile shown in Figure 21. This profile is representative of an IR reflow type of surface mount assembly process. 0.035 0.016 Figure 19. PCB Pad Layout (dimensions in inches). SOT-23 PCB Footprint 0.037 0.95 0.037 0.95 SMT Assembly Reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., IR or vapor phase reflow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. Components with a low mass, such as the SOT-323/-23 package, will reach solder reflow temperatures faster than those with a greater mass. After ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. The preheat zones increase the temperature of the board and components to prevent thermal shock and begin evaporating solvents from the solder paste. The reflow zone briefly elevates the temperature sufficiently to produce a reflow of the solder. The rates of change of temperature for the ramp-up and cooldown zones are chosen to be low enough to not cause deformation of the board or damage to components due to thermal shock. The maximum temperature in the reflow zone (TMAX) should not exceed 235°C. These parameters are typical for a surface mount assembly process for Agilent diodes. As a general guideline, the circuit board and components should be exposed only to the minimum temperatures and times necessary to achieve a uniform reflow of solder. 250 TMAX 0.079 2.0 0.035 0.9 0.031 0.8 DIMENSIONS IN inches mm Figure 20. PCB Pad Layout. TEMPERATURE (°C) 200 150 Reflow Zone 100 Preheat Zone Cool Down Zone 50 0 0 60 120 180 TIME (seconds) Figure 21. Surface Mount Assembly Profile. 240 300 7 Package Dimensions Outline SOT-323 (SC-70) Outline 23 (SOT-23) PACKAGE MARKING CODE (XX) 1.30 (0.051) REF. 1.02 (0.040) 0.89 (0.035) 2.20 (0.087) 2.00 (0.079) XXX DATE CODE (X) 0.54 (0.021) 0.37 (0.015) PACKAGE MARKING CODE (XX) 1.35 (0.053) 1.15 (0.045) 3 1.40 (0.055) 1.20 (0.047) XXX 1 0.650 BSC (0.025) 0.425 (0.017) TYP. 2.20 (0.087) 1.80 (0.071) DATE CODE (X) 0.50 (0.024) 0.45 (0.018) 2.65 (0.104) 2.10 (0.083) 2 2.04 (0.080) 1.78 (0.070) TOP VIEW 0.10 (0.004) 0.00 (0.00) 0.30 REF. 0.25 (0.010) 0.15 (0.006) 1.00 (0.039) 0.80 (0.031) 10° 0.152 (0.006) 0.066 (0.003) 3.06 (0.120) 2.80 (0.110) 0.30 (0.012) 0.10 (0.004) 1.02 (0.041) 0.85 (0.033) 0.20 (0.008) 0.10 (0.004) 0.69 (0.027) 0.45 (0.018) 0.10 (0.004) 0.013 (0.0005) DIMENSIONS ARE IN MILLIMETERS (INCHES) SIDE VIEW DIMENSIONS ARE IN MILLIMETERS (INCHES) Package Characteristics Lead Material ................................... Copper (SOT-323); Alloy 42 (SOT-23) Lead Finish ............................................................................ Tin-Lead 85-15% Maximum Soldering Temperature .............................. 260°C for 5 seconds Minimum Lead Strength .......................................................... 2 pounds pull Typical Package Inductance .................................................................. 2 nH Typical Package Capacitance .............................. 0.08 pF (opposite leads) Ordering Information Specify part number followed by option. For example: HSMP - 382x - XXX Bulk or Tape and Reel Option Part Number; x = Lead Code Surface Mount PIN Option Descriptions -BLK = Bulk, 100 pcs. per antistatic bag -TR1 = Tape and Reel, 3000 devices per 7" reel -TR2 = Tape and Reel, 10,000 devices per 13" reel Tape and Reeling conforms to Electronic Industries RS-481, “Taping of Surface Mounted Components for Automated Placement.” END VIEW Device Orientation REEL TOP VIEW END VIEW 4 mm 8 mm CARRIER TAPE USER FEED DIRECTION ### ### ### ### Note: “###” represents Package Marking Code, Date Code. COVER TAPE Tape Dimensions For Outline SOT-323 (SC-70 3 Lead) P P2 D P0 E F W C D1 t1 (CARRIER TAPE THICKNESS) Tt (COVER TAPE THICKNESS) K0 8° MAX. A0 DESCRIPTION 5° MAX. B0 SYMBOL SIZE (mm) SIZE (INCHES) CAVITY LENGTH WIDTH DEPTH PITCH BOTTOM HOLE DIAMETER A0 B0 K0 P D1 2.24 ± 0.10 2.34 ± 0.10 1.22 ± 0.10 4.00 ± 0.10 1.00 + 0.25 0.088 ± 0.004 0.092 ± 0.004 0.048 ± 0.004 0.157 ± 0.004 0.039 + 0.010 PERFORATION DIAMETER PITCH POSITION D P0 E 1.55 ± 0.05 4.00 ± 0.10 1.75 ± 0.10 0.061 ± 0.002 0.157 ± 0.004 0.069 ± 0.004 CARRIER TAPE WIDTH THICKNESS W t1 8.00 ± 0.30 0.255 ± 0.013 0.315 ± 0.012 0.010 ± 0.0005 COVER TAPE WIDTH TAPE THICKNESS C Tt 5.4 ± 0.10 0.062 ± 0.001 0.205 ± 0.004 0.0025 ± 0.00004 DISTANCE CAVITY TO PERFORATION (WIDTH DIRECTION) F 3.50 ± 0.05 0.138 ± 0.002 CAVITY TO PERFORATION (LENGTH DIRECTION) P2 2.00 ± 0.05 0.079 ± 0.002 www.semiconductor.agilent.com Data subject to change. Copyright © 2001 Agilent Technologies Obsoletes 5968-8016E May 25, 2001 5988-3145EN