ETC IMST225

IMS T225
)
16-bit transputer
FEATURES
H 16 bit architecture
H 33 ns internal cycle time
H 30 MIPS peak instruction rate
H Debugging support
H 4 Kbytes on-chip static RAM
H 60 Mbytes/sec sustained data rate to internal
memory
H 64 Kbytes directly addressable external memory
H 30 Mbytes/sec sustained data rate to external
memory
System
Services
16
16 bit
Processor
H 630 ns response to interrupts
H Four INMOS serial links 5/10/20 Mbits/sec
H Bi-directional data rate of 2.4 Mbytes/sec per link
Link
services
Timers
H Internal timers of 1ms and 64ms
H Boot from ROM or communication links
H Single 5 MHz clock input
H Single +5V
4 Kbytes
of On-chip
RAM
16
Link
interface
16
Link
interface
16
Link
interface
16
Link
interface
16
5% power supply
H Packaging 68 pin PGA / 68 pin PLCC / 100 pin CQFP
H Extended temperature version available
APPLICATIONS
H Real time processing
H Microprocessor applications
External
Memory
Interface
16
Event
H High speed multi processor systems
H Industrial control
H Robotics
H System simulation
H Digital signal processing
H Telecommunications
H Fault tolerant systems
H Medical instrumentation
July 1995
42 1454 03
1/56
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
2 Pin designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
3 System services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
3.1
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
3.2
3.3
3.4
CapPlus, CapMinus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ClockIn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ProcSpeedSelect0–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
6
8
3.5
3.6
3.7
Bootstrap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peek and poke . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
9
9
3.8
3.9
Analyse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
11
4 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
5 External memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
5.1
5.2
5.3
Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processor clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
17
18
5.4
5.5
5.6
Write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MemBAcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
20
23
5.7
Direct memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
6 Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
7 Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
8 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
8.1
8.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
31
8.3
8.4
8.5
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
33
34
8.6
Power rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
9 Package details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
9.1
9.2
9.3
68 pin grid array package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68 pin PLCC J-bend package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100 pin cavity-up ceramic quad flat pack (CQFP) package . . . . . . . . . . . . . . . . . . . . . . .
36
38
40
9.4
Thermal specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
10 Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
11 Transputer instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
2 / 56
1 Introduction
1
Introduction
The IMS T225 transputer is a 16 bit CMOS microcomputer with 4 Kbytes on-chip RAM for high speed processing, an external memory interface and four standard INMOS communication links. The instruction set
achieves efficient implementation of high level languages such as ANSI C and provides direct support for
concurrency when using either a single transputer or a network. Procedure calls, process switching and
typical interrupt latency are sub-microsecond.
For convenience of description, the IMS T225 operation is split into the basic blocks shown in figure 1.1.
VDD
GND
CapPlus
CapMinus
Reset
Analyse
System
Services
16
Error
BootFromROM
ClockIn
ProcSpeedSelect0–2
16 bit
Processor
Link
Services
LinkSpecial
Link0Special
Link123Special
16
Link
Interface
LinkIn0
LinkOut0
16
Link
Interface
LinkIn1
LinkOut1
16
Link
Interface
LinkIn2
LinkOut2
16
Link
Interface
LinkIn3
LinkOut3
Event
EventReq
EventAck
Timers
DisableIntRAM
4 Kbytes
of
On-chip
RAM
16
ProcClockOut
notMemCE
notMemWrB0–1
External
Memory
Interface
MemWait
MemBAcc
MemReq
MemGranted
16
16
MemD0–15
16
MemA0–15
Figure 1.1 IMS T225 block diagram
The IMS T225 is functionally equivalent to the IMS T222 but has the addition of three speed select pins
(ProcSpeedSelect0-2) and improved links. The IMS T225 is pin compatible with the IMS T222 and is a
direct replacement in many applications. The IMS T225 can directly access a linear address space of
64 Kbytes.
System Services include processor reset and bootstrap control, together with facilities for error analysis.
The INMOS communication links allow networks of transputers to be constructed by direct point to point
connections with no external logic. The links support the standard operating speed of 10 Mbits/sec, but
3 / 56
IMS T225
also operate at 5 or 20 Mbits/sec. The links have been improved over those of the IMS T222 and fully
support overlapped acknowledge; each IMS T225 link can transfer data bi-directionally at up to
2.4 Mbytes/sec.
The transputer is designed to efficiently implement high level languages such as ANSI C and occam.
Access to the transputer at machine level is seldom required, but if necessary refer to the Transputer Instruction Set – A Compiler Writer’s Guide. A summary of the transputer instruction set can be found in
section 11.
The IMS T225 instruction set contains a number of instructions to facilitate the implementation of breakpoints. For further information concerning breakpointing, refer to Support for debugging/breakpointing in
transputers (technical note 61).
4 / 56
2 Pin designations
2
Pin designations
Signal names are prefixed by not if they are active low, otherwise they are active high.
Pinout details for various packages are given in section 9.
Pin
In/Out
Function
VCC, GND
Power supply and return
CapPlus, CapMinus
External capacitor for internal clock power supply
ClockIn
in
Input clock
ProcSpeedSelect0–2
in
Processor speed selectors
Reset
in
System reset
Error
out
Error indicator
Analyse
in
Error analysis
BootFromROM
in
Boot from external ROM or from link
DisableIntRAM
in
Disable internal RAM
Table 2.1
Pin
In/Out
IMS T225 system services
Function
ProcClockOut
out
Processor clock
MemA0–15
out
Sixteen address lines
MemD0–15
in/out
Sixteen data lines
notMemWrB0–1
out
Two byte-addressing write strobes
notMemCE
out
Chip enable
MemBAcc
in
Byte access mode selector
MemWait
in
Memory cycle extender
MemReq
in
Direct memory access request
MemGranted
out
Direct memory access granted
Table 2.2 IMS T225 external memory interface
Pin
In/Out
Function
EventReq
in
Event request
EventAck
out
Event request acknowledge
Table 2.3
Pin
In/Out
IMS T225 event
Function
LinkIn0–3
in
Four serial data input channels
LinkOut0–3
out
Four serial data output channels
LinkSpecial
in
Select non-standard speed as 5 or 20 Mbits/sec
Link0Special
in
Select special speed for Link 0
Link123Special
in
Select special speed for Links 1, 2, 3
Table 2.4
IMS T225 link
5 / 56
IMS T225
3
System services
System services include all the necessary logic to initialize and sustain operation of the device. They also
include error handling and analysis facilities.
3.1
Power
Power is supplied to the device via the VDD and GND pins. Several of each are provided to minimize inductance within the package. All supply pins must be connected. The supply must be decoupled close to the
chip by at least one 100 nF low inductance (e.g. ceramic) capacitor between VDD and GND. Four layer
boards are recommended; if two layer boards are used, extra care should be taken in decoupling.
Input voltages must not exceed specification with respect to VDD and GND, even during power-up and
power-down ramping, otherwise latchup can occur. CMOS devices can be permanently damaged by excessive periods of latchup.
3.2
CapPlus, CapMinus
The internally derived power supply for internal clocks requires an external low leakage, low inductance
1mF capacitor to be connected between CapPlus and CapMinus. A ceramic capacitor is preferred, with
an impedance less than 3 Ohms between 100 KHz and 20 MHz. If a polarized capacitor is used the negative terminal should be connected to CapMinus. Total PCB track length should be less than 50 mm. The
connections must not touch power supplies or other noise sources.
VDD
CapPlus
P.C.B track
Phase–locked
loops
Decoupling
capacitor 1 mF
CapMinus
P.C.B track
GND
Figure 3.1 Recommended PLL decoupling
3.3
ClockIn
Transputer family components use a standard clock frequency, supplied by the user on the ClockIn input.
The nominal frequency of this clock for all transputer family components is 5 MHz, regardless of device
type, transputer word length or processor cycle time. High frequency internal clocks are derived from
ClockIn, simplifying system design and avoiding problems of distributing high speed clocks externally.
A number of transputer devices may be connected to a common clock, or may have individual clocks providing each one meets the specified stability criteria. In a multi-clock system the relative phasing of ClockIn clocks is not important, due to the asynchronous nature of the links. Mark/space ratio is unimportant
provided the specified limits of ClockIn pulse widths are met.
Oscillator stability is important. ClockIn must be derived from a crystal oscillator; RC oscillators are not
sufficiently stable. ClockIn must not be distributed through a long chain of buffers. Clock edges must be
monotonic and remain within the specified voltage and time limits.
6 / 56
3 System services
T225-25
Symbol
Parameter
Min
Nom
Max
Units
TDCLDCH
ClockIn pulse width low
40
ns
TDCHDCL
ClockIn pulse width high
40
ns
TDCLDCL
ClockIn period
TDCerror
ClockIn timing error
TDC1DC2
Difference in ClockIn for 2 linked devices
TDCr
TDCf
200
Notes
ns
1,3
ns
2
400
ppm
3
ClockIn rise time
10
ns
4
ClockIn fall time
8
ns
4
0.5
Notes
1 Measured between corresponding points on consecutive falling edges.
2 Variation of individual falling edges from their nominal times.
3 This value allows the use of 200ppm crystal oscillators for two devices connected together by
a link.
4 Clock transitions must be monotonic within the range VIH to VIL (table 8.3).
Table 3.1
ClockIn timing
TDCerror
TDCerror
TDCerror
TDCerror
2.0V
1.5V
0.8V
TDCLDCH
TDCHDCH
TDCLDCL
90%
90%
10%
10%
TDCf
TDCr
Figure 3.2 ClockIn timing
7 / 56
IMS T225
3.4
ProcSpeedSelect0–2
Processor speed of the IMS T225 is variable in discrete steps. The desired speed can be selected, up to
the maximum rated for a particular component, by the three speed select lines ProcSpeedSelect0-2. The
pins are tied high or low, according to the table below, for the various speeds. The pins are arranged so
that the IMS T225 can be plugged directly into a board designed for a IMS T222.
Only six of the possible speed select combinations are currently used; the other two are not valid speed
selectors. The frequency of ClockIn for the speeds given in the table is 5 MHz.
ProcSpeedSelect2
ProcSpeedSelect1
ProcSpeedSelect0
Processor
Clock
Speed MHz
Processor
Cycle
Time ns
0
0
0
20.0
50.0
0
0
1
22.5
44.4
0
1
0
25.0
40.0
0
1
1
30.0
33.3
Not supported
1
0
0
35.0
28.6
Not supported
1
0
1
1
1
0
1
1
1
Table 3.2
3.5
Notes
Not supported
Invalid
17.5
57.1
Not supported
Invalid
Processor speed selection
Bootstrap
The transputer can be bootstrapped either from a link or from external ROM. Tofacilitate debugging, BootFromROM may be dynamically changed but must obey the specified timing restrictions. It is sampled once
only by the transputer, before the first instruction is executed after Reset is taken low.
If BootFromROM is connected high (e.g. to VDD) the transputer starts to execute code from the top two
bytes in external memory, at address #7FFE. This location should contain a backward jump to a program
in ROM. Following this access, BootFromROM may be taken low if required. The processor is in the low
priority state, and the W register points to MemStart (page 11).
If BootFromROM is connected low (e.g. to GND) the transputer will wait for the first bootstrap message
to arrive on any one of its links. The transputer is ready to receive the first byte on a link within two processor
cycles TPCLPCL after Reset goes low.
If the first byte received (the control byte) is greater than 1 it is taken as the quantity of bytes to be input.
The following bytes, to that quantity, are then placed in internal memory starting at location MemStart. Following reception of the last byte the transputer will start executing code at MemStart as a low priority process. BootFromROM may be taken high after reception of the last byte, if required. The memory space
immediately above the loaded code is used as work space. A byte arriving on other links after the control
byte has been received and on the bootstrapping link after the last bootstrap byte, will be retained and no
acknowledge will be sent until a process inputs from them.
8 / 56
3 System services
3.6
Peek and poke
Any location in internal or external memory can be interrogated and altered when the transputer is waiting
for a bootstrap from link. If the control byte is 0 then four more bytes are expected on the same link. The
first two byte word is taken as an internal or external memory address at which to poke (write) the second
two byte word. If the control byte is 1 the next two bytes are used as the address from which to peek (read)
a word of data; the word is sent down the output channel of the same link.
Following such a peek or poke, the transputer returns to its previously held state. Any number of accesses
may be made in this way until the control byte is greater than 1, when the transputer will commence reading its bootstrap program. Any link can be used, but addresses and data must be transmitted via the same
link as the control byte.
3.7
Reset
Reset can go high with VDD, but must at no time exceed the maximum specified voltage for VIH. After
VDD is valid ClockIn should be running for a minimum period TDCVRL before the end of Reset. The falling
edge of Reset initializes the transputer and starts the bootstrap routine. Link outputs are forced low during
reset; link inputs and EventReq should be held low. Memory request (DMA) must not occur whilst Reset
is high but can occur before bootstrap (page 23). If BootFromROM is high bootstrapping will take place
immediately after Reset goes low, using data from external memory; otherwise the transputer will await
an input from any link. The processor will be in the low priority state.
3.8
Analyse
If Analyse is taken high when the transputer is running, the transputer will halt at the next descheduling
point (page 46). From Analyse being asserted, the processor will halt within three time slice periods plus
the time taken for any high priority process to complete. As much of the transputer status is maintained
as is necessary to permit analysis of the halted machine. Processor flags Error and HaltOnError are not
altered at reset, whether Analyse is asserted or not.
Input links will continue with outstanding transfers. Output links will not make another access to memory
for data but will transmit only those bytes already in the link buffer. Providing there is no delay in link acknowledgement, the links should be inactive within a few microseconds of the transputer halting.
Reset should not be asserted before the transputer has halted and link transfers have ceased. If BootFromROM is high the transputer will bootstrap as soon as Analyse is taken low, otherwise it will await
a control byte on any link. If Analyse is taken low without Reset going high the transputer state and operation are undefined. After the end of a valid Analyse sequence the registers have the values given in
table 3.3.
I
MemStart if bootstrapping from a link, or the external memory bootstrap address if bootstrapping
from ROM.
W
MemStart if bootstrapping from ROM, or the address of the first free word after the bootstrap
program if bootstrapping from link.
A
The value of I when the processor halted.
B
The value of W when the processor halted, together with the priority of the process when the
transputer was halted (i.e. the W descriptor).
C
The ID of the bootstrapping link if bootstrapping from link.
Table 3.3
Register values after Analyse
9 / 56
IMS T225
T225-25
Symbol
Parameter
Min
TPVRH
Power valid before Reset
10
ms
TRHRL
Reset pulse width high
8
ClockIn
1
TDCVRL
ClockIn running before Reset end
10
ms
2
TAHRH
Analyse setup before Reset
3
ms
TRLAL
Analyse hold after Reset end
1
ClockIn
TBRVRL
BootFromROM setup
0
ms
TRLBRX
BootFromROM hold after Reset
50
ms
3
TALBRX
BootFromROM hold after Analyse
50
ms
3
Nom
Max
Units
Notes
1 Full periods of ClockIn TDCLDCL required.
2 At power-on reset.
3 Must be stable until after end of bootstrap period. See Bootstrap section 3.5.
Table 3.4 Reset , Analyse and BootFromROM timing
ClockIn
TDCVRL
VDD
TPVRH
TRHRL
Reset
TBRVRL
TRLBRX
BootFromROM
Figure 3.3 Transputer Reset timing with Analyse low
TRHRL
Reset
TRLAL
TAHRH
Analyse
TBRVRL
TALBRX
BootFromROM
Figure 3.4 Transputer Reset, Analyse and BootFromROM timing
10 / 56
Notes
1
3 System services
3.9
Error
The Error pin is connected directly to the internal Error flag and follows the state of that flag. If Error is
high it indicates an error in one of the processes caused, for example, by arithmetic overflow, divide by
zero, array bounds violation or software setting the flag directly (page 46). Once set, the Error flag is only
cleared by executing the instruction testerr. The error is not cleared by processor reset, in order that analysis can identify any errant transputer (page 8).
A process can be programmed to stop if the Error flag is set; it cannot then transmit erroneous data to other
processes, but processes which do not require that data can still be scheduled. Eventually all processes
which rely, directly or indirectly, on data from the process in error will stop through lack of data.
By setting the HaltOnError flag the transputer itself can be programmed to halt if Error becomes set. If Error
becomes set after HaltOnError has been set, all processes on that transputer will cease but will not necessarily cause other transputers in a network to halt. Setting HaltOnError after Error will not cause the transputer to halt; this allows the processor reset and analyse facilities to function with the flags in indeterminate
states.
An alternative method of error handling is to have the errant process or transputer cause all transputers
to halt. This can be done by applying the Error output signal of the errant transputer to the EventReq pin
of a suitably programmed master transputer. Since the process state is preserved when stopped by an
error, the master transputer can then use the analyse function to debug the fault. When using such a circuit,
note that the Error flag is in an indeterminate state on power up; the circuit and software should be designed with this in mind.
Error checks can be removed completely to optimize the performance of a proven program; any unexpected error then occurring will have an arbitrary undefined effect.
If a high priority process pre-empts a low priority one, status of the Error and HaltOnError flags is saved
for the duration of the high priority process and restored at the conclusion of it. Status of the Error flag is
transmitted to the high priority process but the HaltOnError flag is cleared before the process starts. Either
flag can be altered in the process without upsetting the error status of any complex operation being carried
out by the pre-empted low priority process.
In the event of a transputer halting because of HaltOnError, the links will finish outstanding transfers before
shutting down. If Analyse is asserted then all inputs continue but outputs will not make another access
to memory for data.
After halting due to the Error flag changing from 0 to 1 whilst HaltOnError is set, register I points two bytes
past the instruction which set Error. After halting due to the Analyse pin being taken high, register I points
one byte past the instruction being executed. In both cases I will be copied to register A.
Analyse
Master
Transputer
Latch
Reset
Slave
Transputer
0
Slave
Transputer
1
Error[0]
Error[1]
Event
(transputer links not shown)
Slave
Transputer
2
Slave
Transputer
3
Error[2]
Error[3]
Figure 3.5 Error handling in a multi-transputer system
11 / 56
IMS T225
4
Memory
The IMS T225 has 4 Kbytes of fast internal static memory for high rates of data throughput. Each internal
memory access takes one processor cycle ProcClockOut. The transputer can also access an additional
60 Kbytes of external memory space. Internal and external memory are part of the same linear address
space. Internal RAM can be disabled by holding DisableIntRAM high. All internal addresses are then
mapped to external RAM. This pin should not be altered after Reset has been taken low.
IMS T225 memory is byte addressed, with words aligned on two-byte boundaries. The least significant
byte of a word is the lowest addressed byte.
The bits in a byte are numbered 0 to 7, with bit 0 the least significant. The bytes are numbered from 0, with
byte 0 the least significant. In general, wherever a value is treated as a number of component values, the
components are numbered in order of increasing numerical significance, with the least significant component numbered 0. Where values are stored in memory, the least significant component value is stored at
the lowest (most negative) address.
Internal memory starts at the most negative address #8000 and extends to #8FFF. User memory begins
at #8024; this location is given the name MemStart. An instruction ldmemstartval is provided to obtain the
value of MemStart.
The context of a process in the transputer model involves a workspace descriptor (WPtr) and an instruction pointer (IPtr). WPtr is a word address pointer to a workspace in memory. IPtr points to the next instruction to be executed for the process which is the currently executing process. The context switch performed
by the breakpoint instruction swaps the WPtr and IPtr of the currently executing process with the WPtr
and IPtr held above MemStart. Two contexts are held above MemStart, one for high priority and one for
low priority; this allows processes at both levels to have breakpoints. Note that on bootstrapping from a
link, these contexts are overwritten by the loaded code. If this is not acceptable, the values should be
peeked from memory before bootstrapping from a link.
The reserved area of internal memory below MemStart is used to implement link and event channels.
Two words of memory are reserved for timer use, TPtrLoc0 for high priority processes and TPtrLoc1 for
low priority processes. They either indicate the relevant priority timer is not in use or point to the first process on the timer queue at that priority level.
Values of certain processor registers for the current low priority process are saved in the reserved IntSaveLoc locations when a high priority process pre-empts a low priority one.
External memory space starts at #9000 and extends up through #0000 to #7FFF. ROM bootstrapping code
must be in the most positive address space, starting at #7FFE. Address space immediately below this is
conventionally used for ROM based code.
12 / 56
4 Memory
hi
Machine map
Reset inst
lo Byte address
Word offsets
occam map
#7FFE
#0
#9000 — Start of external memory —#0800
#8024 MemStart
MemStart #12
ERegIntSaveLoc
#8022
STATUSIntSaveLoc
#8020
CRegIntSaveLoc
#801E
BRegIntSaveLoc
#801C
ARegIntSaveLoc
#801A
IptrIntSaveLoc
#8018
WdescIntSaveLoc
#8016
TPtrLoc1
#8014
TPtrLoc0
#8012
Event
#8010
#08
Event
Link 3 Input
#800E
#07
Link 3 Input
Link 2 Input
#800C
#06
Link 2 Input
Link 1 Input
#800A
#05
Link 1 Input
Link 0 Input
#8008
#04
Link 0 Input
Link 3 Output
#8006
#03
Link 3 Output
Link 2 Output
#8004
#02
Link 2 Output
Link 1 Output
#8002
#01
Link 1 Output
Link 0 Output
#8000
#00
Link 0 Output
Note 1
(Base of memory)
Notes
1 These locations are used as auxiliary processor registers and should not be manipulated by the
user. Like processor registers, their contents may be useful for implementing debugging tools
(Analyse, page 8). For details see the Transputer Instruction Set – A Compiler Writers’ Guide.
Figure 4.1 IMS T225 memory map
13 / 56
IMS T225
5
External memory interface
The IMS T225 External Memory Interface (EMI) can access a 64 Kbyte physical address space, and provides a sustained bandwidth of 30 Mbytes/sec. It accesses a 16 bit wide address space via separate address and data buses. The data bus can be configured for either 16 bit or 8 bit memory access, allowing
the use of a single bank of byte-wide memory. Both word-wide and byte-wide access may be mixed in a
single memory system (see section 5.5).
The timing parameters given in this chapter are based on tests on a limited number of samples and may
change when full characterization is completed.
The external memory cycle is divided into four Tstates with the following functions:
T1
Address and control setup time.
T2
Data setup time.
T3
Data read/write.
T4
Data and address hold after access.
Each Tstate is half a processor cycle TPCLPCL long (see section 5.2). An external memory cycle is always a complete number of cycles TPCLPCL in length and the start of T1 always coincides with a rising
edge of ProcClockOut. T2 can be extended indefinitely by adding externally generated wait states of one
complete processor cycle each.
During an internal memory access cycle the external memory interface address bus MemA0-15 reflects
the word address used to access internal RAM, notMemWrB0-1 and notMemCE are inactive and the
data bus MemD0-15 is tristated. This is true unless and until a DMA (memory request) activity takes place,
when the lines will be placed in a high impedance state by the transputer.
Bus activity is not adequate to trace the internal operation of the transputer in full, but may be used for
hardware debugging in conjunction with peek and poke (page 8).
ProcClockOut
notMemWrB0–1
Write
Read
Read
notMemCE
MemA0–15
Address
Address
Address
MemD0–15
Figure 5.1 IMS T225 bus activity for 3 internal memory cycles
14 / 56
5 External memory interface
Figure 5.2 below shows an example of an IMS T225 being used in a static RAM application.
CapPlus
CapMinus
ClockIn
(5MHz)
VDD
GND
Link0In
Error
100K
GND
notMemCE
notMemWrB1
notMemWrB0
Link0Out
56R
IMS
Link1In
As Link0 T225
Link1Out
MemD12–15
MemD8–11
Link2In
Link2Out
56R
Link3In
As Link2
Link3Out
Reset
Analyse
MemWait
MemReq
MemD4–7
MemD0–3
16K 4
Static
16K 4 RAM
Static
RAM
16K 4
Static
16K 4
RAM
Static
RAM
MemGranted
MemA0–15
Figure 5.2 IMS T225 static RAM application
5.1
Pin functions
5.1.1
MemA0–15
External memory addresses are output on a non-multiplexed 16 bit address bus (MemA0–15). The address is valid at the start of T1 and remains so until the end of T4. Byte addressing is carried out internally
by the IMS T225 for read cycles. For write cycles the relevant bytes in memory are addressed by the write
enables notMemWrB0-1.
5.1.2
MemD0–15
The non-multiplexed data bus (MemD0–15) is 16 bits wide. Read cycle data may be set up on the bus
at any time after the start of T1, but must be valid when the IMS T225 reads it during T4. Data can be removed any time after the rising edge of notMemCE, but must be off the bus no later than the middle of
T1, which allows for bus turn-around time before the data lines are driven at the start of T2 in a processor
write cycle. Write data is placed on the bus at the start of T2 and removed at the end of T4. The writing
of data into memory is normally synchronized to notMemCE going high.
The data bus is high impedance except when the transputer is writing data. If only one byte is being written,
the unused 8 bits of the bus are high impedance at that time.
15 / 56
IMS T225
5.1.3
notMemWrB0–1
Twowrite enables are provided, one to write each byte of the word. When writing a word, both write enables
are asserted; when writing a byte only the appropriate write enable is asserted. notMemWrB0 addresses
the least significant byte.
The write enables are synchronized with the chip enable signal notMemCE, allowing them to be used without notMemCE for simple designs.
Data may be strobed into memory using notMemWrB0-1 without the use of notMemCE, as the write enables go high between consecutive external memory write cycles. The write enables are placed in a high
impedance state during DMA, and are inactive during internal memory access.
5.1.4
notMemCE
The active low signal notMemCE is used to enable external memory on both read and write cycles.
5.1.5
MemBAcc
The IMS T225 performs word access at even memory locations. Access to byte-wide memory can be
achieved by taking MemBAcc high. Where all external memory operations are to byte-wide memory,
MemBAcc may be wired permanently high. The state of this signal is latched during T2.
If MemBAcc is low then a full word will be accessed in one external memory cycle, otherwise the high and
low bytes of the word will be separately accessed during two consecutive cycles. The first (least significant)
byte is accessed at the word address (MemA0 is low). The second (most significant) byte is accessed at
the word address +1 (MemA0 is high).
5.1.6
MemWait
If the data setup time for read or write is too short it can be extended by inserting wait states at the end
of T2 (see section 5.6). Waitstates can be selected by taking MemWait high. MemWait is sampled during
T2, and should not change state in this region.
Internal memory access is unaffected by the number of wait states selected.
5.1.7
MemReq, MemGranted
Direct memory access (DMA) can be requested at any time by taking the asynchronous MemReq input
high. MemGranted can be used to signal to the device requesting the DMA that it has control of the bus.
For external memory cycles, the IMS T225 samples MemReq during the first high phase of ProcClockOut
after notMemCE goes low. In the absence of an external memory cycle, MemReq is sampled during every
rising edge of ProcClockOut. MemA0-15, MemD0-15, notMemWrB0-1 and notMemCE are tristated before MemGranted is asserted.
5.1.8
ProcClockOut
This clock is derived from the internal processor clock, which is in turn derived from ClockIn (see section 5.2).
16 / 56
5 External memory interface
5.2
Processor clock
This clock is derived from the internal processor clock, which is in turn derived from ClockIn. Its period
is equal to one internal microcode cycle time, and can be derived from the formula
TPCLPCL = TDCLDCL / PLLx
where TPCLPCL is the ProcClockOut Period, TDCLDCL is the ClockIn Period and PLLx is the phase
lock loop factor for the relevant speed part, obtained from the ordering details (refer to section 10).
Edges of the various external memory strobes are synchronized by, but do not all coincide with, rising or
falling edges of ProcClockOut.
T225-25
Symbol
Parameter
TPCLPCL
Min
Max
ProcClockOut period
38
42
ns
TPCHPCL
ProcClockOut pulse width high
14
26
ns
TPCLPCH
ProcClockOut pulse width low
TPCstab
ProcClockOut stability
a
8
Units Notes
ns
2,3
%
1
Notes
1 Stability is the variation of cycle periods between two consecutive cycles, measured at corresponding points on the cycles.
2 a is TPCLPCL – TPCHPCL.
3 This is a nominal value.
Table 5.1
ProcClockOut
1.5V
TPCLPCH
TPCHPCL
TPCLPCL
Figure 5.3 IMS T225 ProcClockOut timing
17 / 56
IMS T225
5.3
Read cycles
External memory addresses are output on the non-multiplexed 16 bit address bus (MemA0–15). The address is valid at the start of T1 and remains so until the end of T4, with the timing shown in figure 5.4. Byte
addressing is carried out internally by the IMS T225 for read cycles.
The non-multiplexed data bus (MemD0–15) is 16 bits wide. Read cycle data may be set up on the data
bus at any time after the start of T1, but must be valid when the IMS T225 reads it during T4. Data can
be removed any time after the rising edge of notMemCE, but must be off the bus no later than the middle
of T1, which allows for bus turn-around time before the data lines are driven at the start of T2 in a processor
write cycle.
Symbol
Parameter
TAVEL
TELEH
TEHEL
TEHAX
TELDrV
TAVDrV
TDrVEH
TEHDrZ
TWEHEL
TPCHEL
TEHPCH
Address valid before chip enable low
Chip enable low
Delay before chip enable re-assertion
Address hold after chip enable high
Data valid from chip enable low
Data valid from address valid
Data setup before chip enable high
Data hold after chip enable high
Write enable setup before chip enable low
ProcClockOut high to chip enable low
Chip enable high to ProcClockOut high
T225-25
Min
Max
6
54
66
15
1
0
40
0
53
17
0
16
4
17
5
Units Notes
ns
1
ns
1
ns
1, 2
ns
1
ns
ns
ns
ns
ns
3
ns
1
ns
Notes
1 This parameter is common to read and write cycles and to byte-wide memory accesses.
2 These values assume back-to-back external memory accesses.
3 Timing is for both write strobes notMemWrB0-1.
Table 5.2
Tstate
T1
Read
T2
T3
T4
T1
ProcClockOut
TPCHEL
TEHPCH
MemA0–15
TEHAX
TAVEL
TELEH
TEHEL
notMemCE
TAVDrV
TDrVEH
TELDrV
MemD0–15
TWEHEL
notMemWrB0–1
Figure 5.4 IMS T225 external read cycle
18 / 56
TEHDrZ
5 External memory interface
5.4
Write cycles
For write cycles the relevant bytes in memory are addressed by the write strobes notMemWrB0-1.
Write data is placed on the data bus (MemD0–15) at the start of T2 and removed at the end of T4. It is
normally written into memory in synchronism with notMemCE going high.
Two write strobes are provided, one to write each byte of the word. When writing a word, both write strobes
are asserted; when writing a byte only the appropriate write enable is asserted. notMemWrB0 addresses
the least significant byte.
The IMS T225 will, by default, perform word access at even memory locations, this is termed word access
mode. Access to byte-wide memory can be achieved by taking the MemBAcc signal high, this is termed
byte access mode (see section 5.5.2). In word access mode a full word will be accessed in one external
memory cycle, in byte access mode the high and low bytes of the word will be separately accessed during
two consecutive cycles. Both word-wide and byte-wide access may be mixed in a single memory system.
Figure 5.6 shows a write access of the least significant byte of the word when in word access mode (MemBAcc low). MemA0 is low to signify access of the least significant byte of the word at the word address.
Data may be strobed into memory using notMemWrB0-1 without the use of notMemCE, as the write
strobes go high between consecutive external memory write cycles. The write strobes are placed in a high
impedance state during DMA, and are inactive during internal memory access.
T225-25
Symbol
Parameter
Min
Max
Units Notes
TDwVEH Data setup before chip enable high
40
TEHDwZ
Data hold after write
3
TDwZEL
Write data invalid to next chip enable
1
TWELEL
Write enable setup before chip enable low
–3
3
ns
1
–3
3
ns
1
TEHWEH Write enable hold after chip enable high
ns
20
ns
ns
Notes
1 Timing is for both write strobes notMemWrB0-1.
Table 5.3
Tstate
T1
Write
T2
T3
T4
T1
ProcClockOut
MemA0–15
notMemCE
TDwZEL
TEHDwZ
TDwVEH
MemD0–15
TWELEL
TEHWEH
notMemWrB0–1
Figure 5.5 IMS T225 external write cycle
19 / 56
IMS T225
Tstate
T1
T2
T3
T4
T1
T2
ProcClockOut
MemA1–15
Address
MemA0
notMemCE
MemD0–7
Least significant byte
MemD8–15
notMemWrB0
notMemWrB1
Figure 5.6 IMS T225 least significant byte write in word access mode
5.5
MemBAcc
The IMS T225 will, by default, perform word access at even memory locations. Access to byte-wide
memory can be achieved by taking MemBAcc high with the timing shown. Where all external memory
operations are to byte-wide memory, MemBAcc may be wired permanently high. The state of this signal
is latched during T2. Where external memory operations may be to both byte and word wide memory,
MemBAcc should be obtained by address decoding. If you use a memory system in which word wide
memory may be used in byte access mode it is recommended that notMemWrB1 is OR gated with
MemA0, to prevent any spurious data being written to the RAM.
If MemBAcc is low then a full word will be accessed in one external memory cycle, otherwise the high and
low bytes of the word will be separately accessed during two consecutive cycles. The first (least significant)
byte is accessed at the word address (MemA0 is low). The second (most significant) byte is accessed at
the word address +1 (MemA0 is high).
5.5.1
Word Read/Write in Byte Access Mode
With MemBAcc high, the first cycle is identical with a normal word access cycle. However, it will be immediately followed by another memory cycle, which will use MemD0-7 to read or write the second (most significant) byte of data. During this second cycle, for a write, notMemWrB0–1 both go low as in the first cycle
and MemA0 goes high. For a read, notMemWrB0–1 remain high and MemA0 goes high. MemD8–15 are
high impedance for both read and write in the second cycle. Figure 5.7 shows a word write to byte-wide
memory.
20 / 56
5 External memory interface
Tstate
T1
T2
T3
T4
T1
T2
T3
T4
T1
ProcClockOut
MemA1–15
MemA0
Least significant byte
MemD0–7
Most significant byte
Most significant byte
MemD8–15
notMemCE
TEHWEH
TWELEL
TWELEL
notMemWrB0
TWELEL
notMemWrB1
MemBAcc
TELBAH
TELBAL
Figure 5.7 IMS T225 word write to byte-wide memory
5.5.2
Byte Write in Byte Access Mode
Writing a Most Significant Byte
In the first cycle notMemWrB1 will go low and notMemWrB0 will remain high. MemA0 remains low. In
the second cycle MemA0 goes high and notMemWrB0–1 go low.The data is written on MemD0–7 in the
second cycle.
Figure 5.8 shows a write access of the most significant byte of the word when in byte access mode (MemBAcc high). During the first access a normal word access is performed with notMemWrB1 active low to
select the most significant byte. During the second cycle, MemD0-7 writes the most significant byte accessed at word address + 1 (MemA0 is high).
Writing a Least Significant Byte
In the first cycle notMemWrB1 remains high and notMemWrB0 goes low. MemA0 remains low. In the
second cycle MemA0 and notMemWrB0 go high, notMemWrB1 remains high. Data is written on
MemD0–7 in the first cycle.
T225-25
Symbol
Parameter
Min
TELBAH MemBAcc high from chip enable
TELBAL
MemBAcc low from chip enable
Table 5.4
27
Max
Units
10
ns
Notes
ns
Byte-wide memory access
21 / 56
IMS T225
Tstate
T1
T2
T3
T4
T1
T2
T3
T4
ProcClockOut
MemA1–15
MemA0
Most significant byte
MemD0–7
Most significant byte
MemD8–15
notMemCE
TEHWEH
TWELEL
TWELEL
notMemWrB0
TWELEL
notMemWrB1
MemBAcc
TELBAH
TELBAL
Figure 5.8 IMS T225 most significant byte write to byte-wide memory
22 / 56
T1
5 External memory interface
5.6
Wait
Wait states can be selected by taking MemWait high. MemWait is sampled during T2, and should not
change state in this region.
A wait state is one processor cycle TPCLPCL long and comprises the pair W1 and W2, each half a processor cycle long (see figure 5.9). If MemWait is still high when sampled in W2 then another wait period will
be inserted. This can continue indefinitely. Internal memory access is unaffected by the number of wait
states selected.
The setup and hold timing requirements for MemWait are the same as for a normal word read/write cycle.
Each wait state inserted extends the length of MemA0-15, MemD0-7, notMemCE, and notMemWrB0
by one ProcClockOut cycle (TPCLPCL).
If wait states are required to extend a byte access cycle, then the time in the cycle at which MemBAcc
needs to be asserted is delayed (relative to the falling edge of notMemCE) by one TPCLPCL for each wait
state inserted (see figure 7.9). MemWait also needs to be re-asserted for the second byte accessed
(MemA0 is high), to extend this cycle. The timing requirements of the second assertion of wait are identical
to the first except that the timing is relative to the equivalent rising edge of ProcClockOut in the second
byte access. Note that the number of wait states inserted in the even and odd byte accesses can be
different.
T225-25
Symbol
Parameter
Min
TPCHWtH MemWait asserted after ProcClockOut high
TPCHWtL
Max
20
MemWait low after ProcClockOut high
40
Units Notes
ns
ns
Table 5.5 Memory wait
Tstate
T1
T2
W1
W2
T3
T4
T1
T2
W1
W2
T3
T4
ProcClockOut
Address
MemA1–15
MemA0
notMemCE
notMemWrB0
TPCHWtL
MemWait
TPCHWtH
MemBAcc
TELBAH+TPCLPCL
MemD0–15
TELBAL+TPCLPCL
Least significant byte
Most significant byte
Figure 5.9 IMS T225 word write to byte wide memory with a single wait state
23 / 56
IMS T225
The wait state generator can be a simple digital delay line, synchronized to notMemCE. The Single Wait
State Generator circuit in figure 5.10 can be extended to provide two or more wait states, as shown in
figure 5.11.
VDD
1/2 74F74
S
R
D
CP
notMemCE
ProcClockOut
Figure 5.10
MemWait
Q
Single wait state generator
VDD
notMemCE
1/6 74F04
GND
S
R
D
CP
Q
1/2 74F74
S
R
D
CP
Q
MemWait
1/2 74F74
ProcClockOut
Figure 5.11 Extendable wait state generator
5.7
Direct memory access
Direct memory access (DMA) can be requested at any time by taking the asynchronous MemReq input
high. For external memory cycles, the IMS T225 samples MemReq during the first high phase of
ProcClockOut after notMemCE goes low. In the absence of an external memory cycle, MemReq is
sampled during every rising edge of ProcClockOut. MemA0-15, MemD0-15, notMemWrB0-1 and
notMemCE are tristated before MemGranted is asserted.
Removal of MemReq is sampled at each rising edge of ProcClockOut and MemGranted removed with
the timing shown in figure 5.14. Further external bus activity,either external cycles or reflection of internal
cycles, will commence during the next low phase of ProcClockOut.
notMemCE, notMemWrB0-1, MemA0-15 and MemD0-15 are in a high impedance state during DMA.
External circuitry must ensure that notMemCE and notMemWrB0-1 do not become active whilst control
is being transferred; it is recommended that a 10K resistor is connected from VDD to each pin. DMA cannot
interrupt an external memory cycle. DMA does not interfere with internal memory cycles in any way, although a program running in internal memory would have to wait for the end of DMA before accessing
external memory. DMA cannot access internal memory.
24 / 56
5 External memory interface
DMA allows a bootstrap program to be loaded into external RAM ready for execution after reset. If MemReq is held high throughout reset, MemGranted will be asserted before the bootstrap sequence begins.
MemReq must be high at least one period TDCLDCL of ClockIn before Reset. The circuit should be designed to ensure correct operation if Reset could interrupt a normal DMA cycle.
MemReq
MemGranted
Reset
Bootstrap
activity
B
B
Bootstrap sequence
Figure 5.12
IMS T225 DMA sequence at reset
MemReq
Internal memory cycles
External memory
interface activity
T1 T2 T3 T4
EMI cycle
T1 T2 W1W2 T3 T4
EMI cycle with wait
MemGranted
notMemWrB0–1
notMemCE
MemA0–15
MemD0–15
Figure 5.13 IMS T225 operation of MemReq and MemGranted
with external and internal memory cycles
25 / 56
IMS T225
Symbol
Parameter
TMRHMGH
TMRLMGL
TAZMGH
TAVMGL
TDZMGH
TEZMGH
TEVMGL
TWEZMGH
TWEVMGL
Memory request response time
Memory request end response time
Address bus tristate before MemGranted
Address bus active after MemGranted end
Data bus tristate before MemGranted
Chip enable tristate before MemGranted
Chip enable active after MemGranted end
Write enable tristate before MemGranted
Write enable active after MemGranted end
T225–25
Min
Max
60
a
65
125
0
0
0
0
–6
0
–6
Units Notes
ns
1
ns
ns
ns
ns
ns
2
ns
ns
2
ns
Notes
1 Maximum response time a depends on whether an external memory cycle is in progress and
whether byte access is active. Maximum time is (2 processor cycles) + (number of wait state
cycles) for word access; in byte access mode this time is doubled.
2 When using DMA, notMemCE and notMemWrB0-1 should be pulled up with a resistor (typically
10K). Capacitance should be limited to a maximum of 50pF.
Table 5.6
Tstate
T1
T2
T3
Memory request timing
T4
T1
ProcClockOut
MemReq
TMRHMGH
TMRLMGL
MemGranted
TAZMGH
TAVMGL
MemA0–15
TDZMGH
MemD0–15
TEZMGH
TEVMGL
notMemCE
TWEZMGH
notMemWrB0–1
Figure 5.14
26 / 56
IMS T225 memory request timing
TWEVMGL
6 Events
6
Events
EventReq and EventAck provide an asynchronous handshake interface between an external event and
an internal process. When an external event takes EventReq high the external event channel (additional
to the external link channels) is made ready to communicate with a process. When both the event channel
and the process are ready the processor takes EventAck high and the process, if waiting, is scheduled.
EventAck is removed after EventReq goes low.
Only one process may use the event channel at any given time. If no process requires an event to occur
EventAck will never be taken high. Although EventReq triggers the channel on a transition from low to
high, it must not be removed before EventAck is high. EventReq should be low during Reset; if not it will
be ignored until it has gone low and returned high. EventAck is taken low when Reset occurs.
If the process is a high priority one and no other high priority process is running, typical latency is 19 full
processor cycles TCPLCPL, and maximum latency (assuming all memory accesses are internal) is 53
full processor cycles. Setting a high priority task to wait for an event input allows the user to interrupt a
transputer program running at low priority. The time taken from asserting EventReq to the execution of
the microcode interrupt handler in the CPU is four cycles. The following functions take place during the
four cycles:
Cycle 1 Sample EventReq at pad on the rising edge of ProcClockOut and synchronize.
Cycle 2 Edge detect the synchronized EventReq and form the interrupt request.
Cycle 3 Sample interrupt vector for microcode ROM in the CPU.
Cycle 4 Execute the interrupt routine for Event rather than the next instruction.
T225-25
Symbol
Parameter
TVHKH
EventReq response
0
ns
TKHVL
EventReq hold
0
ns
TVLKL
Delay before removal of EventAck
0
TKLVH
Delay before re-assertion of EventReq
0
Min
Table 6.1
Max
127
Units
ns
ns
Event
EventReq
TVHKH
TKHVL
TVLKL
TKLVH
EventAck
Figure 6.1 IMS T225 event timing
27 / 56
IMS T225
7
Links
Four identical INMOS bi-directional serial links provide synchronised communication between processors
and with the outside world. Each link comprises an input channel and output channel. A link between two
transputers is implemented by connecting a link interface on one transputer to a link interface on the other
transputer.Every byte of data sent on a link is acknowledged on the input of the same link, thus each signal
line carries both data and control information.
The quiescent state of a link output is low. Each data byte is transmitted as a high start bit followed by a
one bit followed by eight data bits followed by a low stop bit. The least significant bit of data is transmitted
first. After transmitting a data byte the sender waits for the acknowledge, which consists of a high start bit
followed by a zero bit. The acknowledge signifies both that a process was able to receive the acknowledged data byte and that the receiving link is able to receive another byte. The sending link reschedules
the sending process only after the acknowledge for the final byte of the message has been received.
The IMS T225 links support the standard INMOS communication speed of 10 Mbits/sec. In addition they
can be used at 5 or 20 Mbits/sec for 25 MHz devices, and 20 Mbits/sec for faster devices. Links are not
synchronised with ClockIn or ProcClockOut and are insensitive to their phases. Thus links from independently clocked systems may communicate, providing only that the clocks are nominally identical and within
specification.
Links are TTL compatible and intended to be used in electrically quiet environments, between devices on
a single printed circuit board or between two boards via a backplane. Direct connection may be made between devices separated by a distance of less than 300 millimetres. For longer distances a matched
100 ohm transmission line should be used with series matching resistors RM. When this is done the line
delay should be less than 0.4 bit time to ensure that the reflection returns before the next data bit is sent.
Buffers may be used for very long transmissions. If so, their overall propagation delay should be stable
within the skew tolerance of the link, although the absolute value of the delay is immaterial.
Link speeds can be set by LinkSpecial, Link0Special and Link123Special. The link 0 speed can be set
independently. Table 7.1 shows uni-directional and bi-directional data rates in Kbytes/sec for each link
speed; LinknSpecial is to be read as Link0Special when selecting link 0 speed and as Link123Special
for the others. Data rates are quoted for a transputer using internal memory, and will be affected by a factor
depending on the number of external memory accesses and the length of the external memory cycle.
Link
Linkn
Special
Special
Mbits/sec
Uni
Bi
0
0
10
910
1250
0
1
5
450
670
1
0
10
910
1250
1
1
20
1740
2350
Table 7.1
28 / 56
Kbytes/sec
Speed settings for transputer links
7 Links
H
H
0
1
2
3
4
5
6
7
L
H
L
Ack
Data
Figure 7.1 IMS T225 link data and acknowledge packets
Symbol
TJQr
TJQf
TJDr
TJDf
TJQJD
TJBskew
Parameter
LinkOut rise time
LinkOut fall time
LinkIn rise time
LinkIn fall time
Buffered edge delay
Variation in TJQJD
Min
CLIZ
CLL
RM
LinkIn capacitance
LinkOut load capacitance
Series resistor for 100W transmission line
Nom
Max
20
10
20
20
0
20 Mbits/s
10 Mbits/s
5 Mbits/s
@ f=1MHz
3
10
30
7
50
56
Units
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
ohms
Notes
1
1
1
Notes
1 This is the variation in the total delay through buffers, transmission lines, differential receivers
etc., caused by such things as short term variation in supply voltages and differences in delays
for rising and falling edges.
Table 7.2
Link
90%
LinkOut
10%
TJQr
TJQf
90%
LinkIn
10%
TJDr
TJDf
Figure 7.2 IMS T225 link timing
29 / 56
IMS T225
LinkOut
1.5 V
Latest TJQJD
Earliest TJQJD
LinkIn
1.5 V
TJBskew
Figure 7.3 IMS T225 buffered link timing
Transputer family device A
LinkOut
LinkIn
LinkIn
LinkOut
Transputer family device B
Figure 7.4 IMS T225 links directly connected
Transputer family device A
LinkOut
LinkIn
RM=56 ohms
Zo=100 ohms
LinkIn
LinkOut
Zo=100 ohms
RM=56 ohms
Transputer family device B
Figure 7.5 IMS T225 links connected by transmission line
Transputer family device A
LinkOut
LinkIn
buffers
LinkIn
LinkOut
Transputer family device B
Figure 7.6 IMS T225 links connected by buffers
30 / 56
8 Electrical specifications
8
Electrical specifications
8.1
Absolute maximum ratings
SYMBOL
PARAMETER
MIN
MAX
UNITS
NOTES
0
7.0
V
1, 2, 3
–0.5
VDD+0.5
V
1, 2, 3
mA
4
VDD
DC supply voltage
VI, VO
Voltage on input and output pins
II
Input current
25
OSCT
Output short circuit time (one pin)
1
s
2
TS
Storage temperature
150
oC
2
125
oC
2
2
W
–65
TA
Ambient temperature under bias
PDmax
Maximum allowable dissipation
–55
Notes
1 All voltages are with respect to GND.
2 This is a stress rating only and functional operation of the device at these or any other conditions
beyond those indicated in the operating sections of this specification is not implied. Stresses
greater than those listed may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
3 This device contains circuitry to protect the inputs against damage caused by high static voltages
or electrical fields. However, it is advised that normal precautions be taken to avoid application
of any voltage higher than the absolute maximum rated voltages to this high impedance circuit.
Unused inputs should be tied to an appropriate logic level such as VDD or GND.
4 The input current applies to any input or output pin and applies when the voltage on the pin is
between GND and VDD.
Table 8.1
8.2
Absolute maximum ratings
Operating conditions
SYMBOL
PARAMETER
VDD
DC supply voltage
VI, VO
Input or output voltage
CL
Load capacitance on any pin
TA
Operating temperature range
MIN
MAX
UNITS
NOTES
4.75
5.25
V
1
0
VDD
V
1, 2
60
pF
3
70
oC
4
0
Notes
1 All voltages are with respect to GND.
2 Excursions beyond the supplies are permitted but not recommended; see DC characteristics.
3 Excluding LinkOut load capacitance.
4 Air flow rate 400 linear ft/min transverse air flow.
Table 8.2
Operating conditions
31 / 56
IMS T225
8.3
DC electrical characteristics
SYMBOL
PARAMETER
MIN
MAX
UNITS
NOTES
VIH
High level input voltage
2.0
VDD+0.5
V
1, 2
VIL
Low level input voltage
–0.5
0.8
V
1, 2
II
Input current
@ GND<VI<VDD
mA
1, 2
VOH
Output high voltage
@ IOH=2mA
V
1, 2
VOL
Output low voltage
@ IOL=4mA
V
1, 2
IOZ
Tristate output current
@ GND<V0<VDD
10
mA
1, 2
PD
Power dissipation
700
mW
2, 3
CIN
Input capacitance
@ f=1MHz
7
pF
COZ
Output capacitance
@ f=1MHz
10
pF
10
VDD–1
0.4
Notes
1 All voltages are with respect to GND.
2 Parameters for IMS T225-S measured at 4.75V<VDD<5.25V and 0oC<TA<70oC.
Input clock frequency = 5 MHz.
3 Power dissipation varies with output loading and program execution.
Table 8.3
32 / 56
DC characteristics
8 Electrical specifications
8.4
Equivalent circuits
IOL
1.5V
D.U.T.
1MW
50pF
IOH
GND
Note: This circuit represents the device sinking IOL and sourcing IOH with a 50pF capacitive load.
Figure 8.1 Load circuit for AC measurements
VDD–1
Inputs
VIH
0V
VDD–1
Inputs
0V
VIL
tpHL
VDD
1.5V
Outputs
0V
tpLH
VDD
Outputs
1.5V
0V
Figure 8.2 AC measurements timing waveforms
33 / 56
IMS T225
8.5
AC timing characteristics
SYMBOL
PARAMETER
MIN
MAX
UNITS
NOTES
TDr
Input rising edges
2
20
ns
1, 2
TDf
Input falling edges
2
20
ns
1, 2
TQr
Output rising edges
25
ns
1
TQf
Output falling edges
15
ns
1
Notes
1 Non-link pins; see section on links.
2 All inputs except ClockIn; see section on ClockIn.
Table 8.4 Input and output edges
90%
90%
10%
10%
TDr
TDf
90%
90%
10%
10%
TQr
TQf
Figure 8.3 IMS T225 input and output edge timing
30
30
Rise time
20
Time
ns
10
Fall time
Rise time
Time
ns
20
10
Fall time
40
60
80 100
Load capacitance pF
Link
Figure 8.4 Typical rise/fall times
34 / 56
40
60
80 100
Load capacitance pF
EMI
8 Electrical specifications
8.6
Power rating
Internal power dissipationPINT of transputer and peripheral chips depends on VDD, as shown in figure 8.5.
PINT is substantially independent of temperature.
600
T225–25
500
Power
PINT
mW
400
300
4.4
4.6
4.8
5.0
5.2
5.4
5.6
VDD Volts
Figure 8.5 IMS T225 internal power dissipation vs VDD
Total power dissipation PD of the chip is
PD = PINT + PIO
where PIO is the power dissipation in the input and output pins; this is application dependent.
Internal working temperature TJ of the chip is
TJ = TA + q JA * PD
where TA is the external ambient temperature in oC and qJA is the junction-to-ambient thermal resistance
in oC/W.
Further information about device thermal characteristics can be found in section 9.4.
35 / 56
IMS T225
9
Package details
9.1
68 pin grid array package
Figure 9.1 IMS T225 68 pin grid array package pinout
36 / 56
9 Package details
Figure 9.2 IMS T225 68 pin grid array package dimensions
37 / 56
IMS T225
9.2
68 pin PLCC J-bend package
Figure 9.3 IMS T225 68 pin PLCC J-bend package pinout
38 / 56
9 Package details
Figure 9.4 IMS T225 68 pin PLCC J-bend package dimensions
39 / 56
IMS T225
9.3
100 pin cavity-up ceramic quad flat pack (CQFP) package
Figure 9.5 IMS T225 100 pin cavity-up ceramic quad flat pack package pinout
40 / 56
9 Package details
Figure 9.6 IMS T225 100 pin cavity-up ceramic quad flat pack package dimensions
41 / 56
IMS T225
9.4
Thermal specification
The IMS T225 is tested to a maximum silicon temperature of 100_C. For operation within the given specifications, the case temperature should not exceed 85_C.
For temperatures above 85_C the operation of the device cannot be guaranteed and reliability may be
impaired.
For further information on reliability refer to the SGS–THOMSON Microelectronics Quality and Reliability
Program.
42 / 56
10 Ordering
10
Ordering
This section indicates the designation of speed and package selections for the various devices. Speed
of ClockIn is 5 MHz for all parts. Transputer processor cycle time is nominal; it can be calculated more
exactly using the phase lock loop factor PLLx, as detailed in the external memory interface section 5.
For availability contact your local SGS–THOMSON sales office or authorized distributor.
SGS-THOMSON
designation
Processor
clock speed
Processor
cycle time
PLLx
IMS T225-G25S
25.0 MHz
40ns
5.0
68 pin ceramic pin grid array
IMS T225-J25S
25.0 MHz
40ns
5.0
68 pin PLCC J–bend
IMS T225-F25S
25.0 MHz
40ns
5.0
100 pin ceramic quad flat pack
Table 10.1
Package
IMS T225 ordering details
An extended temperature version is available, see the IMS T225E Datasheet for details.
43 / 56
IMS T225
11
Transputer instruction set summary
11.1
Introduction
The Function Codes table 11.9 (page 48) gives the basic function code set. Where the operand value is
less than 16, a single byte encodes the complete instruction. If the operand value is greater than 15, one
prefix instruction (pfix) is required for each additional four bits of the operand. If the operand is negative
the first prefix instruction will be nfix. Examples of prefix coding are given in table 11.1.
Mnemonic
ldc
#3
ldc
#35
Function code
Memory code
#4
#43
is coded as
pfix
#3
#2
#23
ldc
#5
#4
#45
ldc
#987
is coded as
pfix
#9
#2
#29
pfix
#8
#2
#28
ldc
#7
#4
#47
ldc
–31
( ldc #FFFFFFE1)
( ldc #FFE1) {
is coded as
{
nfix
#1
#6
#61
ldc
#1
#4
#41
IMS T222, IMS T225
Table 11.1 prefix coding
Tables 11.10 to 11.30 (pages 48–55) give details of the operation codes. Where an operation code is less
than 16 (e.g. add: operation code 05), the operation can be stored as a single byte comprising the operate
function code F and the operand (5 in the example). Where an operation code is greater than 15 (e.g. ladd:
operation code 16), the prefix function code 2 is used to extend the instruction.
Mnemonic
add
Function code
( op. code #5)
Memory code
#F5
is coded as
opr
ladd
add
#F
( op. code #16)
#F5
#21F6
is coded as
pfix
#1
#2
#21
opr
#6
#F
#F6
Table 11.2 operate coding
44 / 56
11 Transputer instruction set summary
11.1.1
Product identity numbers
The load device identity (lddevid) instruction (table 11.10) pushes the device type identity into the A register. Each product is allocated a unique group of numbers for use with the lddevid instruction. Product identity numbers are given in table 11.3.
Product
IMS T425
IMS T805
IMS T225
IMS T400
Identity numbers
0 to 9 inclusive
10 to 19 inclusive
40 to 49 inclusive
50 to 59 inclusive
Table 11.3 Product identity numbers
11.1.2
Floating point unit
In the floating point unit (FPU) basic addition, subtraction, multiplication and division operations are performed by single instructions. However, certain less frequently used floating point instructions are selected
by a value in register A (when allocating registers, this should be taken into account). A load constant instruction ldc is used to load register A; the floating point entry instruction fpentry then uses this value to
select the floating point operation. This pair of instructions is termed a selector sequence.
In the Floating Point Operation Codes tables 11.23 to 11.29, a selector sequence code is indicated in the
Memory Code column by s. The code given in the Operation Code column is the indirection code, the operand for the ldc instruction.
The FPU and processor operate concurrently, so the actual throughput of floating point instructions is better than that implied by simply adding up the instruction times. For full details see Transputer Instruction
Set – A Compiler Writer’s Guide.
11.1.3
Notation
The Processor Cycles column refers to the number of periods TPCLPCL (refer to ProcClockOut) taken
by an instruction executing in internal memory. The number of cycles is given for the basic operation only;
where the memory code for an instruction is two bytes, the time for the prefix function (one cycle) should
be added. Some instruction times vary.Where a letter is included in the cycles column it is interpreted from
table 11.4.
Ident
b
m{
Interpretation
Bit number of the highest bit set in register A. Bit 0 is the least significant bit.
Bit number of the highest bit set in the absolute value of register A. Bit 0 is the least significant bit.
n
Number of places shifted.
w
Number of words in the message. Part words are counted as full words. If the message is not
word aligned the number of words is increased to include the part words at either end of the
message.
p{
Number of words per row.
r{
Number of rows.
{ does not apply to IMS T225
Table 11.4 Instruction set interpretation
45 / 56
IMS T225
The DEF column of the tables indicates the descheduling/error features of an instruction as described in
table .
Ident
Feature
See section:
D
The instruction is a descheduling point
11.2
E
The instruction will affect the Error flag
11.3
The instruction will affect the FP_Error flag
11.6
F{
{ applies to IMS T805 only
Table 11.5 Instruction features
11.2
Descheduling points
The instructions in table 11.6 are the only ones at which a process may be descheduled. They are also
the ones at which the processor will halt if the Analyse pin is asserted (refer to Analyse section).
input message
output message
output byte
output word
timer alt wait
timer input
stop on error
alt wait
jump
loop end
end process
start process
Table 11.6 Descheduling point instructions
11.3
Error instructions
The instructions in table 11.7 are the only ones which can affect the Error flag directly. Note, however, that
the floating point unit error flag FP_Error is set by certain floating point instructions (section 11.6), and that
Error can be set from this flag by fpcheckerror.
add
add constant
subtract
multiply
fractional multiply {
divide
long add
long subtract
long divide
set error
testerr
fpcheckerror }
check word
check subscript from 0
check single
remainder
check count from 1
{ does not apply to IMS T225
} applies to IMS T805 only
Table 11.7 Error setting instructions
11.4
Debugging support
Table 11.20 (page 52) contains a number of instructions to facilitate the implementation of breakpoints.
These instructions overload the operation of j0. Normally j0 is a no-op which might cause descheduling.
Setj0break enables the breakpointing facilities and causes j0 to act as a breakpointing instruction. When
breakpointing is enabled, j0 swaps the current Iptr and Wptr with an Iptr and Wptr stored above MemStart. The break instruction does not cause descheduling, and preserves the state of the registers. It is possible to single step the processor at machine level using these instructions. Refer to Support for debugging/breakpointing in transputers (technical note 61) for more detailed information regarding debugger
support.
11.5
Block move
The block move instructions (Table 11.21) move any number of bytes from any byte boundary in memory,
to any other byte boundary, using the smallest possible number of word read, and word or part-word writes.
46 / 56
11 Transputer instruction set summary
A block move instruction can be interrupted by a high priority process. On interrupt, block move is completed to a word boundary, independent of start position. When restarting after interrupt, the last word written is written again. This appears as an unnecessary read and write in the simplest case of word aligned
block moves, and may cause problems with FIFOs. This problem can be overcome by incrementing the
saved destination (BregIntSaveLoc) and source pointer (CregIntSaveLoc) values by BytesPerWord
during the high priority process.
11.6
Floating point errors (IMS T805 only)
The FPU has its own error flag FP_Error. This reflects the state of evaluation within the FPU and is set
in circumstances where invalid operations, division by zero or overflow exceptions to the ANSI-IEEE
754-1985 standard would be flagged. FP_Error is also set if an input to a floating point operation is infinite
or is not a number (NaN). The FP_Error flag can be set, tested and cleared without affecting the main Error
flag, but can also set Error when required. Depending on how a program is compiled, it is possible for both
unchecked and fully checked floating point arithmetic to be performed.
The instructions in table 11.8 are the only ones which can affect the floating point error flag FP_Error.
Error is set from this flag by fpcheckerror if FP_Error is set.
fpadd
fpsub
fpmul
fpdiv
fpldnladdsn
fpldnladddb
fpldnlmulsn
fpldnlmuldb
fpremfirst
fpusqrtfirst
fpgt
fpeq
fpuseterror
fpuclearerror
fptesterror
fpuexpincby32
fpuexpdecby32
fpumulby2
fpudivby2
fpur32tor64
fpur64tor32
fpucki32
fpucki64
fprtoi32
fpuabs
fpint
Table 11.8 Floating point error setting instructions
11.7
General instructions
The following tables list the complete instruction set which is common to all variants of the transputer. Exceptions are noted at the bottom of each table by { or }.
47 / 56
IMS T225
Function
Code
Memory
Code
Mnemonic
0
1
2
3
4
5
6
7
8
9
A
0X
1X
2X
3X
4X
5X
6X
7X
8X
9X
AX
j
ldlp
pfix
ldnl
ldc
ldnlp
nfix
ldl
adc
call
cj
B
C
D
E
F
BX
CX
DX
EX
FX
ajw
eqc
stl
stnl
opr
Processor
Cycles
3
1
1
2
1
1
1
2
1
7
2
4
1
2
1
2
–
Name
jump
load local pointer
prefix
load non–local
load constant
load non–local pointer
negative prefix
load local
add constant
call
conditional jump (not taken)
conditional jump (taken)
adjust workspace
equals constant
store local
store non-local
operate
DEF
D
E
Table 11.9 Function codes
Operation
Code
Memory
Code
Mnemonic
Processor
Cycles
2A
3E
3D
18
50
1C
17
54
17C
7E
22FA
23FE
23FD
21F8
25F0
21FC
21F7
25F4
2127FC
27FE
testpranal
saveh
savel
sthf
sthb
stlf
stlb
sttimer
lddevid
ldmemstartval
2
4
4
1
1
1
1
1
1
1
Table 11.10
48 / 56
Name
test processor analyzing
save high priority queue registers
save low priority queue registers
store high priority front pointer
store high priority back pointer
store low priority front pointer
store low priority back pointer
store timer
load device identity
load value of memstart address
Processor initialisation operation codes
DEF
11 Transputer instruction set summary
Operation
Memory
Mnemonic
Processor Cycles
Code
Code
24F6
24FB
23F3
23F2
24F1
24F0
and
or
xor
not
shl
shr
16-bit
devices
1
1
1
1
n+2
n+2
32-bit
devices
1
1
1
1
n+2
n+2
46
4B
33
32
41
40
05
0C
53
72 {
F5
FC
25F3
27F2
add
sub
mul
fmul
1
1
23
1
1
38
35
40
39
37
2
1
1
b+4
m+5
2C
22FC
div
1F
21FF
rem
09
F9
gt
04
F4
diff
52
25F2
sum
08
F8
prod
08
F8
prod
{ does not apply to IMS T225
24
21
2
1
1
b+4
m+5
Table 11.11
Operation
Memory Mnemonic
Code
Code
16
38
37
4F
31
1A
36
21F6
23F8
23F7
24FF
23F1
21FA
23F6
ladd
lsub
lsum
ldiff
lmul
ldiv
lshl
35
23F5
lshr
19
21F9
norm
Name
DEF
and
or
exclusive or
bitwise not
shift left
shift right
add
subtract
multiply
fractional multiply (no rounding)
fractional multiply (rounding)
divide
remainder
greater than
difference
sum
product for positive register A
product for negative register A
E
E
E
E
E
E
E
Arithmetic/logical operation codes
Processor Cycles
16-bit
devices
2
2
3
3
17
19
n+3
n–12
n+3
n–12
n+5
n–10
3
32-bit
devices
2
2
3
3
33
35
n+3
n–28
n+3
n–28
n+5
n–26
3
Name
long add
long subtract
long sum
long diff
long multiply
long divide
long shift left (n<32)
long shift left(n 32)
long shift right (n<32)
long shift right (n 32)
normalise (n<32)
normalise (n 32)
normalise (n=64)
DEF
E
E
E
{ (n<16)
{ (n 16)
{ (n<16)
{ (n 16)
{ (n<16)
{ (n 16)
{ (n=32)
{ for IMS T225
Table 11.12
Long arithmetic operation codes
49 / 56
IMS T225
Operation
Code
Memory
Code
00
F0
3A
Mnemonic
Processor
Cycles
Name
rev
1
reverse
23FA
xword
4
extend to word
56
25F6
cword
5
check word
1D
21FD
xdble
2
extend to double
4C
24FC
csngl
3
check single
42
24F2
mint
1
minimum integer
5A
25FA
dup
1
duplicate top of stack
79
27F9
pop
1
pop processor stack
Table 11.13
Operation Memory Mnemonic
DEF
E
E
General operation codes
Processor Cycles
Name
Code
Code
02
F2
bsub
16-bit
devices
1
0A
FA
wsub
2
2
word subscript
81 {
28F1
wsubdb
3
3
form double word subscript
34
23F4
bcnt
2
2
byte count
3F
23FF
wcnt
4
5
word count
01
F1
lb
5
5
load byte
3B
23FB
sb
4
4
store byte
4A
24FA
move
2w+8
2w+8
DEF
32-bit
devices
1
byte subscript
move message
{ does not apply to IMS T225
Table 11.14
Mnemonic
Indexing/array operation codes
Operation
Code
Memory
Code
Processor
Cycles
Name
DEF
22
22F2
ldtimer
2
load timer
2B
22FB
tin
30
timer input (time future)
D
4
timer input (time past)
D
4E
24FE
talt
4
timer alt start
51
25F1
taltwt
15
timer alt wait (time past)
D
48
timer alt wait (time future)
D
47
24F7
enbt
8
enable timer
2E
22FE
dist
23
disable timer
Table 11.15 Timer handling operation codes
50 / 56
11 Transputer instruction set summary
Operation
Code
Memory
Code
Mnemonic
07
0B
0F
0E
F7
FB
FF
FE
43
44
24F3
24F4
alt
altwt
45
24F5
49
30
in
out
outword
outbyte
Processor
Cycles
2w+19
2w+19
23
23
Name
DEF
input message
output message
output word
output byte
D
D
D
D
alt
alt
alt
alt
D
D
altend
2
5
17
4
24F9
23F0
enbs
diss
3
4
enable skip
disable skip
12
48
21F2
24F8
resetch
enbc
2F
22FF
disc
3
7
5
8
reset channel
enable channel (ready)
enable channel (not ready)
disable channel
start
wait (channel ready)
wait (channel not ready)
end
Table 11.16 Input/output operation codes
Operation
Code
Memory
Code
20
1B
3C
06
21
22F0
21FB
23FC
F6
22F1
Mnemonic
ret
ldpi
gajw
gcall
lend
5
2
2
4
10
5
Table 11.17
Operation
Code
Memory
Code
0D
03
39
15
1E
FD
F3
23F9
21F5
21FE
Processor
Cycles
Mnemonic
startp
endp
runp
stopp
ldpri
Table 11.18
Name
return
load pointer to instruction
general adjust workspace
general call
loop end (loop)
loop end (exit)
DEF
D
D
Control operation codes
Processor
Cycles
12
13
10
11
1
Name
start process
end process
run process
stop process
load current priority
DEF
D
Scheduling operation codes
51 / 56
IMS T225
Operation
Code
Memory
Code
Mnemonic
13
4D
29
21F3
24FD
22F9
csub0
ccnt1
testerr
10
55
57
58
59
21F0
25F5
25F7
25F8
25F9
seterr
stoperr
clrhalterr
sethalterr
testhalterr
Table 11.19
Operation
Code
Memory
Code
0
00
jump 0
B1
2BF1
break
B2
B3
B4
7A
7B
7C
7D
2BF2
2BF3
2BF4
27FA
27FB
27FC
27FD
clrj0break
setj0break
testj0break
timerdisableh
timerdisablel
timerenableh
timerenablel
Processor
Cycles
2
3
2
3
1
2
1
1
2
Name
check subscript from 0
check count from 1
test error false and clear (no error)
test error false and clear (error)
set error
stop on error (no error)
clear halt–on–error
set halt–on–error
test halt–on–error
E
E
E
D
Error handling operation codes
Mnemonic
Table 11.20
Mnemonic
Processor
Cycles
Name
DEF
3
11
13
9
11
1
1
2
1
1
6
6
jump 0 (break not enabled)
jump 0 (break enabled, high priority)
jump 0 (break enabled, low priority)
break (high priority)
break (low priority)
clear jump 0 break enable flag
set jump 0 break enable flag
test jump 0 break enable flag set
disable high priority timer interrupt
disable low priority timer interrupt
enable high priority timer interrupt
enable low priority timer interrupt
D
Debugger support codes
Operation
Code
Memory
Code
5B {
25FB
move2dinit
8
5C {
25FC
move2dall
(2p+23)*r
2D block copy
5D {
25FD
move2dnonzero
(2p+23)*r
2D block copy non-zero bytes
5E {
25FE
(2p+23)*r
2D block copy zero bytes
Processor
Cycles
Name
initialise data for 2D block move
{ does not apply to IMS T225
Table 11.21 2D block move operation codes
52 / 56
DEF
DEF
11 Transputer instruction set summary
Operation
Code
Memory
Code
Mnemonic
Processor
Cycles
Name
74
27F4
crcword
35
calculate crc on word
75
27F5
crcbyte
11
calculate crc on byte
76
27F6
bitcnt
b+2
count bits set in word
77
27F7
bitrevword
36
78
27F8
bitrevnbits
n+4
DEF
reverse bits in word
reverse bottom n bits in word
Table 11.22 CRC and bit operation codes
11.8
Floating point instructions
11.9
Floating point instructions for IMS T805 only
Operation
Code
Memory
Code
Mnemonic
Processor
Cycles
Name
DEF
8E
28FE
fpldnlsn
2
fp load non-local single
8A
28FA
fpldnldb
3
fp load non-local double
86
28F6
fpldnlsni
4
fp load non-local indexed single
82
28F2
fpldnldbi
6
fp load non-local indexed double
9F
29FF
fpldzerosn
2
load zero single
A0
2AF0
fpldzerodb
2
load zero double
AA
2AFA
fpldnladdsn
8/11
fp load non local & add single
F
A6
2AF6
fpldnladddb
9/12
fp load non local & add double
F
AC
2AFC
fpldnlmulsn
13/20
fp load non local & multiply single
F
A8
2AF8
fpldnlmuldb
21/30
fp load non local & multiply double
F
88
28F8
fpstnlsn
2
fp store non-local single
84
28F4
fpstnldb
3
fp store non-local double
9E
29FE
fpstnli32
4
store non-local int32
Processor cycles are shown as Typical/Maximum cycles.
Table 11.23
Floating point load/store operation codes
Operation
Code
Memory
Code
Mnemonic
Processor
Cycles
Name
AB
2AFB
fpentry
1
floating point unit entry
A4
2AF4
fprev
1
fp reverse
A3
2AF3
fpdup
1
fp duplicate
DEF
Table 11.24 Floating point general operation codes
53 / 56
IMS T225
Operation
Code
Memory
Code
22
s
06
Mnemonic
Processor
Cycles
Name
fpurn
1
set rounding mode to round nearest
s
fpurz
1
set rounding mode to round zero
04
s
fpurp
1
set rounding mode to round positive
05
s
fpurm
1
set rounding mode to round minus
Table 11.25
DEF
Floating point rounding operation codes
Operation
Code
Memory
Code
Mnemonic
83
28F3
fpchkerror
1
check fp error
E
9C
29FC
fptesterror
2
test fp error false and clear
F
23
s
fpuseterror
1
set fp error
F
9C
s
fpuclearerror
1
clear fp error
F
Table 11.26
Mnemonic
Processor
Cycles
Name
DEF
Floating point error operation codes
Operation
Code
Memory
Code
Processor
Cycles
Name
DEF
94
29F4
fpgt
4/6
fp greater than
F
95
29F5
fpeq
3/5
fp equality
F
92
29F2
fpordered
3/4
fp orderability
91
29F1
fpnan
2/3
fp NaN
93
29F3
fpnotfinite
2/2
fp not finite
0E
s
fpuchki32
3/4
check in range of type int32
F
0F
s
fpuchki64
3/4
check in range of type int64
F
Processor cycles are shown as Typical/Maximum cycles.
Table 11.27
Floating point comparison operation codes
Operation
Code
Memory
Code
Mnemonic
Processor
Cycles
Name
07
s
fpur32tor64
3/4
real32 to real64
F
08
s
fpur64tor32
6/9
real64 to real32
F
9D
29FD
fprtoi32
7/9
real to int32
F
96
29F6
fpi32tor32
8/10
int32 to real32
98
29F8
fpi32tor64
8/10
int32 to real64
9A
29FA
fpb32tor64
8/8
bit32 to real64
0D
s
fpunoround
2/2
real64 to real32, no round
A1
2AF1
fpint
5/6
round to floating integer
Processor cycles are shown as Typical/Maximum cycles.
Table 11.28 Floating point conversion operation codes
54 / 56
DEF
F
11 Transputer instruction set summary
Operation
Memory
Code
Code
87
28F7
89
Processor Cycles
Mnemonic
Single
Double
fpadd
6/9
6/9
fp add
F
28F9
fpsub
6/9
6/9
fp subtract
F
8B
28FB
fpmul
11/18
18/27
fp multiply
F
8C
28FC
fpdiv
16/28
31/43
fp divide
F
0B
s
2/2
2/2
fp absolute
F
8F
28FF
fpremfirst
36/46
36/46
fp remainder first step
F
90
29F0
fpremstep
32/36
32/36
fp remainder iteration
01
s
fpusqrtfirst
27/29
27/29
fp square root first step
02
s
fpusqrtstep
42/42
42/42
fp square root step
03
s
fpusqrtlast
8/9
8/9
fp square root end
0A
s
fpuexpinc32
6/9
6/9
multiply by 232
fpuabs
Name
DEF
F
F
232
F
09
s
fpuexpdec32
6/9
6/9
divide by
12
s
fpumulby2
6/9
6/9
multiply by 2.0
F
11
s
fpudivby2
6/9
6/9
divide by 2.0
F
Processor cycles are shown as Typical/Maximum cycles.
Table 11.29 Floating point arithmetic operation codes
11.10 Floating point instructions for IMS T400 and IMS T425 only
Operation
Code
Memory
Code
Mnemonic
Processor
Cycles
73
27F3
cflerr
3
check floating point error
9C
29FC
fptesterr
1
load value true (FPU not present)
63
26F3
unpacksn
15
unpack single length fp number
6D
26FD
roundsn
12/15
round single length fp number
6C
26FC
postnormsn
5/30
post–normalise correction of single
length fp number
71
27F1
ldinf
1
Name
DEF
E
load single length infinity
Processor cycles are shown as Typical/Maximum cycles.
Table 11.30 Floating point support operation codes
55 / 56
IMS T225
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publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics.
E
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56 / 56