14-Bit, 500 kSPS PulSAR™ ADC in MSOP/QFN AD7946 Preliminary Technical Data FEATURES APPLICATION DIAGRAM 14-bit resolution with no missing codes Throughput: 500 kSPS INL: ±0.4 LSB typ, ±1 LSB max (±0.0061 % of FSR) S/(N + D): 85 dB @ 20 kHz THD: −100 dB @ 20 kHz Pseudo-differential analog input range 0 V to VREF with VREF up to VDD No pipeline delay Single-supply 5V operation with 1.8 V/2.5 V/3 V/5 V logic interface Serial interface SPI®/QSPI™/µWire/DSP compatible Daisy chain multiple ADCs and BUSY indicator Power dissipation 3.3 mW @ 5 V/100 kSPS, 3.3 µW @ 5 V/100 SPS Stand-by current: 1 nA 10-lead package: MSOP (MSOP-8 size) and QFN (LFCSP), 3 mm × 3 mm same space as SOT-23 Pin-for-pin compatible with the 16-Bit AD7686 APPLICATIONS Battery-powered equipment Data acquisition Instrumentation Medical instruments Process control 0 TO VREF IN+ IN– 5V REF VDD VIO SDI AD7946 1.8 TO VDD SCK SDO GND 3- OR 4-WIRE INTERFACE (SPI, DAISY CHAIN, CS) CNV Figure 1. GENERAL DESCRIPTION The AD7946 is a 14-bit, charge redistribution successive approximation, analog-to-digital converter (ADC) that operates from a single 5V power supply, VDD. It contains a low power, high speed, 14-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port. The part also contains a low noise, wide bandwidth, short aperture delay track-and-hold circuit. On the CNV rising edge, it samples an analog input IN+ between 0 V to REF with respect to a ground sense IN−. The reference voltage, REF, is applied externally and can be set up to the supply voltage. Its power scales linearly with throughput. Table 1. MSOP, QFN (LFCSP)/SOT-23 14 and16-Bit ADC Type 16-Bit True Differential 16-Bit Pseudo Differential/Unipolar 16-Bit Unipolar 14-Bit Pseudo Differential/Unipolar 14-Bit Unipolar 0.5 TO 5V 100 kSPS AD7684 250 kSPS AD7687 500 kSPS AD7688 AD7683 AD7685 AD7694 AD7686 AD7942 AD7946 AD7680 The SPI compatible serial interface also features the ability, using the SDI input, to daisy chain several ADCs on a single 3wire bus and provides an optional BUSY indicator. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using the separate supply VIO. The AD7946 is housed in a 10-lead MSOP or a 10-lead QFN (LFCSP) with operation specified from −40°C to +85°C. AD7940 Rev Pr D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. AD7946 Preliminary Technical Data TABLE OF CONTENTS Specifications..................................................................................... 3 Converter Operation.................................................................. 12 Timing Specifications....................................................................... 5 Typical Connection Diagram ................................................... 13 Absolute Maximum Ratings............................................................ 6 Digital Interface.......................................................................... 17 ESD Caution.................................................................................. 6 Application Hints ........................................................................... 24 Pin Configuration and Function Descriptions............................. 7 Layout .......................................................................................... 24 Terminology ...................................................................................... 8 Evaluating the AD7946’s Performance.................................... 24 Typical Performance Characteristics ............................................. 9 Outline Dimensions ....................................................................... 25 Circuit Information.................................................................... 12 Ordering Guide .......................................................................... 26 REVISION HISTORY 5/04—Revision D: Preliminary Rev Pr D | Page 2 of 27 Preliminary Technical Data AD7946 SPECIFICATIONS VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted. Table 2. Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Analog Input CMRR Leakage Current at 25°C Input Impedance ACCURACY No Missing Codes Differential Linearity Error Integral Linearity Error Transition Noise Gain Error2, TMIN to TMAX Gain Error Temperature Drift Offset Error2, TMIN to TMAX Offset Temperature Drift Power Supply Sensitivity THROUGHPUT Conversion Rate Transient Response AC ACCURACY Signal-to-Noise Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) Conditions Min 14 IN+ − IN− IN+ IN− fIN = 250 kHz Acquisition Phase 0 −0.1 −0.1 Typ Max Unit Bits VREF VDD + 0.1 0.1 V V V dB nA 65 1 14 −0.7 −1 REF = VDD = 5 V VDD = 5V ± 5% ±0.25 ±0.4 0.33 ±TBD ±TBD ±TBD ±TBD ±TBD 0 83 83 Intermodulation Distortion4 1 ±TBD ±TBD 500 400 Full-Scale Step fIN = 20 kHz, VREF = 5 V fIN = 20 kHz fIN = 20 kHz fIN = 20 kHz, VREF = 5 V fIN = 20 kHz, VREF = 5 V, −60 dB Input +0.7 +1 Bits LSB1 LSB LSB LSB ppm/°C mV ppm/°C LSB kSPS ns 85 −100 −100 85 25 dB3 dB dB dB dB TBD dB LSB means least significant bit. With the 5 V input range, one LSB is 305.2 µV. See Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference. 3 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 4 fIN1 = 21.4 kHz, fIN2 = 18.9 kHz, each tone at −7 dB below full-scale. 2 Rev Pr D | Page 3 of 27 AD7946 Preliminary Technical Data VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted. Table 3. Parameter REFERENCE Voltage Range Load Current SAMPLING DYNAMICS −3 dB Input Bandwidth Aperture Delay DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay VOL VOH POWER SUPPLIES VDD VIO VIO Range Standby Current1, 2 Power Dissipation TEMPERATURE RANGE3 Specified Performance 1 2 3 Conditions Min Typ 0.5 Max Unit VDD + 0.3 500 kSPS, REF = 5 V TBD V µA VDD = 5 V 9 2.5 MHz ns –0.3 0.7 × VIO −1 −1 0.3 × VIO VIO + 0.3 +1 +1 Serial 14 Bits Straight Binary Conversion Results Available Immediately after Completed Conversion 0.4 VIO − 0.3 ISINK= +500 µA ISOURCE= −500 µA Specified Performance Specified Performance 4.5 2.3 1.8 VDD and VIO = 5 V, 25°C VDD = 5 V, 100 SPS Throughput VDD = 5 V, 100 kSPS Throughput VDD = 5 V, 500 kSPS Throughput TMIN to TMAX 1 3.3 3.3 −40 With all digital inputs forced to VIO or GND as required. During acquisition phase. Contact Analog Devices for extended temperature range. Rev Pr D | Page 4 of 27 5.5 VDD + 0.3 VDD + 0.3 50 V V µA µA V V 5 25 V V V nA µW mW mW +85 °C Preliminary Technical Data AD7946 TIMING SPECIFICATIONS −40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated. Table 4. 1 Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time between Conversions CNV Pulse Width ( CS Mode ) SCK Period ( CS Mode ) SCK Period ( Chain Mode ) VIO above 4.5 V VIO above 3 V VIO above 2.7 V VIO above 2.3 V SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO above 4.5 V VIO above 3 V VIO above 2.7 V VIO above 2.3 V CNV or SDI Low to SDO D15 MSB Valid (CS Mode) VIO above 4.5 V VIO above 2.7 V VIO above 2.3 V CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) SDI Valid Setup Time from CNV Rising Edge (CS Mode) SDI Valid Hold Time from CNV Rising Edge (CS Mode) SCK Valid Setup Time from CNV Rising Edge (Chain Mode) SCK Valid Hold Time from CNV Rising Edge (Chain Mode) SDI Valid Setup Time from SCK Falling Edge (Chain Mode) SDI Valid Hold Time from SCK Falling Edge (Chain Mode) SDI High to SDO High (Chain Mode with BUSY indicator) VIO above 4.5 V VIO above 2.3 V 1 See Figure 2 and Figure 3 for load conditions. Rev Pr D | Page 5 of 27 Symbol tCONV tACQ tCYC tCNVH tSCK tSCK tSCKL tSCKH tHSDO tDSDO Min 0.5 400 2 10 15 Typ Max 1.6 19 20 21 22 7 7 5 Unit µs ns µs ns ns ns ns ns ns ns ns ns 14 15 16 17 ns ns ns ns 15 18 22 25 ns ns ns ns ns ns ns ns ns ns 15 26 ns ns tEN tDIS tSSDICNV tHSDICNV tSSCKCNV tHSCKCNV tSSDISCK tHSDISCK tDSDOSDI 15 0 5 5 5 4 AD7946 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs IN+1, IN−1, REF Supply Voltages VDD, VIO to GND VDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature θJA Thermal Impedance θJC Thermal Impedance Lead Temperature Range Vapor Phase (60 sec) Infrared (15 sec) 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rating GND − 0.3 V to VDD + 0.3 V or ±130 mA −0.3 V to +7 V ±7 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V −65°C to +150°C 150°C 200°C/W (MSOP-10) 44°C/W (MSOP-10) 215°C 220°C See the Analog Input section. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. 500µA IOL 1.4V TO SDO 500µA 02968-PrH-002 CL 50pF IOH Figure 2. Load Circuit for Digital Interface Timing 70% VIO 30% VIO tDELAY 2V OR VIO – 0.5V1 2V OR VIO – 0.5V1 0.8V OR 0.5V2 0.8V OR 0.5V2 NOTES 1. 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V. 2. 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V. Figure 3. Voltage Reference Levels for Timing Rev Pr D | Page 6 of 27 02968-PrH-003 tDELAY Preliminary Technical Data AD7946 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REF 1 10 VIO VDD 2 9 SDI 8 SCK IN– 4 7 SDO GND 5 6 CNV IN+ 3 AD7946 Figure 4.10-Lead MSOP and QFN (LFCSP) Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 Mnemonic REF Type1 AI 2 3 VDD IN+ P AI 4 5 6 IN− GND CNV AI P DI 7 8 9 SDO SCK SDI DO DI DI 10 VIO P Function Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should be decoupled closely to the pin with a 10 µF capacitor. Power Supply. Analog Input. It is referred to in IN−. The voltage range, i.e., the difference between IN+ and IN−, is 0 V to VREF. Analog Input Ground Sense. To be connected to the analog ground plane or to a remote sense ground. Power Supply Ground. Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part, chain or CS mode. In CS mode, it enables the SDO pin when low. In chain mode, the data should be read when CNV is high. Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 14 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY indicator feature is enabled. Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). 1 AI = Analog Input, DI = Digital Input, DO = Digital Output, and P = Power Rev Pr D | Page 7 of 27 AD7946 Preliminary Technical Data TERMINOLOGY Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (Figure 21). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Offset Error The first transition should occur at a level 1/2 LSB above analog ground (152.6 µV for the 0 V to 5 V range). The offset error is the deviation of the actual transition from that point. Gain Error The last transition (from 111 . . . 10 to 111 . . . 11) should occur for an analog voltage 1 1/2 LSB below the nominal full scale (4.999542 V for the 0 V to 5 V range). The gain error is the deviation of the actual level of the last transition from the ideal level after the offset has been adjusted out. Spurious-Free Dynamic Range (SFDR) The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to S/(N+D) by the following formula ENOB = (S /[N + D ]dB − 1.76 )/ 6.02) and is expressed in bits. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in dB. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in dB. Signal-to-(Noise + Distortion) Ratio (S/[N+D]) S/(N+D) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in dB. Aperture Delay Aperture delay is a measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response The time required for the ADC to accurately acquire its input after a full-scale step function was applied. Rev Pr D | Page 8 of 27 Preliminary Technical Data AD7946 TYPICAL PERFORMANCE CHARACTERISTICS Figure 5. Integral Nonlinearity vs. Code Figure 8. Differential Nonlinearity vs. Code Figure 6. Histogram of a DC Input at the Code Center Figure 9. Histogram of a DC Input at the Code Center Figure 7. FFT Plot Figure 10. S/[N + D] vs. Frequency Rev Pr D | Page 9 of 27 AD7946 Preliminary Technical Data Figure 11. SNR vs. Temperature Figure 14. SNR and THD vs. Input Level Figure 12. THD vs. Frequency Figure 15. Operating Currents vs. Supply Figure 13. THD, SFDR vs. Temperature Figure 16. Power-Down Currents vs. Temperature Rev Pr D | Page 10 of 27 Preliminary Technical Data AD7946 Figure 19. tDSDO vs. Capacitance Load and Supply Figure 17. Operating Currents vs. Temperature Figure 18. Offset and Gain Error vs. Temperature Rev Pr D | Page 11 of 27 AD7946 Preliminary Technical Data IN+ SWITCHES CONTROL LSB MSB 8,192C 4,096C 4C 2C C SW+ C BUSY REF COMP GND 8,192C 4,096C 4C 2C C CONTROL LOGIC OUTPUT CODE C MSB LSB SW– CNV IN– Figure 20. ADC Simplified Schematic CIRCUIT INFORMATION CONVERTER OPERATION The AD7946 is a fast, low power, single-supply, precise 14-bit ADC using a successive approximation architecture. The AD7946 is a successive approximation ADC based on a charge redistribution DAC. Figure 20 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 14 binary weighted capacitors, which are connected to the two comparator inputs. The AD7946 is capable of converting 500,000 samples per second (500 kSPS) and powers down between conversions. When operating at 100 SPS, for example, it consumes typically 3.3µW, ideal for battery-powered applications. The AD7946 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications. The AD7946 is specified from 4.5 V to 5.5 V, and can be interfaced to either 5 V, 3.3 V, 2.5 V, or 1.8 V digital logic. It is housed in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that combines space savings and allows flexible configurations. It is pin-for-pin-compatible with the 16 Bit ADC AD7686. During the acquisition phase, terminals of the array tied to the comparator’s input are connected to GND via SW+ and SW−. All independent switches are connected to the analog inputs. Thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN− inputs. When the acquisition phase is complete and the CNV input goes high, a conversion phase is initiated. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the inputs IN+ and IN− captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4 . . . VREF/16384). The control logic toggles these switches, starting with the MSB, in order to bring the comparator back into a balanced condition. After the completion of this process, the part returns to the acquisition phase and the control logic generates the ADC output code and a BUSY signal indicator. Because the AD7946 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process. Rev Pr D | Page 12 of 27 Preliminary Technical Data AD7946 TYPICAL CONNECTION DIAGRAM The ideal transfer characteristic for the AD7946 is shown in Figure 21 and Table 7. Figure 22 shows an example of the recommended connection diagram for the AD7946 when multiple supplies are available. ADC CODE (STRAIGHT BINARY) Transfer Functions 111...111 111...110 111...101 000...010 000...000 –FS –FS + 1 LSB 02968-PrH-006 000...001 +FS – 1 LSB +FS – 1.5 LSB –FS + 0.5 LSB ANALOG INPUT Figure 21. ADC Ideal Transfer Function Table 7. Output Codes and Ideal Input Voltages Description FSR – 1 LSB Midscale + 1 LSB Midscale Midscale – 1 LSB –FSR + 1 LSB –FSR Analog Input VREF = 5 V 4.999695 V 2.500305 V 2.5 V 2.499695 V 305.2 µV 0V Digital Output Code Hexa 3FFF1 2001 2000 1FFF 0001 00002 1 This is also the code for an overranged analog input (VIN+ – VIN above VREF – VGND). 2 This is also the code for an underranged analog input (VIN+ – VIN below VGND). (NOTE 1) ≥7V 5V REF 10µF (NOTE 2) 100nF 1.8V TO VDD ≥7V 100nF 33Ω REF VDD IN+ 0 TO VREF (NOTE 3) ≤–2V VIO SDI SCK AD7946 2.7nF (NOTE 4) IN– 3- OR 4-WIRE INTERFACE (NOTE 5) SDO CNV GND NOTE 1: SEE REFERENCE SECTION FOR REFERENCE SELECTION. NOTE 2: CREF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). NOTE 3: SEE DRIVER AMPLIFIER CHOICE SECTION. NOTE 4: OPTIONAL FILTER. SEE ANALOG INPUT SECTION. NOTE 5: SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE. Figure 22. Typical Application Diagram with multiple supplies Rev Pr D | Page 13 of 27 AD7946 Preliminary Technical Data Analog Input Figure 23 shows an equivalent circuit of the input structure of the AD7946. The two diodes, D1 and D2, provide ESD protection for the analog inputs IN+ and IN−. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V because this will cause these diodes to become forward-biased and start conducting current. However, these diodes can handle a forward-biased current of 130 mA maximum. For instance, these conditions could eventually occur when the input buffer’s (U1) supplies are different from VDD. In such a case, an input buffer with a short-circuit current limitation can be used to protect the part. VDD D1 IN+ OR IN– CPIN RIN CIN D2 GND During the acquisition phase, the impedance of the analog input IN+ can be modeled as a parallel combination of capacitor C1 and the network formed by the series connection of R1 and C2. C1 is primarily the pin capacitance. R1 is typically 600 Ω and is a lumped component made up of some serial resistors and the on resistance of the switches. C2 is typically 30 pF and is mainly the ADC sampling capacitor. During the conversion phase, where the switches are opened, the input impedance is limited to C1. R1 and C2 make a 1-pole, low-pass filter that reduces undesirable aliasing effect and limits the noise. When the source impedance of the driving circuit is low, the AD7946 can be driven directly. Large source impedances significantly affect the ac performance, especially total harmonic distortion (THD). The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency, as shown in Figure 25. Figure 23. Equivalent Analog Input Circuit This analog input structure allows the sampling of the differential signal between IN+ and IN−. By using this differential input, small signals common to both inputs are rejected, as shown in Figure 24, which represents the typical CMRR over frequency. For instance, by using IN− to sense a remote signal ground, ground potential differences between the sensor and the local ADC ground are eliminated. Figure 25. THD vs. Analog Input Frequency and Source Resistance Figure 24. Analog Input CMRR vs. Frequency Rev Pr D | Page 14 of 27 Preliminary Technical Data AD7946 Driver Amplifier Choice Table 8. Recommended Driver Amplifiers. Although the AD7946 is easy to drive, the driver amplifier needs to meet the following requirements: Amplifier AD8021 AD8022 OP184 AD8605, AD8615 AD8519 AD8031 The noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the SNR and transition noise performance of the AD7946. Note that the AD7946 has a noise much lower than most of the other 14bit ADCs and, therefore, can be driven by a noisier op amp while preserving the same or better system performance. The noise coming from the driver is filtered by the AD7946 analog input circuit 1-pole, low-pass filter made by R1 and C2 or by the external filter, if one is used. • • For ac applications, the driver needs to have a THD performance suitable to that of the AD7946. Figure 12 gives the THD versus frequency that the driver should exceed. For multichannel multiplexed applications, the driver amplifier and the AD7946 analog input circuit must be able to settle for a full-scale step of the capacitor array at a 14-bit level (0.006%). In the amplifier’s data sheet, settling at 0.1% to 0.01% is more commonly specified. This could differ significantly from the settling time at a 14-bit level and should be verified prior to driver selection. Typical Application Very low noise and high frequency Low noise and high frequency Low power, low noise, and low frequency 5 V single-supply, low power Small, low power and low frequency High frequency and low power Voltage Reference Input The AD7946 voltage reference input, REF, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the REF and GND pins as explained in the Layout section. When REF is driven by a very low impedance source, e.g., a reference buffer using the AD8031 or the AD8605, a 10 µF (X5R, 0805 size) ceramic chip capacitor is appropriate for optimum performance. If an unbuffered reference voltage is used, the decoupling value depends on the reference used. For instance, a 22 µF (X5R, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift ADR43x reference. If desired, smaller reference decoupling capacitor values down to 2.2 µF can be used with a minimal impact on performance, especially DNL. Rev Pr D | Page 15 of 27 AD7946 Preliminary Technical Data Power Supply Supplying the ADC from the Reference The AD7946 is specified 4.5 V to 5.5 V. It uses two power supply pins: a core supply VDD and a digital input/output interface supply VIO. VIO allows direct interface with any logic between 1.8 V and VDD. To reduce the supplies needed, the VIO and VDD can be tied together. The AD7946 is independent of power supply sequencing between VIO and VDD. Additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in Figure 26, which represents PSRR over frequency. For simplified applications, the AD7946, with its low operating current, can be supplied directly using the reference circuit, as shown in Figure 28. The reference line can be driven by either: • The system power supply directly • A reference voltage with enough current output capability, such as the ADR43x • A reference buffer, such as the AD8031, that can also filter the system power supply, as shown in Figure 28. 5V 5V 10Ω 5V 10kΩ 1µF AD8031 10µF 1µF (NOTE 1) REF VDD AD7946 NOTE 1: OPTIONAL REFERENCE BUFFER AND FILTER Figure 26. PSRR vs. Frequency The AD7946 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate as shown in see Figure 27. This makes the part ideal for low sampling rate (even a few Hz) and low battery-powered applications. Figure 27. Operating Currents vs. Sampling Rate Rev Pr D | Page 16 of 27 Figure 28. Example of Application Circuit VIO Preliminary Technical Data AD7946 DIGITAL INTERFACE Though the AD7946 has a reduced number of pins, it offers flexibility in its serial interface modes. The AD7946, when in CS mode, is compatible with SPI, QSPI, digital hosts, and DSPs, e.g., Blackfin® ADSP-BF53x or ADSP219x). This interface can use either 3-wire or 4-wire. A 3-wire interface using the CNV, SCK, and SDO signals minimizes wiring connections useful, for instance, in isolated applications. A 4-wire interface using the SDI, CNV, SCK, and SDO signals allows CNV, which initiates the conversions, to be independent of the readback timing (SDI). This is useful in low jitter sampling or simultaneous sampling applications. The AD7946, when in chain mode, provides a daisy chain feature using the SDI input for cascading multiple ADCs on a single data line similar to a shift register. The mode in which the part operates depends on the SDI level when the CNV rising edge occurs. The CS mode is selected if SDI is high and the chain mode is selected if SDI is low. The SDI hold time is such that when SDI and CNV are connected together, the chain mode is always selected. In either mode, the AD7946 offers the flexibility to optionally force a start bit in front of the data bits. This start bit can be used as a BUSY signal indicator to interrupt the digital host and trigger the data reading. Otherwise, without a BUSY indicator, the user must time out the maximum conversion time prior to readback. The BUSY indicator feature is enabled as follows: • In the CS mode, if CNV or SDI is low when the ADC conversion ends (Figure 32 and Figure 36). • In the chain mode, if SCK is high during the CNV rising edge (Figure 40). Rev Pr D | Page 17 of 27 AD7946 Preliminary Technical Data CS MODE 3-Wire, No BUSY Indicator are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host also using the SCK falling edge will allow a faster reading rate provided it has an acceptable hold time. After the 14th SCK falling edge or when CNV goes high, whichever is earlier, SDO returns to high impedance. This mode is usually used when a single AD7946 is connected to an SPI compatible digital host. The connection diagram is shown in Figure 29 and the corresponding timing is given in Figure 30. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. Once a conversion is initiated, it will continue to completion irrespective of the state of CNV. For instance, it could be useful to bring CNV low to select other SPI devices, such as analog multiplexers, but CNV must be returned high before the minimum conversion time and held high until the maximum conversion time to avoid the generation of the BUSY signal indicator. When the conversion is complete, the AD7946 enters the acquisition phase and powers down. When CNV goes low, the MSB is output onto SDO. The remaining data bits CONVERT DIGITAL HOST CNV VIO SDI AD7946 DATA IN SDO SCK CLK Figure 29. CS Mode 3-Wire, No BUSY Indicator Connection Diagram (SDI High) SDI = 1 tCYC tCNVH CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL 1 2 3 12 tHSDO 14 tSCKH tDSDO tEN SDO 13 D13 D12 D11 tDIS D1 D0 Figure 30. CS Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High) Rev Pr D | Page 18 of 27 04656-PrC-008 SCK Preliminary Technical Data AD7946 CS Mode 3-Wire with BUSY Indicator powers down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host also using the SCK falling edge will allow a faster reading rate provided it has an acceptable hold time. After the optional 15th SCK falling edge, or when CNV goes high, whichever is earlier, SDO returns to high impedance. This mode is usually used when a single AD7946 is connected to an SPI compatible digital host having an interrupt input. The connection diagram is shown in Figure 31 and the corresponding timing is given in Figure 32. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. SDO is maintained in high impedance until the completion of the conversion irrespective of the state of CNV. Prior to the minimum conversion time, CNV could be used to select other SPI devices, such as analog multiplexers, but CNV must be returned low before the minimum conversion time and held low until the maximum conversion time to guarantee the generation of the BUSY signal indicator. When the conversion is complete, SDO goes from high impedance to low. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. The AD7946 then enters the acquisition phase and CONVERT VIO CNV VIO DIGITAL HOST 47kΩ SDI AD7946 DATA IN SDO SCK IRQ CLK Figure 31. CS Mode 3-Wire with BUSY Indicator Connection Diagram (SDI High) SDI = 1 tCYC tCNVH CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL 1 2 3 tHSDO 13 14 15 tSCKH tDSDO SDO tDIS D13 D12 D1 D0 Figure 32. CS Mode 3-Wire with BUSY Indicator Serial Interface Timing (SDI High) Rev Pr D | Page 19 of 27 04656-PrC-010 SCK AD7946 Preliminary Technical Data CS Mode 4-Wire, No BUSY Indicator time and held high until the maximum conversion time to avoid the generation of the BUSY signal indicator. When the conversion is complete, the AD7946 enters the acquisition phase and powers down. Each ADC result can be read by bringing low its SDI input which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK driving edges. The data is valid on both SCK edges. Although the nondriving edge can be used to capture the data, a digital host also using the SCK falling edge will allow a faster reading rate provided it has an acceptable hold time. After the 14th SCK falling edge, or when SDI goes high, whichever is earlier, SDO returns to high impedance and another AD7946 can be read. This mode is usually used when multiple AD7946s are connected to an SPI compatible digital host. A connection diagram example using two AD7946s is shown in Figure 33 and the corresponding timing is given in Figure 34. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback (if SDI and CNV are low, SDO is driven low). Prior to the minimum conversion time, SDI could be used to select other SPI devices, such as analog multiplexers, but SDI must be returned high before the minimum conversion CS2 CS1 CONVERT CNV SDI AD7946 DIGITAL HOST CNV SDO SDI SCK AD7946 SDO SCK DATA IN CLK Figure 33. CS Mode 4-Wire, No BUSY Indicator Connection Diagram tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSSDICNV SDI(CS1) tHSDICNV tSCK SDI(CS2) tSCKL 1 2 12 3 tHSDO 14 15 16 26 27 28 tSCKH tDSDO tEN SDO 13 D13 D12 D11 tDIS D1 D0 D13 D12 Figure 34. CS Mode 4-Wire, No BUSY Indicator Serial Interface Timing Rev Pr D | Page 20 of 27 D1 D0 04656-PrC-012 SCK Preliminary Technical Data AD7946 CS Mode 4-Wire with BUSY Indicator low. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. The AD7946 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCK driving edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host also using the SCK falling edge will allow a faster reading rate provided it has an acceptable hold time. After the optional 15th SCK falling edge, or SDI going high, whichever is earlier, the SDO returns to high impedance. This mode is usually used when a single AD7946 is connected to an SPI compatible digital host, which has an interrupt input, and it is desired to keep CNV, which is used to sample the analog input, independent of the signal used to select the data reading. This requirement is particularly important in applications where low jitter on CNV is desired. The connection diagram is shown in Figure 35 and the corresponding timing is given in Figure 36. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback (if SDI and CNV are low, SDO is driven low). Prior to the minimum conversion time, SDI could be used to select other SPI devices, such as analog multiplexers, but SDI must be returned low before the minimum conversion time and held low until the maximum conversion time to guarantee the generation of the BUSY signal indicator. When the conversion is complete, SDO goes from high impedance to CS1 CONVERT VIO CNV DIGITAL HOST 47kΩ SDI AD7946 DATA IN SDO SCK IRQ CLK Figure 35. CS Mode 4-Wire with BUSY Indicator Connection Diagram tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSSDICNV SDI tSCK tHSDICNV tSCKL 1 2 3 tHSDO 13 14 15 tSCKH tDSDO tDIS tEN SDO D13 D12 D1 Figure 36. CS Mode 4-Wire with BUSY Indicator Serial Interface Timing Rev Pr D | Page 21 of 27 D0 04656-PrC-014 SCK AD7946 Preliminary Technical Data Chain Mode, No BUSY Indicator onto SDO and the AD7946 enters the acquisition phase and powers down. The remaining data bits stored in the internal shift register are then clocked by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 14 × N clocks are required to readback the N ADCs. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host also using the SCK falling edge will allow a faster reading rate and, consequently more AD7946s in the chain, provided the digital host has an acceptable hold time. The maximum conversion rate may be reduced due to the total readback time. For instance, with a 5 ns digital host set-up time and 3 V interface, up to five AD7946s running at a conversion rate of 333 kSPS can be daisy-chained on a 3-wire port. This mode can be used to daisy chain multiple AD7946s on a 3wire serial interface. This feature is useful for reducing component count and wiring connections, e.g., in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using two AD7946s is shown in Figure 37 and the corresponding timing is given in Figure 38. When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion, selects the chain mode, and disables the BUSY indicator. In this mode, CNV is held high during the conversion phase and the subsequent data readback. When the conversion is complete, the MSB is output CONVERT CNV CNV SDI AD7946 SDI SDO DIGITAL HOST AD7946 A B SCK SCK DATA IN SDO CLK Figure 37. Chain Mode, No BUSY Indicator Connection Diagram SDIA = 0 tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL tSSCKCNV SCK 1 tHSCKCNV 2 3 12 13 tSSDISCK 14 15 16 DA13 DA12 26 27 28 DA1 DA0 tSCKH SDOA = SDIB DA13 DA12 DA11 DA1 DA0 DB13 DB12 DB11 DB1 DB0 tHSDO tDSDO SDOB Figure 38. Chain Mode, No BUSY Indicator Serial Interface Timing Rev Pr D | Page 22 of 27 04656-PrC-016 tHSDISC tEN Preliminary Technical Data AD7946 Chain Mode with BUSY Indicator Figure 39) SDO will be driven high. This transition on SDO can be used as a BUSY indicator to trigger the data readback controlled by the digital host. The AD7946 then enters the acquisition phase and powers down. The data bits stored in the internal shift register are then clocked out, MSB first, by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 14 × N + 1 clocks are required to readback the N ADCs. Although the rising edge can be used to capture the data, a digital host also using the SCK falling edge will allow a faster reading rate and, consequently more AD7946s in the chain, provided the digital host has an acceptable hold time. For instance, with a 5 ns digital host set-up time and 3 V interface, up to five AD7946s running at a conversion rate of 333 kSPS can be daisy-chained to a single 3-wire port. This mode can also be used to daisy chain multiple AD7946s on a 3-wire serial interface while providing a BUSY indicator. This feature is useful for reducing component count and wiring connections, e.g., in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using three AD7946s is shown in Figure 39 and the corresponding timing is given in Figure 40. When SDI and CNV are low, SDO is driven low. With SCK high, a rising edge on CNV initiates a conversion, selects the chain mode, and enables the BUSY indicator feature. In this mode, CNV is held high during the conversion phase and the subsequent data readback. When all ADCs in the chain have completed their conversions, the nearend ADC ( ADC C in CONVERT SDI CNV CNV CNV AD7946 AD7946 AD7946 SDO SDI SDI SDO A B C SCK SCK SCK DIGITAL HOST DATA IN SDO IRQ CLK Figure 39. Chain Mode with BUSY Indicator Connection Diagram tCYC CNV = SDIA ACQUISITION tCONV tACQ ACQUISITION CONVERSION tSSCKCNV SCK tSCKH 1 tHSCKCNV 2 tSSDISCK tEN SDOA = SDIB 3 4 tSCK 13 13 15 16 17 27 28 29 31 35 41 42 43 DA1 DA0 tSCKL tHSDISC DA13 DA12 DA11 DA1 DA0 DB13 DB12 DB11 DB1 DB0 DA13 DA12 DA1 DA0 DC13 DC12 DC11 DC1 DC0 DB13 DB12 DB1 DB0 DA13 DA12 SDOB = SDIC tDSDOSDI SDOC Figure 40. Chain Mode with BUSY Indicator Serial Interface Timing Rev Pr D | Page 23 of 27 04656-PrC-018 tHSDO tDSDO AD7946 Preliminary Technical Data APPLICATION HINTS LAYOUT The printed circuit board that houses the AD7946 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7946 with all its analog signals on the left side and all its digital signals on the right side eases this task. Avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7946 is used as a shield. Fast switching signals, such as CNV or clocks, should never run near analog signal paths. Crossover of digital and analog signals should be avoided At least one ground plane should be used. It could be common or split between the digital and analog section. In such a case, it should be joined underneath the AD7946s. The AD7946 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic inductances. That is done by placing the reference decoupling ceramic capacitor close to, and ideally right up against, the REF and GND pins and connect these pins with wide, low impedance traces. Figure 41. Example of Layout of the AD7946 (Top Layer) Finally, the power supply VDD and VIO of the AD7946 should be decoupled with ceramic capacitors, typically 100 nF, placed close to the AD7946 and connected using short and large traces to provide low impedance paths and reduce the effect of glitches on the power supply lines. An example of layout following these rules is shown in Figure 41 and Figure 42. EVALUATING THE AD7946’S PERFORMANCE Other recommended layouts for the AD7946 are outlined in the evaluation board for the AD7946 (EVAL-AD7946). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-CONTROL BRD2. Figure 42. Example of Layout of the AD7946 (Bottom Layer) Rev Pr D | Page 24 of 27 Preliminary Technical Data AD7946 OUTLINE DIMENSIONS 3.00 BSC 10 6 4.90 BSC 3.00 BSC 1 5 PIN 1 0.50 BSC 0.95 0.85 0.75 1.10 MAX 0.15 0.00 0.27 0.17 SEATING PLANE 0.80 0.60 0.40 8° 0° 0.23 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA Figure 43.10-Lead Micro Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters INDEX AREA 0.50 BSC 3.00 BSC SQ 1 1.50 BCS SQ PIN 1 INDICATOR 5 (BOTTOM VIEW) 6 10 0.80 0.75 0.70 SEATING PLANE 2.48 2.38 2.23 0.80 MAX 0.55 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 1.74 1.64 1.49 EXPOSED PAD TOP VIEW 0.50 0.40 0.30 PADDLE CONNECTED TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES 0.20 REF Figure 44. 10-Lead Lead Frame Chip Scale Package [ QFN (LFCSP)] 3 mm × 3 mm Body (CP-10) Dimensions shown in millimeters Rev Pr D | Page 25 of 27 AD7946 Preliminary Technical Data ORDERING GUIDE Models AD7946BRM AD7946BRMRL7 AD7946BCPWP AD7946BCPRL7 EVAL-AD7946CB1 EVAL-CONTROL BRD22 EVAL-CONTROL BRD32 1 2 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package (Option) MSOP (RM-10) MSOP (RM-10) QFN [LFCSP] (CP-10) QFN [LFCSP] (CP-10) Evaluation Board Controller Board Controller Board Transport Media, Quantity Tube, 50 Reel, 1,000 Waffle pack, 50 Reel, 1,500 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes. These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. Rev Pr D | Page 26 of 27 Brand C1E C1E C1E C1E Preliminary Technical Data AD7946 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR04656-0-8/04(PrD) Rev Pr D | Page 27 of 27