a
Low Power, Low Noise
Precision FET Op Amp
AD795
FEATURES
Low Power Replacement for Burr-Brown
OPA-111, OPA-121 Op Amps
Low Noise
2.5 V p-p max, 0.1 Hz to 10 Hz
11 nV/÷Hz max at 10 kHz
0.6 fA/÷Hz at 1 kHz
High DC Accuracy
250 V max Offset Voltage
3 V/ⴗC max Drift
1 pA max Input Bias Current
Low Power: 1.5 mA max Supply Current
CONNECTION DIAGRAMS
8-Pin SOIC (RN) Package
NC 1
8 NC
–IN 2
7 +VS
+IN 3
6 OUTPUT
–V S 4
5 NC
AD795
NC = NO CONNECT
APPLICATIONS
Low Noise Photodiode Preamps
CT Scanners
Precision l-to-V Converters
PRODUCT DESCRIPTION
The AD795 is a low noise, precision, FET input operational
amplifier. It offers both the low voltage noise and low offset drift
of a bipolar input op amp and the very low bias current of a
FET-input device. The 1014 W common-mode impedance
insures that input bias current is essentially independent of
common-mode voltage and supply voltage variations.
The AD795 is useful for many high input impedance, low noise
applications. The AD795J and AD795K are rated over the
commercial temperature range of 0∞C to +70∞C.
The AD795 is available in 8-pin SOIC.
1k
50
SAMPLE SIZE = 570
40
PERCENTAGE OF UNITS
VOLTAGE NOISE SPECTRAL DENSITY – nV/÷Hz
The AD795 has both excellent dc performance and a guaranteed and tested maximum input voltage noise. It features 1 pA
maximum input bias current and 250 mV maximum offset voltage, along with low supply current of 1.5 mA max.
Furthermore, the AD795 features a guaranteed low input noise
of 2.5 mV p-p (0.1 Hz to 10 Hz) and a 11 nV/÷Hz max noise
level at 10 kHz. The AD795 has a fully specified and tested
input offset voltage drift of only 3 mV/∞C max.
100
10
30
20
10
1
10
100
1k
FREQUENCY – Hz
10k
AD795 Voltage Noise Spectral Density
0
–5
–4
–3
–2
–1
0
1
2
3
4
5
INPUT OFFSET VOLTAGE DRIFT – mV/∞C
Typical Distribution of Average Input Offset Voltage Drift
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
AD795–SPECIFICATIONS (@ +25ⴗC and ⴞ15 V dc unless otherwise noted)
Parameter
Conditions
INPUT OFFSET VOLTAGE 1
Initial Offset
Offset
vs. Temperature
vs. Supply (PSRR)
vs. Supply (PSRR)
TMIN–TMAX
INPUT BIAS CURRENT 2
Either Input
Either Input @ TMAX =
Either Input
Offset Current
Offset Current @ TMAX =
OPEN-LOOP GAIN
Min
86
84
TMIN–TMAX
VCM = 0 V
VCM = 0 V
VCM = +10 V
VCM = 0 V
VCM = 0 V
VO = ± 10 V
RLOAD ≥ 10 kW
RLOAD ≥ 10 kW
110
100
AD795JR
Typ
Max
Units
100
300
3
110
100
500
1000
10
mV
mV
mV/∞C
dB
dB
1
23
1
0.1
2
2/3
pA
pA
pA
pA
pA
1.0
120
108
dB
dB
0.1 Hz to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
1.0
20
12
11
9
INPUT CURRENT NOISE
f = 0.1 Hz to 10 Hz
f = 1 kHz
13
0.6
fA p-p
fA/÷Hz
G = –1
VO = 20 V p-p
RLOAD = 2 kW
VOUT = 20 V p-p
RLOAD = 2 kW
1.6
MHz
16
kHz
1
V/ms
10 V Step
10 V Step
50% Overdrive
f = 1 kHz
R1 ≥ 10 kW
VO = 3 V rms
10
11
2
ms
ms
ms
–108
dB
VDIFF = ± 1 V
1012储2
1014储2.2
W储pF
W储pF
± 20
± 11
V
V
V
dB
dB
FREQUENCY RESPONSE
Unity Gain, Small Signal
Full Power Response
Slew Rate, Unity Gain
3.3
50
40
17
11
mV p-p
nV/÷Hz
nV/÷Hz
nV/÷Hz
nV/÷Hz
INPUT VOLTAGE NOISE
3
SETTLING TIME
To 0.1%
To 0.01%
Overload Recovery4
Total Harmonic
Distortion
INPUT IMPEDANCE
Differential
Common Mode
INPUT VOLTAGE RANGE
Differential5
Common-Mode Voltage
Over Max Operating Temperature
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Voltage
Current
± 10
± 10
90
86
VCM = ± 10 V
TMIN–TMAX
RLOAD ≥ 2 kW
TMIN–TMAX
VOUT = ± 10 V
Short Circuit
VS –4
VS –4
±5
POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
±4
110
100
VS –2.5
± 10
± 15
± 15
1.3
–2–
V
V
mA
mA
± 18
1.5
V
V
mA
REV. B
AD795
NOTES
1
Input offset voltage specifications are guaranteed after 5 minutes of operation at T A = +25∞C.
2
Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at T A = +25∞C. For higher temperature, the current doubles every 10∞C.
3
Gain = –1, R1 = 10 kW.
4
Defined as the time required for the amplifier’s output to return to normal operation after removal of a 50% overload from the amplifier input.
5
Defined as the maximum continuous voltage between the inputs such that neither input exceeds ± 10 V from ground.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS 1
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation2 (@ TA = +25∞C)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and –VS
Storage Temperature Range (R) . . . . . . . . . –65∞C to +125∞C
Operating Temperature Range
AD795J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0∞C to +70∞C
Model
Temperature Range
Package Option*
AD795JR
0∞C to +70∞C
RN-8
*N = Plastic mini-DIP; R = SOIC package.
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
8-Pin Small Outline Package: qJA = 155∞C/Watt
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD795 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, p roper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. B
–3–
WARNING!
ESD SENSITIVE DEVICE
AD795–Typical Performance Characteristics
20
RL = 10kW
RL = 10k W
OUTPUT VOLTAGE RANGE – ±Volts
INPUT COMMON MODE RANGE – ±Volts
20
15
+VIN
10
–VIN
5
0
0
5
15
10
15
+VOUT
10
–VOUT
5
0
20
0
5
SUPPLY VOLTAGE – ±Volts
Figure 1. Common-Mode Voltage Range vs. Supply
1.0
Vs = ±15V
0.95
25
INPUT BIAS CURRENT – pA
OUTPUT VOLTAGE SWING – Volts p-p
20
Figure 2. Output Voltage Range vs. Supply Voltage
30
20
15
10
5
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0
10
100
1k
LOAD RESISTANCE – W
10k
0
5
10
15
20
SUPPLY VOLTAGE – ±Volts
Figure 4. Input Bias Current vs. Supply
Figure 3. Output Voltage Swing vs. Load Resistance
10 –9
50
INPUT BIAS CURRENT – Amps
SAMPLE SIZE = 1058
40
PERCENTAGE OF UNITS
10
15
SUPPLY VOLTAGE – ±Volts
30
20
10
10 –10
10 –11
10 –12
10 –13
10 –14
0
0
.5
1
1.5
–60
2
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE – °C
INPUT BIAS CURRENT – pA
Figure 5. Typical Distribution of Input Bias Current
Figure 6. Input Bias Current vs. Temperature
–4–
REV. B
AD795
10–4
INPUT BIAS CURRENT – Amperes
1.00
INPUT BIAS CURRENT – pA
0.95
0.90
0.85
0.80
0.75
0.70
0.65
10–5
–IIN
10–7
10–8
10–9
10–10
10–11
10–12
10–13
10–14
0.60
–15
–10
0
–5
+5
+10
–6
+15
COMMON MODE VOLTAGE – Volts
100
15
CURRENT NOISE
7.5
VOLTAGE NOISE – mV p-p
1.0
10
CURRENT NOISE – fA/÷Hz
VOLTAGE NOISE – nV/÷Hz
10
0.1
5
–20
0
20
40
60
80
100
120
0.01
140
10
1.0
10 3
10 4
VOLTAGE NOISE (REFERRED TO INPUT) – nV/÷Hz
50
SAMPLE SIZE = 344
PERCENTAGE OF UNITS
40
f = 0.1 TO 10Hz
30
20
10
10 8
10 9
1k
100
10
1.0
1
0
1
2
0.1 TO 10Hz INPUT VOLTAGE NOISE p-p – mV
10 5
106
10 7
SOURCE RESISTANCE – W
Figure 10. Input Voltage Noise vs. Source Resistance
Figure 9. Voltage and Current Noise Spectral Density vs.
Temperature
3
10
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
Figure 11. Typical Distribution of Input Voltage Noise
REV. B
6
100
TEMPERATURE – °C
0
5
Noise Bandwidth: 0.1 to 10Hz
VOLTAGE NOISE
–40
4
3
–1
1
2
–4 –3 –2
0
DIFFERENTIAL INPUT VOLTAGE – ±Volts
1k
f = 1kHz
12.5
–5
Figure 8. Input Bias Current vs. Differential Input Voltage
Figure 7. Input Bias Current vs. Common-Mode Voltage
–60
+IIN
10–6
Figure 12. Input Voltage Noise Spectral Density
–5–
AD795
30
10
SHORT CIRCUIT CURRENT – mA
8
6
OUTPUT SWING FROM 0 TO ±V
25
– OUTPUT CURRENT
20
15
+ OUTPUT CURRENT
10
0.1%
4
0.01%
2
ERROR
0
–2
–4
0.1%
0.01%
–6
–8
5
–60
–10
–40
–20
0
20
40
60
80
100
120
3
140
4
5
6
TEMPERATURE – °C
Figure 13. Short Circuit Current Limit vs. Temperature
9
10
11
120
900
POWER SUPPLY REJECTION – dB
800
700
600
500
400
300
200
100
+PSRR
–PSRR
80
60
40
20
100
0
–15
0
–5
0
5
10
–10
INPUT COMMON MODE VOLTAGE – Volts
1
15
Figure 15. Absolute Input Error Voltage vs. Input
Common-Mode Voltage
10
100
1k
10k
100k
FREQUENCY – Hz
1M
Figure 16. Power Supply Rejection vs. Frequency
120
120
120
100
OPEN-LOOP GAIN – dB
100
80
60
40
20
100
PHASE
80
80
60
60
GAIN
40
40
20
20
0
0
–20
0
1
10
100
1k
10k
100k
FREQUENCY – Hz
1M
10
10M
Figure 17. Common-Mode Rejection vs. Frequency
10M
PHASE MARGIN – Degrees
ABSOLUTE INPUT ERROR VOLTAGE – mV
8
Figure 14. Output Swing and Error vs. Settling Time
1000
COMMON MODE REJECTION – dB
7
SETTING TIME – µs
100
1k
10k
100k
1M
–20
10M
FREQUENCY – Hz
Figure 18. Open-Loop Gain & Phase Margin vs. Frequency
–6–
REV. B
AD795
30
RL = 10kW
25
OUTPUT VOLTAGE – Volts p-p
CLOSED-LOOP OUTPUT IMPEDANCE – W
1000
100
20
15
10
5
0
1k
10k
100k
FREQUENCY – Hz
10
1.0
0.1
1M
1k
Figure 19. Large Signal Frequency Response
10k
100k
FREQUENCY – Hz
1M
10M
Figure 20. Closed-Loop Output Impedance vs. Frequency
2.0
QUIESCENT SUPPLY CURRENT – mA
–60
VIN = 3Vrms
RL = 10k
–70
THD – dB
–80
–90
–100
–110
1.5
1.0
0.5
0
–120
0
100
1k
10k
FREQUENCY – Hz
5
100k
10
15
SUPPLY VOLTAGE ± Volts
Figure 22. Quiescent Supply Current vs. Supply
Voltage Drift
Figure 21. Total Harmonic Distortion vs. Frequency
50
SAMPLE SIZE = 1419
PERCENTAGE OF UNITS
40
30
20
10
0
–500 –400 –300 –200 –100
0
100
200
300
400
500
INPUT OFFSET VOLTAGE – µV
Figure 23. Typical Distribution of Input Offset Voltage
REV. B
–7–
20
AD795
10kW
+VS 0.1mF
10kW
VIN
7
2
AD795
3
4
5ms
20V
100
90
90
10
10
CL
100pF
RL
0.1mF 10kW
0%
–VS
5V
Figure 24. Unity Gain Inverter
Figure 25. Unity Gain Inverter
Large Signal Pulse Response
+V S 0.1mF
3
4
20mV
100
100
90
90
10
10
500n s
VOUT
6
RL
0.1mF 10kW
Figure 26. Unity Gain Inverter
Small Signal Pulse Response
5ms
20V
7
AD795
VIN
500ns
VOUT
6
0%
2
10mV
100
CL
100pF
0%
0%
–V S
5V
Figure 27. Unity Gain Follower
Figure 28. Unity Gain Follower
Large Signal Pulse Response
MINIMIZING INPUT CURRENT
The AD795 is guaranteed to 1 pA max input current with ± 15
volt supply voltage at room temperature. Careful attention to
how the amplifier is used will maintain or possibly better this
performance.
The amplifier’s operating temperature should be kept as low as
possible. Like other JFET input amplifier’s, the AD795’s input
Figure 29. Unity Gain Follower
Small Signal Pulse Response
current will double for every 10∞C rise in junction temperature
(illustrated in Figure 6). On-chip power dissipation will raise the
device operating temperature, causing an increase in input
current. Reducing supply voltage to cut power dissipation will
reduce the AD795’s input current (Figure 4). Heavy output
loads can also increase chip temperature, maintaining a
minimum load resistance of 10 kW is recommended.
–8–
REV. B
AD795
CIRCUIT BOARD NOTES
The AD795 is designed for mounting on PC boards. Maintaining
picoampere resolution in those environments requires a lot of
care. Both the board and the amplifier’s package have finite
resistance. Voltage differences between the input pins and other
pins as well as PC board metal traces will cause parasitic currents
(Figure 30) larger than the AD795’s input current unless special
precautions are taken. Two methods of minimizing parasitic
leakages are guarding of the input lines and maintaining adequate
insulation resistance.
CF
RF
VE
2
+
6
AD795
IS
VOUT
3
–
IP
Figures 31 and 32 show the recommended guarding schemes
for follower and inverted topologies. Pin 1 is not connected, and
can be safely connected to the guard. The high impedance input
trace should be guarded on both edges for its entire length.
RP
CP
IP =
VS
RP
+
dCP
dT
VS+
dV S
dT
CP
VS
Figure 30. Sources of Parasitic Leakage Currents
CF
GUARD
RF
2
VOUT
3
–
1
8
2
7
3
4
TOP VIEW
("R" PACKAGE)
+
6
AD795
IS
6
5
NOTE:
ON THE "R" PACKAGE
PINS 1, 5 AND 8 ARE OPEN
AND CAN BE CONNECTED
TO ANALOG COMMON OR
TO THE DRIVEN GUARD TO
REDUCE LEAKAGE.
F
Figure 31. Guarding Scheme–lnverter
GUARD
GUARD TRACES
1
2
INPUT
TRACE
–VS
AD795
TOP VIEW
3
8
+
VS
7
–
3
6
4
5
CONNECT TO JUNCTION
OF R F AND R I, OR TO PIN 6
FOR UNITY GAIN.
AD795
2
+
6
VOUT
RF
RI
–
Figure 32. Guard Scheme–Follower
REV. B
–9–
AD795
Leakage through the bulk of the circuit board will still occur
with the guarding schemes shown in Figures 31 and 32. Standard “G10” type printed circuit board material may not have
high enough volume resistivity to hold leakages at the subpicoampere level particularly under high humidity conditions.
One option that eliminates all effects of board resistance is
shown in Figure 33. The AD795’s sensitive input pin (either
Pin 2 when connected as an inverter, or Pin 3 when connected
as a follower) is bent up and soldered directly to a Teflon*
insulated standoff. Both the signal input and feedback component leads must also be insulated from the circuit board by
Teflon standoffs or low-leakage shielded cable.
some cases, a shield placed over the resistors, or even the entire
amplifier, may be needed to minimize electrical interference
originating from other circuits. Referring to the equation in
Figure 30, this coupling can take place in either, or both, of two
different forms—coupling via time varying fields:
dV
C
dT P
or by injection of parasitic currents by changes in capacitance
due to mechanical vibration:
dCp
V
dT
INPUT PIN:
PIN 2 FOR INVERTER
OR PIN 3 FOR FOLLOWER
1
2
8
AD795
3
6
5
Both proper shielding and rigid mechanical mounting of
components help minimize error currents from both of these
sources.
INPUT SIGNAL
LEAD
AD795
7
4
*Teflon is a registered trademark of E.I. du Pont Co.
OFFSET NULLING
The circuit in Figure 34 can be used when the amplifier is used
as an inverter. This method introduces a small voltage in series
with the amplifier’s positive input terminal. The amplifier’s
input offset voltage drift with temperature is not affected.
However, variation of the power supply voltages will cause
offset shifts.
PC
BOARD
TEFLON INSULATED STANDOFF
Figure 33. Input Pin to Insulating Standoff
Contaminants such as solder flux on the board’s surface and on
the amplifier’s package can greatly reduce the insulation resistance between the input pin and those traces with supply or
signal voltages. Both the package and the board must be kept
clean and dry. An effective cleaning procedure is to first swab
the surface with high grade isopropyl alcohol, then rinse it with
deionized water and, finally, bake it at 100∞C for 1 hour. Polypropylene and polystyrene capacitors should not be subjected to
the 100∞C bake as they will be damaged at temperatures greater
than 80∞C.
RF
RI
2
+
VI
–
Other guidelines include making the circuit layout as compact
as possible and reducing the length of input lines. Keeping
circuit board components rigid and minimizing vibration will
reduce triboelectric and piezoelectric effects. All precision high
impedance circuitry requires shielding from electrical noise and
interference. For example, a ground plane should be used under
all high value (i.e., greater than 1 MW) feedback resistors. In
–10–
AD795
+
6
VOUT
3
+V S
499kW
–
499kW
100kW
200W
0.1mF
–VS
Figure 34. Alternate Offset Null Circuit for Inverter
REV. B
AD795
AC RESPONSE WITH HIGH VALUE SOURCE AND
FEEDBACK RESISTANCE
5m s
10mV
Source and feedback resistances greater than 100 kW will
magnify the effect of input capacitances (stray and inherent to
the AD795) on the ac behavior of the circuit. The effects of
common-mode and differential input capacitances should be
taken into account since the circuit’s bandwidth and stability
can be adversely affected.
100
90
10
In a follower, the source resistance, RS, and input commonmode capacitance, CS (including capacitance due to board and
capacitance inherent to the AD795), form a pole that limits
circuit bandwidth to 1/2 p RSCS. Figure 35 shows the follower
pulse response from a 1 MW source resistance with the
amplifier’s input pin isolated from the board, only the effect of
the AD795’s input common-mode capacitance is seen.
0%
Figure 37. Inverter Pulse Response with 1 MW Source and
Feedback Resistance, 1 pF Feedback Capacitance
OVERLOAD ISSUES
10mV
Driving the amplifier output beyond its linear region causes
some sticking; recovery to normal operation is within 2 ms of the
input voltage returning within the linear range.
5m s
100
90
If either input is driven below the negative supply, the amplifier’s
output will be driven high, causing a phenomenon called phase
reversal. Normal operation is resumed within 30 ms of the input
voltage returning within the linear range.
10
Figure 38 shows the AD795’s input currents versus differential
input voltage. Picoamp level input current is maintained for
differential voltages up to several hundred millivolts. This
behavior is only important if the AD795 is in an open-loop
application where substantial differential voltages are produced.
0%
Figure 35. Follower Pulse Response from 1 MW
Source Resistance
10–4
In an inverting configuration, the differential input capacitance
forms a pole in the circuit’s loop transmission. This can create
peaking in the ac response and possible instability. A feedback
capacitance can be used to stabilize the circuit. The inverter
pulse response with RF and RS equal to 1 MW, and the input pin
isolated from the board appears in Figure 36. Figure 37 shows
the response of the same circuit with a 1 pF feedback
capacitance. Typical differential input capacitance for the
AD795 is 2 pF.
10mV
INPUT BIAS CURRENT – Amperes
10–5
5m s
–IN
+IN
10–6
10–7
10–8
10–9
10–10
10–11
10–12
10–13
100
10–14
–6
90
–5
–4
–3
–2
–1
0
1
2
3
4
5
6
DIFFERENTIAL INPUT VOLTAGE – ±Volts
Figure 38. Input Bias Current vs. Differential Input Voltage
10
0%
Figure 36. Inverter Pulse Response with 1 MW Source and
Feedback Resistance
REV. B
–11–
AD795
INPUT PROTECTION
The AD795 safely handles any input voltage within the supply
voltage range. Some applications may subject the input
terminals to voltages beyond the supply voltages—in these
cases, the following guidelines should be used to maintain the
AD795’s functionality and performance.
If the inputs are driven more than a 0.5 V below the minus supply, milliamp level currents can be produced through the input
terminals. That current should be limited to 10 mA for “transient” overloads (less than 1 second) and 1 mA for continuous
overloads, this can be accomplished with a protection resistor in
the input terminal (as shown in Figures 40 and 41). The protection resistor’s Johnson noise will add to the amplifier’s input
voltage noise and impact the frequency response.
Driving the input terminals above the positive supply will cause
the input current to increase and limit at 40 mA. This condition
is maintained until 15 volts above the positive supply—any
input voltage within this range does not harm the amplifier.
Input voltage above this range causes destructive breakdown
and should be avoided.
RP
SOURCE
3
AD795
Figure 40. Follower with Input Current Limit
Figure 41 is a schematic of the AD795 as an inverter with an
input voltage clamp. Bootstrapping the clamp diodes at the
inverting input minimizes the voltage across the clamps and
keeps the leakage due to the diodes low. Low leakage diodes
(less than 1 pA), such as the FD333s should be used, and
should be shielded from light to keep photocurrents from being
generated. Even with these precautions, the diodes will measurably increase the input current and capacitance.
In order to achieve the low input bias currents of the AD795, it
is not possible to use the same on-chip protection as used in
other Analog Devices op amps. This makes the AD795
sensitive to handling and precautions should be taken to
minimize ESD exposure whenever possible.
RF
RF
CF
RP
SOURCE
6
2
SOURCE
2
AD795
2
AD795
6
6
3
3
PROTECT DIODES
(LOW LEAKAGE)
Figure 41. Input Voltage Clamp with Diodes
Figure 39. Inverter with Input Current Limit
–12–
REV. B
AD795
will typically drop by a factor of two for every 10∞C rise in
temperature. In the AD795, both the offset voltage and drift are
low, this helps minimize these errors.
10pF
10 9 W
Minimizing Noise Contributions
The noise level limits the resolution obtainable from any preamplifier. The total output voltage noise divided by the
feedback resistance of the op amp defines the minimum
detectable signal current. The minimum detectable current
divided by the photodiode sensitivity is the minimum detectable
light power.
GUARD
2
OUTPUT
AD795
PHOTODIODE
3
6
8
FILTERED
OUTPUT
Sources of noise in a typical preamp are shown in Figure 44.
The total noise contribution is defined as:
Ê
Rf
Rf Ê 1+ s (Cd ) Rd ˆ ˆ 2
Ê
ˆ2
+ (en 2 )Á1+
˜
Á
˜˜
Á
Rd Ë 1+ s (Cf ) Rf ¯ ˜¯
Ë 1+ s (Cf ) Rf ¯
Ë
OPTIONAL 26Hz
FILTER
V OUT = (in 2 + if 2 + is2 ) Á
Figure 42. The AD795 Used as a Photodiode Preamplifier
Cf
10pF
Preamplifier Applications
The low input current and offset voltage levels of the AD795
together with its low voltage noise make this amplifier an
excellent choice for preamplifiers used in sensitive photodiode
applications. In a typical preamp circuit, shown in Figure 42,
the output of the amplifier is equal to:
Rf
109 W
PHOTODIODE
en
VOUT = ID (Rf) = Rp (P) Rf
where:
ID
iS
= photodiode signal current (Amps)
Rd
iS
Cd
50pF
in
if
OUTPUT
Rp = photodiode sensitivity (Amp/Watt)
Rf = the value of the feedback resistor, in ohms.
P
= light power incident to photodiode surface, in watts.
Figure 44. Noise Contributions of Various Sources
An equivalent model for a photodiode and its dc error sources is
shown in Figure 43. The amplifier’s input current, IB, will
contribute an output voltage error which will be proportional to
the value of the feedback resistor. The offset voltage error, VOS,
will cause a “dark” current error due to the photodiode’s finite
shunt resistance, Rd. The resulting output voltage error, VE, is
equal to:
VE = (1 + Rf/Rd) VOS + Rf IB
A shunt resistance on the order of 109 ohms is typical for a
small photodiode. Resistance Rd is a junction resistance which
Cf
10pF
Rf
109 W
PHOTODIODE
Rd
ID
VOS
Cd
50pF
IB
OUTPUT
Figure 45, a spectral density versus frequency plot of each
source’s noise contribution, shows that the bandwidth of the
amplifier’s input voltage noise contribution is much greater than
its signal bandwidth. In addition, capacitance at the summing
junction results in a “peaking” of noise gain in this configuration. This effect can be substantial when large photodiodes with
large shunt capacitances are used. Capacitor Cf sets the signal
bandwidth and also limits the peak in the noise gain. Each
source’s rms or root-sum-square contribution to noise is obtained by integrating the sum of the squares of all the noise
sources and then by obtaining the square root of this sum.
Minimizing the total area under these curves will optimize the
preamplifier’s overall noise performance.
An output filter with a passband close to that of the signal can
greatly improve the preamplifier’s signal to noise ratio. The
photodiode preamplifier shown in Figure 44—without a
bandpass filter—has a total output noise of 50 mV rms. Using a
26 Hz single pole output filter, the total output noise drops to
23 mV rms, a factor of 2 improvement with no loss in signal
bandwidth.
Figure 43. A Photodiode Model Showing DC Error
Sources
REV. B
–13–
AD795
voltage contributions are also amplified by the “T” network
gain. A low noise, low offset voltage amplifier, such as the
AD795, is needed for this type of application.
OUTPUT VOLTAGE NOISE – Volts/÷ Hz
10mV
is & i f
SIGNAL BANDWIDTH
A pH Probe Buffer Amplifier
A typical pH probe requires a buffer amplifier to isolate its 106
to 109 W source resistance from external circuitry. Just such an
amplifier is shown in Figure 47. The low input current of the
AD795 allows the voltage error produced by the bias current
and electrode resistance to be minimal. The use of guarding,
shielding, high insulation resistance standoffs, and other such
standard methods used to minimize leakage are all needed to
maintain the accuracy of this circuit.
1mV
in
WITH FILTER
NO FILTER
100nV
en
en
10nV
1
10
100
1k
FREQUENCY – Hz
10k
100k
Figure 45. Voltage Noise Spectral Density of the Circuit of
Figure 44 With and Without an Output Filter
10pF
RG
10 kW
The slope of the pH probe transfer function, 50 mV per pH
unit at room temperature, has a +3300 ppm/∞C temperature
coefficient. The buffer of Figure 47 provides an output voltage
equal to 1 volt/pH unit. Temperature compensation is provided
by resistor RT which is a special temperature compensation
resistor, part number Q81, 1 kW, 1%, +3500 ppm/∞C, available
from Tel Labs Inc.
V OS ADJUST
100kW
Rf
+15V
+VS
0.1mF
Ri
1.1kW
108 W
COM
–VS
VOUT
AD795
4
VOUT
PH
PROBE
OUTPUT
5
AD795
RG
= I D Rf (1+
)
Ri
–15V
–V S
1
GUARD
3
PHOTODIODE
0.1mF
6
1VOLT/pH UNIT
7
2
19.6kW
8
+VS
Figure 46. A Photodiode Preamp Employing a “T”
Network for Added Gain
RT
1kW
+3500ppm/ ∞C
Using a “T” Network
A “T” network, shown in Figure 46, can be used to boost the
effective transimpedance of an I-to-V converter, for a given
feedback resistor value. However, amplifier noise and offset
Figure 47. A pH Probe Amplifier
–14–
REV. B
AD795
OUTLINE DIMENSIONS
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(RN-8)
Dimensions shown in millimeters and (inches)
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
8
5
1
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
SEATING
0.10
PLANE
6.20 (0.2440)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.33 (0.0130)
0.50 (0.0196)
ⴛ 45ⴗ
0.25 (0.0099)
8ⴗ
0.25 (0.0098) 0ⴗ 1.27 (0.0500)
0.41 (0.0160)
0.19 (0.0075)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
All brand or product names mentioned are trademarks or registered trademarks of their respective holders.
REV. B
–15–
AD795
Revision History
Location
Page
10/02–Data Sheet changed from REV. A to REV. B
Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to CIRCUIT BOARD NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
C00845–0–10/02(B)
Deleted Plastic Mini-DIP (N) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Edits to Figure 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Edits to OFFSET NULLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Deleted Figure 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Deleted Low Noise Op Amp Selection Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PRINTED IN U.S.A.
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
–16–
REV. B