ETC QLUS3316

QLUS3316-PT280C Device Data Sheet
• • • • • • Utopia Level 3 Slave Bridges
1.0 Utopia Level 3 (L3) Bridge Core Features
• Implements two Utopia L3 Slaves providing a solution to bridge Utopia Master devices
• Compliant with ATM-Forum af-phy-0136.000 (Utopia L3)
• Meets 90MHz performance offering more than 1.4Gbps cell rate transfers
• Single chip solution for improved system integration
• Support cell level transfer mode, single PHY
• Cell and clock rate decoupling with on chip FIFOs
• Up to 1.5 KByte of on chip FIFO per data direction
• Integrated management interface and built-in errored cell discard
• ATM Cell size programmable via external pins from 16 to 128 bytes
• Optional Utopia parity generation/checking enable/disable via external pin
• Built in JTAG port (IEEE1149 compliant)
• Simulation model available for system level verification (Contact Quicklogic for details)
• Solution also available as flexible Soft-IP core, delivered with a full device modelization
and verification testbenches
QLUS3316-PT280C Device Data Sheet
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QLUS3316-PT280C Device Data Sheet
2.0 Utopia Overview
The Utopia (Universal Test & Operations PHY Interface for ATM) interface is defined by
the ATM Forum to provide a standard interface between ATM devices and ATM PHY or
SAR (Segmentation And Re-assembly) devices.
Figure 1: Utopia Reference Model
The Utopia Standard defines a full duplex bus interface with a Master/Slave paradigm. The
Slave interface responds to the requests from the Master. The Master performs PHY
arbitration and initiates data transfers to and from the Slave device.
The ATM forum has standardized the Utopia Levels 1 (L1) to 3 (L3). Each level extends
the maximum supported interface speed from OC3, 155Mbps (L1) over OC12, 622Mbps
(L2) to 3.2Gbit/s (L3).
The following Table 1 gives an overview of the main differences in these three levels.
Table 1: Utopia Level Differences
Utopia Level
Interface Width
Max. Interface Speed
Maximum Throughput
1
8-bit
25 MHz
200 Mbps (typ. OC3 155 Mbps)
2
8-bit, 16-bit
50 MHz
800 Mbps (typ. OC12 622 Mbps)
3
8-bit, 32-bit
104 MHz
3.2 Gbps (typ. OC48 2.5 Gbps)
Utopia Level 1 implements an 8-bit interface running at up to 25MHz. Level 2 adds a 16
Bit interface and increases the speed to 50MHz. Level 3 extends the interface further by
a 32 Bit word-size and speeds up to 104MHz providing rates up to 3.2 Gbit/s over the
interface.
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QLUS3316-PT280C Device Data Sheet
In addition to the differences in throughput, Utopia Level 2 uses a shared bus offering to
physically share a single interface bus between one master and up to 31 slave devices
(Multi-PHY or MPHY operation). This allows the implementation of aggregation units that
multiplex several slave devices to a single Master device. The Level 1 and Level 3 are pointto-point only, whereas Level 1 has no notion of multiple slaves. Level 3 still has the notion
of multiple slaves, but they must be implemented in a single physical device connected to
the Utopia Interface.
3.0 Utopia Slave/Slave Bridge Application
As it is not possible to connect two Master devices together, the Slave/Slave Bridge
provides the necessary interfaces to convey between two Master devices as shown in
Figure 2.
Figure 2: Utopia Slave Bridge
The Bridge automatically transfers data as soon as it becomes available from one side to
the other. Internal asynchronous FIFOs enable independent clock domains for each
interface.
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4.0 Application
Figure 3: Slave/Slave Bridge connecting two Master Devices
Data flows from the Bridge's TX Ports to the corresponding RX Ports on the other side of
the bridge.
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QLUS3316-PT280C Device Data Sheet
5.0 Core Pinout
On the Utopia interfaces, the Core implements all the required Utopia signals and provides
all the Utopia optional signals (Indicated by an 'O' in the following tables). The optional
Utopia signals are activated during the Core configuration and inactive Utopia signals
should be left unconnected (Outputs) or tied to a zero logic level (inputs) as specified in the
following Tables.
In addition to the Utopia Interface signals, error indication signals are available for error
monitoring or statistics. An error indication always shows that a cell has been discarded by
the bridge. Possible errors are parity or cell-length errors on the receive interface of the
corresponding Utopia Interfaces.
All Utopia interfaces work in the same transfer mode (cell level). A mix is not possible.
To identify the sides of the core the notion "WEST" and "EAST" for the corresponding
interfaces will be used.
Figure 4: Utopia Level 3 Slave/Slave Bridge Top Entity
5.1 Signal Descriptions
Table 2: Global Signal
Pin
Mode
Description
reset
In
Active high chip reset
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Table 3: Device Management Interface
Pin
Mode
wtx_err
Out
Description
Transmit error indication on west interface. When driven high, indicates that an
errored cell (Wrong parity or wrong length) was received from the device
connected to the west interface and is discarded.
Transmit error status information for west interface. When wtx_err is driven,
indicates the error status of the discarded cell:
wtx_err_stat(1:0)
Out
• wtx_err_stat(0) : When set to '1' indicates that a cell is discarded because of
a parity error.
• wtx_err_stat(1) : When set to '1' indicates that a cell is discarded because it
has a wrong length (Consecutive assertion of ut_tx_soc on the Utopia
interface within less than a complete cell time).
etx_err
Out
Transmit error indication on east interface. When driven high, indicates that an
errored cell (Wrong parity or wrong length) was received from the device
connected to the east interface side.
Transmit error status information for east receive interface. When etx_err is
driven, indicates the error status of the discarded cell:
etx_err_stat(1:0)
Out
• ex_err_stat(0) : When set to '1' indicates that a cell is discarded because of
a parity error.
• etx_err_stat(1) : When set to '1' indicates that a cell is discarded because it
has a wrong length (Consecutive assertion of ut_tx_soc on the Utopia
interface within less than a complete cell time).
NOTE: wtx_.. signals are sampled with west transmit clock (wtxclk). etx_.. signals are
sampled with west receive clock (wrxclk).
Table 4: West Utopia Slave Transmit Interface
Pin
Mode
Description
wtxclk
In
90MHz transmit byte clock. The Core samples all Utopia Transmit signals on txclk
rising edge.
wtxdata[15:0]
In
Transmit data bus.
wtxprty
In
Transmit data bus parity. Standard odd or non-standard even parity can be
optionally checked by the connected Slave.
When the parity check is disabled during the Core configuration, or not used in
the design, the pin txprty should be tied to '0'.
wtxsoc
In
Transmit start of cell. Asserted by the Master to indicate that the current word is
the first word of a cell.
wtxenb
In
Active low transmit data transfer enable.
wtxclav[0]
Out
Cell buffer available. Asserted in octet level transfers to indicate to the Master that
the FIFO is almost full (Active low) or, in cell level transfers, to indicate to the
Master that the PHY port FIFO has space to accept one cell.
Out
Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status
indication is selected during the Core configuration, one txclav signal is
implemented per PHY port. The maximum number of clav signals is limited
to four.
wtxclav[3:1] (O)
wtxaddr[4:0]
In
Utopia transmit address. When the Core operates in MPHY mode, address bus
used during polling and slave port selection. Bit 4 is the MSB.
txaddr(4:0) becomes optional (And should be left open) when the Core does not
operate in MPHY mode.
NOTE: (O) indicates optional signals.
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QLUS3316-PT280C Device Data Sheet
Table 5: West Utopia Slave Receive Interface
Pin
Mode
Description
wrxclk
In
90MHz receive byte clock. The Core samples all Utopia Receive signals on rxclk
rising edge.
wrxdata[15:0]
Out
Receive data bus.
wrxprty (O)
Out
Receive data bus parity. Standard odd or non standard even parity can be
optionally generated by the Utopia Slave Core.
When the parity generation is disabled during the Core configuration, the pin
rxprty can be let unconnected.
wrxsoc
Out
Receive start of cell. Asserted to indicate that the current word is the first word of
a cell.
wrxenb
In
wrxclav[0]
Out
Cell buffer available. Asserted in octet level transfers to indicate to the Master that
the FIFO is almost empty (Active low) or, in cell level transfers, to indicate to the
Master that the PHY port FIFO has space one cell available in the FIFO.
wrxclav[3:1] (O)
Out
Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status
indication is selected, one rxclav signal is implemented per PHY port. The
maximum number of clav signals is limited to four.
wrxaddr(4:0)
In
Active low transmit data transfer enable.
Utopia receive address. When the Core operates in MPHY mode, address bus
used during polling and slave port selection. Bit 4 is the MSB.
txaddr(4:0) becomes optional (And should be left open) when the Core does not
operate in MPHY mode.
Table 6: East Utopia Slave Transmit Interface
Pin
Mode
Description
etxclk
In
90MHz transmit byte clock. The Core samples all Utopia Transmit signals on txclk
rising edge.
etxdata[15:0]
In
Transmit data bus.
etxprty
In
Transmit data bus parity. Standard odd or non-standard even parity can be
optionally checked by the connected Slave.
When the parity check is disabled during the Core configuration, or not used in
the design, the pin txprty should be left open.
etxsoc
In
Transmit start of cell. Asserted by the Master to indicate that the current word is
the first word of a cell.
etxenb
In
Active low transmit data transfer enable.
etxclav[0]
Out
Cell buffer available. Asserted in octet level transfers to indicate to the Master that
the FIFO is almost full (Active low) or, in cell level transfers, to indicate to the
Master that the PHY port FIFO has space to accept one cell.
etxclav[3:1] (O)
Out
Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status
indication is selected during the Core configuration, one txclav signal is
implemented per PHY port. The maximum number of clav signals is limited
to four.
etxaddr[4:0]
In
Utopia transmit address. When the Core operates in MPHY mode, address bus
used during polling and slave port selection. Bit 4 is the MSB.
txaddr(4:0) becomes optional (And should be left open) when the Core does not
operate in MPHY mode.
NOTE: (O) indicates optional signals.
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Table 7: East Utopia Slave Receive Interface
Pin
Mode
Description
erxclk
In
90MHz receive byte clock. The Core samples all Utopia Receive signals on rxclk
rising edge.
erxdata[15:0]
Out
Receive data bus.
erxprty (O)
Out
Receive data bus parity. Standard odd or non standard even parity can be
optionally generated by the Utopia Slave Core.
When the parity generation is disabled during the Core configuration, the pin
rxprty can be let unconnected.
erxsoc
Out
Receive start of cell. Asserted to indicate that the current word is the first word of
a cell.
erxenb
In
erxclav[0]
Out
Cell buffer available. Asserted in octet level transfers to indicate to the Master that
the FIFO is almost empty (Active low) or, in cell level transfers, to indicate to the
Master that the PHY port FIFO has space one cell available in the FIFO.
rxclav[3:1] (O)
Out
Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status
indication is selected, one rxclav signal is implemented per PHY port. The
maximum number of clav signals is limited to four.
erxaddr(4:0)
In
Active low transmit data transfer enable.
Utopia receive address. When the Core operates in MPHY mode, address bus
used during polling and slave port selection. Bit 4 is the MSB.
taddr(4:0) becomes optional (And should be left open) when the Core does not
operate in MPHY mode.
Table 8: Device Configuration Pins
Pin
Mode
Description
prty_en
In
Enable parity checking on the Utopia interface.
If disabled (tied to 0), the wrx_err_stat(0) signal can be ignored and left open and
the rx parity input should be tied to 0. Also the tx parity pins can be left open.
cellsize[7:0]
In
Define cellsize: sets the size in bytes of a cell. Binary value to be set usually by
board wiring.
The size must be a multiple of 2.
The configuration pins are not intended for change during operation. They are usually
board wired to configure the device for operation.
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QLUS3316-PT280C Device Data Sheet
6.0 Global Signal Distribution
The externally provided Utopia Transmit and Receive clocks are connected to global
resources to provide low skew and fast chip level distribution. In both data directions, the
two corresponding Utopia Interfaces are decoupled by asynchronous FIFOs.
Therefore each interface runs completely independently each at its own tx and rx clocks
which typically are up to 104 MHz on the Level 3 interface (west) and up to 50 MHz on
the Level 2 interface (east).
The Error indications of the two receive interfaces are always sampled within the west clock
domains. The errors of the east tx (receiving) interface is available on the etx_err signal,
which is handled using the west clock domain (wrxclk). The west tx (receiving) error is
directly derived from the west tx block (wtxclk).
Figure 5: Slave/Slave Bridge Clock Distribution
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QLUS3316-PT280C Device Data Sheet
7.0 Functional Description – Utopia Interface
The Utopia Bridge operates in single PHY mode. Therefore no address bus and only a
single status pin (clav[0]) per direction is used on the interfaces.
7.1 Utopia Interface Single PHY Transmit Interface
The Transmit interface is controlled by the Master.
The transmit interface has data flowing in the same direction as the ATM enable
ut_txenb. The ATM transmit block generates all output signals on the rising edge of
the ut_txclk.
Transmit data is transferred from the Master to PHY layer via the following procedure. The
Core indicates it can accept data using the ut_txclav signal, then the Master drives data
onto ut_txdat and asserts ut_txenb.
Once a cell transfer has started, the Master or the Slave device cannot pause the transfer
by any mean.
7.1.1 Cell Level Transfer
The Slave asserts ut_txclav 1 when it is capable of accepting the transfer of a whole
cell. The Master asserts ut_txenb (Low) to indicate that it drives valid data to the Slave
2. Together with the first octet of a cell, the Master asserts ut_txsoc for one clock
cycle 3.
To ensure that the Master does not cause transmit overrun, the Slave de-asserts
ut_txclav when ut_txsoc is de-asserted by the Master 4.
When a cell transfer is initiated, the Master or the Slave cannot pause the transfer by any
means.
To complete the cell transfer, the Master de-asserts the Utopia enable signal ut_txenb 5.
Figure 6: Single Cell Transfer
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QLUS3316-PT280C Device Data Sheet
7.1.2 Back to Back Cells Transfer
When, during a cell transfer, the Slave is able to receive a subsequent cell, the Master can
keep ut_txenb asserted between two cells 1 and asserts ut_txsoc, to start a new cell
transfer, immediately after the last octet of the previous cell 2.
Figure 7: Back to Back Cell Transfer
7.2 Utopia Interface Single PHY Receive Interface
The Receive interface is controlled by the Master. The receive interface has data flowing
in the opposite direction to the Master enable ut_rxenb.
Receive data is transferred from the Slave to Master via the following procedure. The Slave
indicates it has valid data, then the Master asserts ut_rxenb to read this data from the
Slave. The Slave indicates valid data (thereby controlling the data flow) via the ut_rxclav
signal.
7.2.1 Single Cell Transfer
The Slave asserts ut_rxclav when it is ready to send a complete cell to the Master device
1. The Master interface asserts ut_rxenb to start the cell transfer 2. The Slave samples
ut_rxenb and starts driving data on the following clock edge 3. The Slave asserts
ut_rxsoc together with the cell first word to indicate the start of a cell 4.
The Master drives ut_txenb high two clock cycles before the expected end of the current
cell if the Slave has no more cell to transfer 5. The Slave de-asserts ut_rxclav to indicate
that no new cell is available 6 together with the start of cell indication.
When a cell transfer is initiated, the transfer cannot be paused by the Master or the Slave.
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Figure 8: Single Cell Transfer
7.2.2 Back to Back Cell Transfer
If the Master keeps ut_rxenb asserted at the end of a cell transfer 1 and if the Slave has
a new cell to send, the Slave keeps ut_rxclav drives the new cell asserting ut_rxsoc
to indicate the start of a new cell 2.
Figure 9: Back to Back Cells Transfer
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QLUS3316-PT280C Device Data Sheet
8.0 Core Management and Error Handling
On Egress, the Core is designed to handle and report Utopia errors such as Parity error or
wrong cell length. Errored cells are discarded with an error status indication provided to the
user PHY application.
When an errored cell is received on the Utopia interface, the Core discards the complete
cell and provides a cell discard indication to the User PHY application (Signal eg_err(n)
asserted) 1 together with a cell discard status (Signal eg_err_stat(1:0)) 2.
NOTE: eg_err is routed to the corresponding wtx_err and etx_err respectively
(see Figure 4).
Figure 10: Cell Discard Indication
Table 9: Error Status Word Bit Coding
Error Status Bit
Name
Description
0
PARITY_ERR
Valid when wtx/etx_err is asserted. If set to one indicates that a
cell is discarded with a parity error decoded by the Core.
1
LENGTH_ERR
Valid when wtx/etx_err is asserted. If set to one indicates that a
cell is discarded with a cell length error detected on the Utopia
interface.
The signals are sampled on the corresponding clocks from the west interface:
• etx_... sampled with wrxclk (west receive clock)
• wtx_... sampled with wtxclk (west transmit clock)
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9.0 Complexity and Performance Summary
9.1 Timing Parameters Definition
Figure 11: Tco Timing Parameter Definition
Figure 12: Tsu Timing Parameter Definition
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QLUS3316-PT280C Device Data Sheet
Table 10: 16-Bit Utopia Interface Timing Characteristics
Parameter
typ
Max
Unit
tco
7.0
6.0
ns
tsu
2.5
1.8
ns
wrxclk
90
MHz
wtxclk
90
MHz
erxclk
90
MHz
etxclk
90
MHz
minimum reset time
50
ns
NOTE: Timing model "worst" case is used.
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10.0 Device Pinout
10.1 Signals Overview
Table 11: Signals Overview Table
Signals
Description
wrxclk, wrxclav,
wrxenb*,wrxdat, wrxsoc
West Utopia Receive Interface
wtxclk, wtxclav, wtxenb*,
wtxdata, wtxsoc
West Utopia Transmit Interface
wtx_err, wtx_err_stat
West Interface error indication (sampled with wtxclk)
.
erxclk, erxclav, erxenb*,
erxdata, erxsoc
East Utopia Receive Interface
etxclk, etxclav, etxenb*,
etxdata, etxsoc
East Utopia Transmit Interface
etx_err, etx_err_stat
prty_en, cellsize
East Interface error indication (sampled with wrxclk)
Configuration Pins to be board wired.
Cellsize [0] Should be tied to GND.
reset
Active high device reset
GND
Ground
VCC
Device Power 2.5 V
clk(x)
unused clock inputs should be tied to GND
IOCTRL(x)
VCCIO(x)
IO Power 3.3 V
INREF(x)
connect to GND
PLLRST(x)
connect to GND or VCC
PLLOUT(x)
connect to GND or VCC
VCCPLL(x)
GNDPLL(x)
TCK, TRSTB
JTAG signals. connect to GND
TMS, TDI
JTAG signals. connect to VCC
TDO
JTAG signal. leave open
iov
nc
not connected. should be left open
*: active low signal
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QLUS3316-PT280C Device Data Sheet
10.2 PT280 FPGBA Device Diagram
WEST receive error indication
device configuration
EAST receive error indication
QLUS3316
-PT280C
Figure 13: PT280 bottom view
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10.3 280 Pin FPBGA (PT280) Pinout Table
Table 12: 280 Pin FPBGA (PT280) Pinout Table
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PIN
Function
PIN
Function
PIN
Function
PIN
Function
PIN
Function
A1
pllout(3)
D1
nc
G19
wrxdat[12]
N16
nc
U6
inref(a)
A2
gndpll(0)
D2
nc
H1
nc
N17
nc
U7
nc
A3
etx_err
D3
nc
H2
nc
N18
ioctrl(c)
U8
nc
A4
etx_err_stat[0]
D4
nc
H3
nc
N19
ioctrl(c)
U9
vccio(a)
A5
etx_err_stat[1]
D5
nc
H4
nc
P1
erxdat[10]
U10
erxclk
A6
ioctrl(f)
D6
cellsize[0]
H5
vcc
P2
erxdat[11]
U11
vccio(b)
A7
wtxclav[0]
D7
prty_en
H15
vcc
P3
ioctrl(h)
U12
nc
A8
wtxprty
D8
reset
H16
vcc
P4
inref(h)
U13
etxdat[13]
A9
wtxenb
D9
clk(8)
H17
wrxdat[13]
P5
vcc
U14
ioctrl(b)
A10
wtxclk
D10
wrxclav[0]
H18
wrxdat[14]
P15
gnd
U15
vccio(b)
etxdat[5]
A11
wtxsoc
D11
wrxprty
H19
wrxdat[15]
P16
nc
U16
A12
wtxdat[0]
D12
wrxenb
J1
nc
P17
nc
U17
tdo
A13
wtxdat[1]
D13
inref(e)
J2
nc
P18
wtx_err
U18
pllrst(2)
A14
ioctrl(e)
D14
wrxsoc
J3
vccio(g)
P19
wtx_err_stat[0]
U19
etxprty
A15
wtxdat[2]
D15
wrxdat[0]
J4
nc
R1
erxdat[7]
V1
pllout(2)
gndpll(3)
A16
wtxdat[3]
D16
wrxdat[1]
J5
gnd
R2
erxdat[8]
V2
A17
wtxdat[4]
D17
wrxdat[2]
J15
vcc
R3
vccio(h)
V3
gnd
A18
pllrst(1)
D18
wrxdat[3]
J16
nc
R4
erxdat[9]
V4
erxprty
A19
gnd
D19
wrxdat[4]
J17
vccio(d)
R5
gnd
V5
erxenb
B1
pllrst(0)
E1
cellsize[3]
J18
nc
R6
gnd
V6
ioctrl(a)
B2
gnd
E2
cellsize[2]
J19
nc
R7
vcc
V7
nc
B3
wtxdat[5]
E3
vccio(g)
K1
vcc
R8
vcc
V8
nc
B4
wtxdat[6]
E4
cellsize[1]
K2
tck
R9
gnd
V9
nc
B5
wtxdat[7]
E5
gnd
K3
nc
R10
gnd
V10
clk(1)
clk(4)
B6
inref(f)
E6
vcc
K4
nc
R11
vcc
V11
B7
wtxdat[8]
E7
vcc
K5
gnd
R12
vcc
V12
nc
B8
wtxdat[9]
E8
vcc
K15
gnd
R13
vcc
V13
etxdat[14]
B9
tms
E9
vcc
K16
nc
R14
vcc
V14
inref(b)
B10
clk(6)
E10
gnd
K17
nc
R15
gnd
V15
etxdat[9]
etxdat[6]
B11
wtxdat[10]
E11
gnd
K18
nc
R16
etxdat[3]
V16
B12
wtxdat[11]
E12
vcc
K19
trstb
R17
vccio(c)
V17
etxdat[1]
B13
ioctrl(e)
E13
vcc
L1
nc
R18
etxenb
V18
gndpll(2)
B14
wtxdat[12]
E14
gnd
L2
nc
R19
wtx_err_stat[1]
V19
gnd
B15
wtxdat[13]
E15
gnd
L3
vccio(h)
T1
erxdat[2]
W1
gnd
B16
wtxdat[14]
E16
wrxdat[5]
L4
nc
T2
erxdat[3]
W2
pllrst(3)
B17
vccpll(1)
E17
vccio(d)
L5
vcc
T3
erxdat[4]
W3
nc
B18
gndpll(1)
E18
inref(d)
L15
gnd
T4
erxdat[5]
W4
nc
B19
pllout(0)
E19
ioctrl(d)
L16
nc
T5
erxdat[6]
W5
nc
C1
wtxdat[15]
F1
inref(g)
L17
vccio(c)
T6
ioctrl(a)
W6
erxclav[0]
C2
vccpll(0)
F2
ioctrl(g)
L18
nc
T7
nc
W7
nc
C3
nc
F3
cellsize[5]
L19
nc
T8
nc
W8
nc
C4
nc
F4
cellsize[4]
M1
erxdat[15]
T9
nc
W9
tdi
C5
vccio(f)
F5
gnd
M2
nc
T10
nc
W10
etxclk
C6
ioctrl(f)
F15
vcc
M3
nc
T11
clk(3)
W11
nc
C7
nc
F16
ioctrl(d)
M4
nc
T12
nc
W12
nc
C8
nc
F17
wrxdat[6]
M5
vcc
T13
etxdat[12]
W13
etxdat[15]
C9
vccio(f)
F18
wrxdat[7]
M15
vcc
T14
etxdat[11]
W14
ioctrl(b)
C10
wrxclk
F19
wrxdat[8]
M16
inref(c)
T15
etxdat[8]
W15
etxdat[10]
C11
vccio(e)
G1
nc
M17
nc
T16
etxdat[4]
W16
etxdat[7]
C12
nc
G2
cellsize[7]
M18
nc
T17
vccpll(2)
W17
etxdat[2]
C13
nc
G3
ioctrl(g)
M19
nc
T18
etxsoc
W18
etxdat[0]
W19
pllout(1)
C14
nc
G4
cellsize[6]
N1
ioctrl(h)
T19
etxclav[0]
C15
vccio(e)
G5
vcc
N2
erxdat[12]
U1
erxsoc
C16
nc
G15
vcc
N3
erxdat[13]
U2
erxdat[0]
C17
nc
G16
wrxdat[9]
N4
erxdat[14]
U3
vccpll(3)
C18
nc
G17
wrxdat[10]
N5
vcc
U4
erxdat[1]
C19
nc
G18
wrxdat[11]
N15
vcc
U5
vccio(a)
© 2001 QuickLogic Corporation
QLUS3316-PT280C Device Data Sheet
11.0 References
• ATM Forum, Utopia Level 3, af-phy-0136.000, 1999
12.0 Contact
QuickLogic Corp.
Tel
: 408 990 4000 (US)
: + 44 1932 57 9011 (Europe)
: + 49 89 930 86 170 (Germany)
: + 852 8106 9091 (Asia)
: + 81 45 470 5525 (Japan)
E-mail
: in fo@q ui ck lo gi c. co m
Internet : ww w. q ui ck l og i c . c om
QLUS3316-PT280C Device Data Sheet
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QLUS3316-PT280C Device Data Sheet
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© 2001 QuickLogic Corporation