a Dual Channel, 12-Bit, 80 MSPS A/D Converter with Analog Input Signal Conditioning AD13280 and performance while still maintaining excellent isolation, and providing for significant board area savings. FEATURES Dual, 80 MSPS Minimum Sample Rate Channel-to-Channel Matching, 1% Gain Error 90 dB Channel-to-Channel Isolation DC-Coupled Signal Conditioning 80 dB Spurious-Free Dynamic Range Selectable Bipolar Inputs (1 V and 0.5 V Ranges) Integral Single-Pole Low-Pass Nyquist Filter Two’s Complement Output Format 3.3 V Compatible Outputs 1.85 W per Channel Industrial and Military Grade Multiple options are provided for driving the analog input, including single-ended, differential, and optional series filtering. The AD13280 also offers the user a choice of analog input signal ranges to further minimize additional external signal conditioning, while still remaining general purpose. The AD13280 operates with ± 5.0 V for the analog signal conditioning with a separate 5.0 V supply for the analog-to-digital conversion, and 3.3 V digital supply for the output stage. Each channel is completely independent allowing operation with independent encode and analog inputs, and maintaining minimal crosstalk and interference. APPLICATIONS Radar Processing (Optimized for I/Q Baseband Operation) Phased Array Receivers Multichannel, Multimode Receivers GPS Antijamming Receivers Communications Receivers The AD13280 is packaged in a 68-lead ceramic gull wing package. Manufacturing is done on Analog Devices, Inc. MIL-38534 Qualified Manufacturers Line (QML) and components are available up to Class-H (–40°C to +85°C). The components are manufactured using Analog Devices, Inc. high-speed complementary bipolar process (XFCB). PRODUCT DESCRIPTION The AD13280 is a complete dual channel signal processing solution including on board amplifiers, references, ADCs, and output termination components to provide optimized system performance. The AD13280 has on-chip track-and-hold circuitry and utilizes an innovative multipass architecture to achieve 12-bit, 80 MSPS performance. The AD13280 uses innovative highdensity circuit design and laser-trimmed thin-film resistor networks to achieve exceptional channel matching, impedance control, PRODUCT HIGHLIGHTS 1. Guaranteed sample rate of 80 MSPS. 2. Input signal conditioning included; gain and impedance match. 3. Single-ended, differential, or off-module filter options. 4. Fully tested/characterized full channel performance. 5. Compatible with 14-bit (up to) 65 MSPS family. FUNCTIONAL BLOCK DIAGRAM AMP-IN-A-2 AMP-IN-B-2 AMP-IN-A-1 AMP-IN-B-1 AMP-OUT-B AMP-OUT-A A–IN B+IN AD13280 A+IN B–IN DROUTA (LSB) D0A DROUTB D1A ENC D2A TIMING D3A VREF D4A DROUT VREF DROUT D5A 12 12 D6A 9 100 OUTPUT TERMINATORS D7A D8A 3 TIMING ENC ENC ENC D11B (MSB) D10B 5 100 OUTPUT TERMINATORS D9B D8B 7 D7B D9A D10A D11A (MSB) D0B D1B D2B D3B D4B D5B (LSB) D6B REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 AD13280–SPECIFICATIONS Parameter (AVCC = +5 V, AVEE = –5 V, DVCC = +3.3 V; applies to each ADC with Front-End Amplifier unless otherwise noted.) Temp Test Level Mil Subgroup Min RESOLUTION AD13280AZ/BZ Typ Max 12 Unit Bits 1 DC ACCURACY No Missing Codes Offset Error Offset Error Channel Match Gain Error2 Gain Error Channel Match Full 25°C Full Full 25°C Full 25°C Max Min IV I VI VI I VI I VI VI 12 1 2, 3 1, 2, 3 1 2, 3 1 2 3 –2.2 –2.2 –1.0 –3 –5.0 –1.5 –3.0 –5 Guaranteed ± 1.0 ± 1.0 ± 0.1 –1.0 ± 2.0 ± 0.5 ± 1.0 ± 1.0 SINGLE-ENDED ANALOG INPUT Input Voltage Range AMP-IN-X-1 AMP-IN-X-2 Input Resistance AMP-IN-X-1 AMP-IN-X-2 Capacitance Analog Input Bandwidth3 Full Full V V Full Full 25°C Full IV IV V V DIFFERENTIAL ANALOG INPUT Analog Signal Input Range A+IN to A–IN and B+IN to B–IN 4 Input Impedance Analog Input Bandwidth Full 25°C Full V V V ENCODE INPUT (ENC, ENC)1 Differential Input Voltage Differential Input Resistance Differential Input Capacitance Full 25°C 25°C IV V V 12 SWITCHING PERFORMANCE Maximum Conversion Rate 5 Minimum Conversion Rate 5 Aperture Delay (tA) Aperture Delay Matching Aperture Uncertainty (Jitter) ENCODE Pulsewidth High at Max Conversion Rate ENCODE Pulsewidth Low at Max Conversion Rate Output Delay (tOD) Encode, Rising to Data Ready, Rising Delay Full Full 25°C 25°C 25°C 25°C 25°C Full Full VI IV V IV V IV IV V V 4, 5, 6 12 12 12 4.75 4.75 25°C Min Max 25°C Min Max 25°C Min Max I II II I II II I II II 4 6 5 4 6 5 4 6 5 67.5 64.5 67.5 67.5 64 67.5 63.5 61.5 63.5 70 25°C Min Max 25°C Min Max 25°C Min Max I II II I II II I II II 4 6 5 4 6 5 4 6 5 67 63.5 67 65 63 65 54.5 53 54.5 69 SNR1, 6 Analog Input @ 10 MHz Analog Input @ 21 MHz Analog Input @ 37 MHz SINAD1, 7 Analog Input @ 10 MHz Analog Input @ 21 MHz Analog Input @ 37 MHz –2– +2.2 +2.2 +1.0 +1 +5.0 +1.5 +3.0 +5 ± 0.5 ± 1.0 12 12 99 198 100 200 4.0 100 V V 101 202 7.0 Ω Ω pF MHz ±1 618 50 V Ω MHz 10 2.5 V p-p kΩ pF 0.4 80 20 12 % FS % FS % % FS % FS % % % 1.5 250 0.3 6.25 6.25 5 8.5 70 65 68.5 59 500 8 8 MSPS MSPS ns ps ps rms ns ns ns ns dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS REV. 0 AD13280 Temp Test Level Mil Subgroup Min 25°C Min Max 25°C Min Max 25°C Min Max I II II I II II I II II 4 6 5 4 6 5 4 6 5 75 70 75 68 67 68 56 55 56 SINGLE-ENDED ANALOG INPUT Passband Ripple to 10 MHz Passband Ripple to 25 MHz 25°C 25°C DIFFERENTIAL ANALOG INPUT Passband Ripple to 10 MHz Passband Ripple to 25 MHz Parameter SPURIOUS-FREE DYNAMIC RANGE Analog Input @ 10 MHz AD13280AZ/BZ Typ Max Unit 1, 8 80 dBFS 75 dBFS 62 dBFS V V 0.05 0.1 dB dB 25°C 25°C V V 0.3 0.82 dB dB 25°C Min Max 25°C I II II V 4 6 5 4 80 dBc 77 dBc 25°C V 4 60 dBc CHANNEL-TO-CHANNEL ISOLATION 10 25°C IV 12 TRANSIENT RESPONSE 25°C V Analog Input @ 21 MHz Analog Input @ 37 MHz TWO-TONE IMD REJECTION 9 fIN = 9.1 MHz and 10.1 MHz f1 and f2 are –7 dB fIN = 19.1 MHz and 20.7 MHz f1 and f2 are –7 dB fIN = 36 MHz and 37 MHz f1 and f2 are –7 dB DIGITAL OUTPUTS11 Logic Compatibility DVCC = 3.3 V Logic “1” Voltage Logic “0” Voltage DVCC = 5 V Logic “1” Voltage Logic “0” Voltage Output Coding POWER SUPPLY AVCC Supply Voltage12 I (AVCC) Current AVEE Supply Voltage12 I (AVEE) Current DVCC Supply Voltage12 I (DVCC) Current ICC (Total) Supply Current per Channel Power Dissipation (Total) Power Supply Rejection Ratio (PSRR) 75 71 75 90 dB 25 ns CMOS Full Full I I Full Full V V Full Full Full Full Full Full Full Full Full IV I IV I IV I I I V 1, 2, 3 1, 2, 3 2.5 DVCC – 0.2 0.2 0.5 DVCC – 0.3 0.35 Two’s Complement 4.85 1, 2, 3 –5.25 1, 2, 3 3.135 1, 2, 3 1, 2, 3 1, 2, 3 5.0 310 –5.0 38 3.3 34 369 3.72 0.01 V V V V 5.25 338 –4.75 49 3.465 46 433 4.05 V mA V mA V mA mA W % FSR/% VS NOTES 1 All ac specifications tested by driving ENCODE and ENCODE differentially. Single-ended input: AMP-IN-X-1 = 1 V p-p, AMP-IN-X-2 = GND. 2 Gain tests are performed on AMP-IN-X-1 input voltage range. 3 Full Power Bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. 4 For differential input: +IN = 1 V p-p and –IN = 1 V p-p (signals are 180 ° out of phase). For single-ended input: +IN = 2 V p-p and = –IN = GND. 5 Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%. 6 Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 80 MSPS. SNR is reported in dBFS, related back to converter full scale. 7 Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 80 MSPS. SINAD is reported in dBFS, related back to converter full scale. 8 Analog Input signal at –1 dBFS; SFDR is ratio of converter full scale to worst spur. 9 Both input tones at –7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. 10 Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B Channel. 11 Digital output logic levels: DV CC = 3.3 V, C LOAD = 10 pF. Capacitive loads > 10 pF will degrade performance. 12 Supply voltage recommended operating range. AV CC may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range AVCC = 5.0 V to 5.25 V. Specifications subject to change without notice. REV. 0 –3– AD13280 2 1 68 67 66 65 64 63 62 61 3 60 PIN 1 IDENTIFIER AV EEA 11 AV CCA 12 AGNDB 59 AV EEB 58 AV CCB AGNDA 13 ENCODEA 14 57 56 AGNDB ENCODEB ENCODEA 15 55 ENCODEB AGNDA 16 DV CCA 17 54 AGNDB DV CCB 52 D11B(MSB) 51 D10B AD13280 NC 18 53 TOP VIEW (Not to Scale) NC 19 TEST LEVEL AGNDB SHIELD AGNDB 4 5 AMP-IN-B-1 AMP-IN-B-2 AGNDA 6 B+IN AMP-OUT-B A–IN AGNDA 7 B–IN AMP-OUT-A A+IN 8 AGNDB AMP-IN-A-1 9 AGNDA 10 NOTES 1 Absolute maximum ratings are limiting values applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedance for “ES” package: θJC 2.2°C/W; θJA 24.3°C/W. D0A(LSB) 20 50 D9B D1A 21 49 D8B D2A 22 48 D7B D3A 23 47 D6B D4A 24 46 D5B D5A 25 DGNDA 26 45 D4B DGNDB 100% Production Tested. 44 DGNDB D3B D1B D2B DROUTB NC NC SHIELD DROUTA D0B(LSB) NC = NO CONNECT III Sample Tested only. D10A D11A(MSB) D7A D8A D9A II 100% Production Tested at 25°C, and sample tested at specified temperatures. AC testing done on sample basis. D6A 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 DGNDA I AMP-IN-A-2 PIN CONFIGURATION 68-Lead Ceramic Leaded Chip Carrier (ES-68C) ELECTRICAL1 AVCC Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 7 V AVEE Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V to 0 V DVCC Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 7 V Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . VEE to VCC Analog Input Current . . . . . . . . . . . . . . –10 mA to +10 mA Digital Input Voltage (ENCODE) . . . . . . . . . . . . . 0 to VCC ENCODE, ENCODE Differential Voltage . . . . . . . . 4 V max Digital Output Current . . . . . . . . . . . . . . –10 mA to +10 mA ENVIRONMENTAL2 Operating Temperature (Case) . . . . . . . . . –40°C to +85°C Maximum Junction Temperature . . . . . . . . . . . . . . . . 175°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C Storage Temperature Range (Ambient) . . –65°C to +150°C AGNDA ABSOLUTE MAXIMUM RATINGS IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested with temperature at 25°C: sample tested at temperature extremes. ORDERING GUIDE Model Temperature Range (Case) Package Description Package Option AD13280AZ AD13280AF –25°C to +85°C –25°C to +85°C ES-68C ES-68C 5962-0053001HXA AD13280/PCB –40°C to +85°C 25°C 68-Lead Ceramic Leaded Chip Carrier 68-Lead Ceramic Leaded Chip Carrier with Nonconductive Tie-Bar 68-Lead Ceramic Leaded Chip Carrier Evaluation Board with AD13280AZ CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD13280 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– ES-68C WARNING! ESD SENSITIVE DEVICE REV. 0 AD13280 PIN FUNCTION DESCRIPTIONS Pin No. Name Function 1, 35 2, 3, 9, 10, 13, 16 SHIELD AGNDA 4 5 6 7 8 11 12 14 15 17 18, 19, 37, 38 20–25, 28–33 26, 27 34 36 39–42, 45–52 43, 44 53 54, 57, 60, 61, 67, 68 A–IN A+IN AMP-OUT-A AMP-IN-A-1 AMP-IN-A-2 AVEEA AVCCA ENCODEA ENCODEA DVCCA NC D0A–D11A DGNDA DROUTA DROUTB D0B–D11B DGNDB DVCCB AGNDB 55 56 58 59 62 63 64 65 66 ENCODEB ENCODEB AVCCB AVEEB AMP-IN-B-2 AMP-IN-B-1 AMP-OUT-B B+IN B–IN Internal Ground Shield between Channels A Channel Analog Ground. A and B grounds should be connected as close to the device as possible. Inverting Differential Input (Gain = 1). Noninverting Differential Input (Gain = 1). Single-Ended Amplifier Output (Gain = 2). Analog Input for A Side ADC (Nominally ± 0.5 V). Analog Input for A Side ADC (Nominally ± 1.0 V). A Channel Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V). A Channel Analog Positive Supply Voltage (Nominally 5.0 V). Complement of Encode; Differential Input. Encode Input; Conversion Initiated on Rising Edge. A Channel Digital Positive Supply Voltage (Nominally 5.0 V/ 3.3 V). No Connect. Digital Outputs for ADC A. D0 (LSB). A Channel Digital Ground. Data Ready A Output. Data Ready B Output. Digital Outputs for ADC B. D0 (LSB). B Channel Digital Ground. B Channel Digital Positive Supply Voltage (Nominally 5.0 V/ 3.3 V). B Channel Analog Ground. A and B grounds should be connected as close to the device as possible. Encode Input; Conversion Initiated on Rising Edge. Complement of Encode; Differential Input. B Channel Analog Positive Supply Voltage (Nominally 5.0 V). B Channel Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V). Analog Input for B Side ADC (Nominally ± 1.0 V). Analog Input for B Side ADC (Nominally ± 0.5 V). Single-Ended Amplifier Output (Gain = 2). Noninverting Differential Input (Gain = 1). Inverting Differential Input (Gain = 1). REV. 0 –5– AD13280 –Typical Performance Characteristics 0 0 –20 –20 –30 –40 –40 –50 –50 –60 –60 dB dB –30 –70 3 –80 2 –90 –70 4 –110 –110 –120 –120 –130 5 10 15 20 25 30 2 –90 6 –100 0 3 –80 5 –100 –130 ENCODE = 80MSPS AIN = 10MHz (–1dBFS) SNR = 69.19dBFS SFDR = 79.55dBc –10 ENCODE = 80MSPS AIN = 5MHz (–1dBFS) SNR = 69.4dBFS SFDR = 81.9dBc –10 35 40 0 5 10 15 TPC 1. Single Tone @ 5 MHz 25 30 35 40 35 40 TPC 4. Single Tone @ 10 MHz 0 0 ENCODE = 80MSPS AIN = 18MHz (–1dBFS) SNR = 69.79dBFS SFDR = 76.81dBc –10 –20 –30 –10 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 –120 –130 –130 0 5 10 15 20 25 30 35 ENCODE = 80MSPS AIN = 37MHz (–1dBFS) SNR = 68.38dBFS SFDR = 57.81dBc –20 dB dB 20 4 FREQUENCY – MHz FREQUENCY – MHz 40 2 3 0 5 10 5 6 4 15 20 25 30 FREQUENCY – MHz FREQUENCY – MHz TPC 2. Single Tone @ 18 MHz TPC 5. Single Tone @ 37 MHz 0 0 ENCODE = 80MSPS AIN = 9MHz AND 10MHz (–7dBFS) SFDR = 82.77dBc –10 –20 –30 ENCODE = 80MSPS AIN = 19MHz AND 20MHz (–7dBFS) SFDR = 74.41dBc –10 –20 –30 –40 –40 –50 –50 –60 –60 dB dB 5 6 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 –120 –130 –130 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 FREQUENCY – MHz FREQUENCY – MHz TPC 3. Two Tone @ 9 MHz/10 MHz TPC 6. Two Tone @ 19 MHz/20 MHz –6– REV. 0 AD13280 3 3.0 ENCODE = 80MSPS DNL MAX = 0.688 CODES DNL MIN = 0.385 CODES 2.5 ENCODE = 80MSPS INL MAX = 0.562 CODES INL MIN = 0.703 CODES 2 2.0 1 LSB LSB 1.5 1.0 0.5 0 –1 0 –2 –0.5 –3 –1.0 0 512 1024 1536 2048 2560 3072 3584 4096 0 TPC 7. Differential Nonlinearity 0 ENCODE = 80MSPS ROLL-OFF = 0.0459dB –3 dBFS –4 –5 –6 –7 –8 –9 –10 1.0 3.5 6.0 8.5 11.0 13.5 16.0 18.5 21.0 23.5 26.0 FREQUENCY – MHz TPC 8. Passband Ripple to 25 MHz REV. 0 1024 1536 2048 2560 3072 TPC 9. Integral Nonlinearity –1 –2 512 –7– 3584 4096 AD13280 Minimum Conversion Rate DEFINITION OF SPECIFICATIONS Analog Bandwidth The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Maximum Conversion Rate The encode rate at which parametric testing is performed. Aperture Delay Output Propagation Delay The delay between a differential crossing of ENCODE and ENCODE command and the instant at which the analog input is sampled. The delay between a differential crossing of ENCODE and ENCODE command and the time when all output data bits are within valid logic levels. Aperture Uncertainty (Jitter) Overvoltage Recovery Time The sample-to-sample variation in aperture delay. The amount of time required for the converter to recover to 0.02% accuracy after an analog input signal of the specified percentage of full scale is reduced to midscale. Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Power Supply Rejection Ratio Differential Analog Input Voltage Range The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. May be reported in dB (i.e., degrades as signal level is lowered) or in dBFS (always related back to converter full scale). The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise-and-Distortion (SINAD) The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage from the other pin, which is 180 degrees out of phase. Peak-to-peak differential is computed by rotating the inputs phase 180 degrees and taking the peak measurement again. The difference is then computed between both peak measurements. Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. May be reported in dB (i.e., degrades as signal level is lowered) or in dBFS (always related back to converter full scale). Differential Nonlinearity The deviation of any code from an ideal 1 LSB step. Encode Pulsewidth/Duty Cycle Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic “1” state to achieve rated performance; pulsewidth low is the minimum time ENCODE pulse should be left in low state. At a given clock rate, these specs define an acceptable Encode duty cycle. Spurious-Free Dynamic Range Harmonic Distortion The ratio of the rms signal amplitude to the rms value of the worst harmonic component. The time required for the converter to achieve 0.02% accuracy when a one-half full-scale step function is applied to the analog input. Integral Nonlinearity Two-Tone Intermodulation Distortion Rejection The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. Transient Response The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” determined by a least square curve fit. The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc. tA N+3 N AIN N+1 N+2 t ENC ENC, ENC t ENCH N N+4 t ENCL N+2 N+1 N+3 N+4 t E_DR D[11:0] N–3 N–2 t OD N–1 N DRY Figure 1. Timing Diagram –8– REV. 0 AD13280 THEORY OF OPERATION AMP-IN-X-1 The AD13280 is a high-dynamic range 12-bit, 80 MHz pipeline delay (three pipelines) analog-to-digital converter. The custom analog input section provides input ranges of 1 V and 2 V p-p and input impedance configurations of 50 Ω, 100 Ω, and 200 Ω. 100 AMP-IN-X-2 TO AD8037 100 Figure 2. Single-Ended Input Stage The AD13280 employs four monolithic ADI components per channel (AD8037, AD8138, AD8031, and a custom ADC IC), along with multiple passive resistor networks and decoupling capacitors to fully integrate a complete 12-bit analog-to-digital converter. LOADS AVCC AVCC AVCC 10k AVCC 10k ENCODE ENCODE 10k 10k LOADS Figure 3. ENCODE Inputs In the single-ended input configuration the input signal is passed through a precision laser trimmed resistor divider allowing the user to externally select operation with a full-scale signal of ± 0.5 V, or ± 1.0 V by choosing the proper input terminal for the application. The result of the resistor divider is to apply a fullscale input approximately 0.4 V to the noninverting input of the internal AD8037 amplifier. The AD13280 analog input includes an AD8037 amplifier featuring an innovative architecture that maximizes the dynamic range capability on the amplifiers’ inputs and outputs. The AD8037 amplifier provides a high input impedance and gain for driving the AD8138 in a single-ended to differential amplifier configuration. The AD8138 has a –3 dB bandwidth at 300 MHz and delivers a differential signal with the lowest harmonic distortion available in a differential amplifier. The AD8138 differential outputs help balance the differential inputs to the custom ADC maximizing the performance of the device. DVCC CURRENT MIRROR DVCC VREF DR OUT CURRENT MIRROR The AD8031 provides the buffer for the internal reference analogto-digital converter. The internal reference voltage of the custom ADC is designed to track the offsets and drifts and is used to ensure matching over an extended temperature range of operation. The reference voltage is connected to the output common-mode input on the AD8138. This reference voltage sets the output common mode on the AD8138 at 2.4 V, which is the midsupply level for the ADC. The custom ADC has complementary analog input pins, AIN and AIN. Each analog input is centered at 2.4 V and should swing ± 0.55 V around this reference. Since AIN and AIN are 180 degrees out of phase, the differential analog input signal is 2.2 V peak-to-peak. Both analog inputs are buffered prior to the first track-and-hold. Figure 4. Digital Output Stage DVCC The custom ADC digital outputs drive 100 Ω series resistors (Figure 5). The result is a 12-bit parallel digital CMOS-compatible word, coded as two’s complement. CURRENT MIRROR USING THE SINGLE-ENDED INPUT DVCC VREF 100 D0–D11 CURRENT MIRROR Figure 5. Digital Output Stage REV. 0 The AD13280 has been designed with the user’s ease of operation in mind. Multiple input configurations have been included on-board to allow the user a choice of input signal levels and input impedance. The standard inputs are ± 0.5 V and 1.0 V. The user can select the input impedance of the AD13280 on any input by using the other inputs as alternate locations for the GND. The following chart summarizes the impedance options available at each input location. AMP-IN-X-1 = 100 Ω when AMP-IN-X-2 is open. AMP-IN-X-1 = 50 Ω when AMP-IN-X-2 is shorted to GND. AMP-IN-X-2 = 200 Ω when AMP-IN-X-1 is open. Each channel has two analog inputs AMP-IN-A-1 and AMPIN-A-2 or AMP-IN-B-1 and AMP-IN-B-2. Use AMP-IN-A-1 –9– AD13280 or AMP-IN-B-1 when an input of ±0.5 V full scale is desired. Use AMP-IN-A-2 or AMP-IN-B-2 when ± 1 V full scale is desired. Each channel has an AMP-OUT which must be tied to either a noninverting or inverting input of a differential amplifier with the remaining input grounded. For example, Side A, AMP-OUT-A (Pin 6) must be tied to A+IN (Pin 5) with A–IN (Pin 5) tied to ground for noninverting operation or AMP-OUT-A (Pin 6) tied to A–IN (Pin 4) with A+IN (Pin 5) tied to ground for inverting operation. If a low jitter ECL/PECL clock is available, another option is to ac-couple a differential ECL/PECL signal to the encode input pins as shown below. A device that offers excellent jitter performance is the MC100LVEL16 (or same family) from Motorola. VT 0.1F ENCODE ECL/ PECL AD13280 0.1F ENCODE USING THE DIFFERENTIAL INPUT APPLYING THE AD13280 Encoding the AD13280 The AD13280 encode signal must be a high quality, extremely low phase noise source, to prevent degradation of performance. Maintaining 12-bit accuracy at 80 MSPS places a premium on encode clock phase noise. SNR performance can easily degrade 3 dB to 4 dB with 37 MHz input signals when using a high-jitter clock source. See Analog Devices’ Application Note AN-501, “Aperture Uncertainty and ADC System Performance” for complete details. For optimum performance, the AD13280 must be clocked differentially. The encode signal is usually ac-coupled into the ENCODE and ENCODE pins via a transformer or capacitors. These pins are biased internally and require no additional bias. VT Figure 7. Differential ECL for Encode Jitter Consideration The signal-to-noise ratio (SNR) for any ADC can be predicted. When normalized to ADC codes, Equation 1 accurately predicts the SNR based on three terms. These are jitter, average DNL error, and thermal noise. Each of these terms contributes to the noise within the converter. 2 (1 + ε ) VNOISE RMS SNR = –20 × log N + (2 × π × f ANALOG × t J RMS )2 + N 2 2 1/2 = analog input frequency tJ RMS = rms jitter of the encode (rms sum of encode source and internal encode circuitry) ε = average DNL of the ADC (typically 0.50 LSB) N = Number of bits in the ADC VNOISE RMS = V rms noise referred to the analog input of the ADC (typically 5 LSB) For a 12-bit analog-to-digital converter like the AD13280, aperture jitter can greatly affect the SNR performance as the analog frequency is increased. The chart below shows a family of curves that demonstrates the expected SNR performance of the AD13280 as jitter increases. The chart is derived from the above equation. For a complete discussion of aperture jitter, please consult Analog Devices’ Application Note AN-501, “Aperture Uncertainty and ADC System Performance.” Shown below is one preferred method for clocking the AD13280. The clock source (low jitter) is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD13280 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to the other portions of the AD13280, and limits the noise presented to the ENCODE inputs. A crystal clock oscillator can also be used to drive the RF transformer if an appropriate limited resistor (typically 100 Ω) is placed in the series with the primary. 71 AIN = 5MHz 70 69 68 AIN = 10MHz 67 66 65 AIN = 20MHz 64 63 62 61 60 AIN = 37MHz ENCODE 3.2 3.4 2.6 2.8 3.0 1.4 1.6 1.8 2.0 2.2 2.4 58 AD13280 0.6 0.8 1.0 1.2 T1-4T 3.6 3.8 4.0 59 0.0 0.2 0.4 CLOCK SOURCE 0.1F 100 (1) fANALOG SNR – –dBFS Each channel of the AD13280 was designed with two optional differential inputs, A+IN, A–IN and B+IN, B–IN. The inputs provide system designers with the ability to bypass the AD8037 amplifier and drive the AD8138 directly. The AD8138 differential ADC driver can be deployed in either a single-ended or differential input configuration. The differential analog inputs have a nominal input impedance of 620 Ω and nominal fullscale input range of 1.2 V p-p. The AD8138 amplifier drives a differential filter and the custom analog-to-digital converter. The differential input configuration provides the lowest even-order harmonics and signal-to-noise (SNR) performance improvement of up to 3 dB (SNR = 73 dBFS). Exceptional care was taken in the layout of the differential input signal paths. The differential input transmission line characteristics are matched and balanced. Equal attention to system level signal paths must be provided in order to realize significant performance improvements. CLOCK JITTER – ps ENCODE HSMS2812 DIODES Figure 8. SNR vs. Jitter Figure 6. Crystal Clock Oscillator—Differential Encode –10– REV. 0 AD13280 Power Supplies LAYOUT INFORMATION Care should be taken when selecting a power source. Linear supplies are strongly recommended. Switching supplies tend to have radiated components that may be “received” by the AD13280. Each of the power supply pins should be decoupled as closely as possible to the package, using 0.1 µF chip capacitors. The schematic of the evaluation board (Figure 10) represents a typical implementation of the AD13280. The pinout of the AD13280 is very straightforward and facilitates ease of use and the implementation of high-frequency/high-resolution design practices. It is recommended that high-quality ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. All capacitors can be standard high-quality ceramic chip capacitors. The AD13280 has separate digital and analog power supply pins. The analog supplies are denoted AVCC and the digital supply pins are denoted DVCC. AVCC and DVCC should be separate power supplies because the fast digital output swings can couple switching current back into the analog supplies. Note that AVCC must be held within 5% of 5 V. The AD13280 is specified for DVCC = 3.3 V as this is a common supply for digital ASICs. Output Loading Care must be taken when designing the data receivers for the AD13280. The digital outputs drive an internal series resistor (e.g., 100 Ω) followed by a gate like 75LCX574. To minimize capacitive loading, there should be only one gate on each output pin. An example of this is shown in the evaluation board schematic shown in Figure 9. The digital outputs of the AD13280 have a constant output slew rate of 1 V/ns. A typical CMOS gate combined with a PCB trace will have a load of approximately 10 pF. Therefore, as each bit switches, 10 mA (10 pF × 1 V ÷ 1 ns) of dynamic current per bit will flow in or out of the device. A full-scale transition can cause up to 120 mA (12 bits × 10 mA/bit) of transient current through the output stages. These switching currents are confined between ground and the DVCC pin. Standard TTL gates should be avoided since they can appreciably add to the dynamic switching currents of the AD13280. It should also be noted that extra capacitive loading will increase output timing and invalidate timing specifications. Digital output timing is guaranteed with 10 pF loads. Care should be taken when placing the digital output runs. Because the digital outputs have such a high slew rate, the capacitive loading on the digital outputs should be minimized. Circuit traces for the digital outputs should be kept short and connect directly to the receiving gate. Internal circuitry buffers the outputs of the ADC through a resistor network to eliminate the need to externally isolate the device from the receiving gate. EVALUATION BOARD The AD13280 evaluation board (Figure 9) is designed to provide optimal performance for evaluation of the AD13280 analog-to-digital converter. The board encompasses everything needed to ensure the highest level of performance for evaluating the AD13280. The board requires an analog input signal, encode clock, and power supply inputs. The clock is buffered on-board to provide clocks for the latches. The digital outputs and out clocks are available at the standard 40-pin connectors J1 and J2. Power to the analog supply pins is connected via banana jacks. The analog supply powers the associated components and the analog section of the AD13280. The digital outputs of the AD13280 are powered via banana jacks with 3.3 V. Contact the factory if additional layout or applications assistance is required. Figure 9. Evaluation Board Mechanical Layout REV. 0 –11– AD13280 Bill of Materials List for Evaluation Board Qty. Component Name Ref/Des 2 1 2 10 2 4 28 74LCX16373MTD AD13280AZ ADP3330 BJACK BRES0805 BRES0805 CAP2 2 2 6 4 2 8 CAP2 H40DM IND2 MC10EL16 MC100ELT23 POLCAP2 4 6 36 RES2 RES2 RES2 12 4 4 1 SMA Standoff Screws PCB U7, U8 U1 U5, U6 BJ1–BJ10 R41, R53 R38, R39, R55, R56 C1, C2, C5–C10, C12, C16–C18, C20–C26, C28, C30–C38 C13, C27 J1, J2 L1–L6 U2, U4, U9, U11 U4, U10 C3, C4, C11, C14, C15, C19, C29, C30 R47–R50 R1, R2, R5, R7, R8, R54 R3, R4, R6, R9, R12–R15, R19–R28, R31–R36, R37, R42, R43, R44–R46 R51, R52 J3–J14 Value Description Manufacturing Part No. 25 Ω 33 kΩ 0.1 µF Latch AD13280 Regulator Banana Jacks 0805 SM Resistor 0805 SM Resistor 0805 SM Capacitor 74LCX16373MTD (Fairchild) AD13280AZ ADP3330ART-3.3RL7 108-0740-001 (Johnson Components) ERJ-6GEYJ 240V ERJ-6GEYJ 333V GRM 40X7R104K025BL 10 µF 0805 SM Capacitor 2 × 20 40 Pin Male Connector SM Inductor Clock Drivers ECL/TTL Clock Drivers Tantalum Polar Caps VJ1206U474MFXMB TSW-120-08-G-D 2743019447 MC1016EP16D SY100ELT23L T491C106M016A57280 0Ω 50 Ω 100 Ω 0805 SM Resistor 0805 SM Resistor 0805 SM Resistor ERJ-6GEY OR 00V ERJ-6GEYJ 510V ERJ-6GEYJ 101V SMA Connectors Standoff Screws (Standoff) AD13280 Eval Board (Rev. B) 142-0701-201 313-2477-016 (Johnson Components) MPMS 004 0005 PH (Building Fasteners) GS03361 0.47 µF 47 Ω –12– REV. 0 AD13280 J13 SMA E68 AGNDA J9 SMA J6 SMA E67 AGNDB E66 J8 SMA LIDA J3 SMA E50 E83 E81 E79 E78 61 AGNDB 62 AMP IN B 2 AMP OUT B AMP IN B 1 63 64 E84 65 E82 B–IN B+IN 66 E80 67 AGNDB 68 AGNDB 1 SHIELD AGNDA AGNDA 2 E76 E75 3 E73 AMP OUT A 4 E77 7 8 D8B DGNDB DGNDB –5VAB C33 0.1F AGNDB +5VAB C17 C38 0.1F 0.1F AGNDB 59 58 57 56 55 54 AGNDB ENCBB ENCB AGNDB AGNDB OUT 3.3VDB 53 52 51 50 49 48 47 46 45 44 C18 0.1F D11B C37 0.1F D10B D9B DGNDB D8B D7B D6B D5B D4B DGNDB 43 D3B 42 D4B 60 DGNDB D2B D3B D1B 41 D1B 40 39 D0B 38 NC DRAOUT NC1B DGNDA NC = NO CONNECT NC0B DGNDA 37 D5A D2B D5B D0B(LSBB) D4A NC D6B DRBOUT D7B D3A SHIELD D2A 36 26 D1A 27 DGNDA 25 D9B 35 D5A 24 D10B NC DRAOUT D4A 23 D11B(MSB) D0A(LSB) D11A(MSBA) D3A NC 34 D2A 22 +3.3VDB AD13280 D11A D1A 21 U1 +3VDA 33 DGNDA 20 AGNDB D9A D0A AGNDA D10A NC1A 19 ENCB 32 NC0A 18 AGNDB –5.2VAB ENCA D9A 17 C10 0.1F AGNDB ENCBB D10A C36 0.1F 16 AGNDB AGNDB ENCAB D7A AGNDA OUT 3.3VDA 15 AGNDB E86 AGNDB 30 ENCA AGNDA E85 AGNDA D7A ENCAB 14 E54 E52 +5VAB 29 AGNDA AGNDB J7 SMA +5VAA D6A 13 –5VAA DGNDA 12 28 11 AGNDA D6A AGNDA 10 AMP IN A 1 AGNDA AGNDA –5VAA C9 0.1F AGNDA +5VAA C34 C35 0.1F 0.1F AMP IN A 2 9 AGNDA D8A AGNDA E70 6 E72 E69 A–IN E49 A+IN E51 AGNDA 5 E74 E71 E53 31 J4 SMA D8A AGNDA J14 SMA DRBOUT E56 E55 LIDB E65 E48 DGNDA BJ10 1 C29 10F L1 U7 C62 0.1F DGNDB +3VAA 47 20% @100MHz BJ6 47 20% @100MHz +3VDA E40 DUT 3.3VDA 1 C3 10F –5VAA 47 BJ2 20%@100MHz +5VAA L3 U1 C20 0.1F –5VAA L5 U1 C32 0.1F AGNDA AGNDA AGNDA 1 C11 10F AGNDA DGNDA 47 20% @100MHz +3VDB BJ9 1 C30 10F +5VAB 47 20%@100MHz BJ5 DUT 3.3VDB U8 C16 0.1F DGNDB L2 1 C4 10F AGNDB –5VAB 47 20%@100MHz BJ1 +5VAB L4 U1 C21 0.1F AGNDB Figure 10a. Evaluation Board REV. 0 –13– 1 C19 10F AGNDB –5VAB L6 U1 C31 0.1F AGNDB AD13280 U8 25 26 R48 0 DGNDA NC0A NC1A DGNDA DUT 3.3VDA LSB D0A D1A DGNDA D2A D3A D4A D5A DGNDA D6A D7A DUT 3.3VDA D8A D9A DGNDA D10A MSB D11A R7 50 27 28 LE2 OE2 115 O15 114 O14 GND GND 113 29 112 30 VCC 31 111 32 110 33 GND 34 19 35 18 36 17 37 16 38 GND 39 15 40 14 41 VCC 42 13 43 12 44 GND 45 11 46 10 47 LE1 48 24 DGNDA R17, DNI 23 22 21 O13 20 O12 19 VCC 18 O11 17 O10 16 GND 15 O9 14 O8 13 O7 12 O6 11 GND 10 O5 9 O4 8 VCC 7 O3 6 O2 5 GND 4 O1 3 O0 2 OE1 1 F0A F1A DGNDA R40, DNI R44, DNI F2A F3A DUT 3.3VDA R45, 100 DGNDA R46, 100 R15, 100 R14, 100 R13, 100 R15, 100 DGNDA B0A (LSB) B1A B2A B3A B4A B5A R24, 100 R23, 100 B6A B7A DUT 3.3VDA R22, 100 R21, 100 DGNDA H40DM J1 R18, DNI R20, 100 R19, 100 B8A B9A 1 2 3 4 5 6 40 39 38 37 36 35 7 B6A 8 B5A 9 R5 E61 50 B4A 10 11 E59 E60 12 B3A 13 B2A 14 B1A 15 LSB B0A 16 F3A 17 F2A 18 F1A 19 F0A 20 DGNDA 34 33 32 31 30 29 3.3VDA MSB B11A B10A C15 10F B9A B8A B7A DGNDA BUFLATA DRAOUT R47 0 28 27 26 25 24 23 22 21 DGNDA B10A B11A (MSB) DGNDA LATCHA 74LCX16374 E58 U7 25 26 R50 0 DGNDB NC0B NC1B DGNDB DUT 3.3VDB LSB D0B D1B DGNDB D2B D3B D4B D5B DGNDB D6B D7B DUT 3.3VDB D8B D9B DGNDB D10B MSB D11B R8 50 27 28 LE2 OE2 115 O15 114 O14 GND GND 113 29 112 30 VCC 31 111 32 110 33 GND 34 19 35 18 36 17 37 16 38 GND 39 15 40 14 41 VCC 42 13 43 12 44 GND 45 11 46 10 47 LE1 48 24 DGNDB R10, DNI 23 22 21 O13 20 O12 19 VCC 18 O11 17 O10 16 GND 15 O9 14 O8 13 O7 12 O6 11 GND 10 O5 9 O4 8 VCC 7 O3 6 O2 5 GND 4 O1 3 O0 2 OE1 1 F0B F1B DGNDB R30, DNI R29, DNI F2B F3B DUT 3.3VDB R28, 100 DGNDB R27, 100 R26, 100 R12, 100 R9, 100 B0B (LSB) B3B B6B B7B DUT 3.3VDB R34, 100 R33, 100 DGNDB R32, 100 R31, 100 MSB B11B B10B C14 10F B9B B8B B7B DGNDB B8B B9B B10B R2 50 E64 B2B R36, 100 R35, 100 3.3VDB B1B B4B R25, 100 B5B DGNDB J2 H40DN R11, DNI E63 B6B B5B B4B E62 BUFLATB DRAOUT R49 0 B3B B2B B1B LSB B0B F3B F2B F1B F0B DGNDB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 DGNDB B11B (MSB) DGNDB LATCHB 74LCX16374 E57 Figure 10b. Evaluation Board –14– REV. 0 AD13280 U5 ERR OUT 1 ADP3330 2 +5VAA 5 NR 3 IN 5 SD GND 4 AGNDA J5 ENCODE SMA 1 C1 0.1F 2 D QB VEE R42 100 BJ4 6 ENCA 5 2 NC D VCC U3 3 DB 4 VBB Q QB DGNDB 1 AGNDA DGNDB BJ8 R3 100 +3.3VDA DGNDA 1 6 2 3 R4 100 DGNDA DGND C5 0.47F 7 MC10EL16 NC = NO CONNECT BJ7 1 5 VEE AGNDA 1 C8 0.1F R43 100 C6 0.47F 8 AGNDB 1 ENCAB AGNDA 1 BJ3 C7 0.1F +3.3VA 7 R56 33k DGNDA R55 33k AGNDA Q U2 8 MC10EL16 NC = NO CONNECT C2 0.1F R41 25 VCC AGNDA AGNDA J12 SMA NC 3 DB 4 VBB R1 50 AGNDA AGNDA C13 0.47F 4 NC VCC D Q0 U4 Q1 DB VBB VEE DGNDA 8 E15 E7 +3.3VDA LATCHA E23 7 6 E19 BUFLATA 5 DGNDA DGNDB E11 E39 DGNDA DGNDA MC100EPT23 NC = NO CONNECT DGNDA 3 ERR OUT 1 ADP3330 2 IN U6 +5VAB 5 SD GND 4 AGNDB AGNDB J10 ENCODE SMA 1 C22 0.1F 2 3 R54 50 AGNDB 4 D DB Q QB VBB VEE 2 NC VCC C24 0.1F +3.3VB 7 6 ENCB C28 0.1F R51 100 AGNDA DGNDB C25 0.47F DGNDB 8 R37 100 +3.3VDB 7 D Q U9 6 3 DB QB 4 5 VBB VEE MC10EL16 NC = NO CONNECT C26 0.1F 1 2 R6 100 DGNDB DGNDB 3 4 NC D VCC U10 DB VBB Q0 Q1 VEE 8 +3.3VDA LATCHB E24 6 E22 BUFLATB 5 MC100EPT23 NC = NO CONNECT –15– DGNDB 7 Figure 10c. Evaluation Board REV. 0 AGNDA E38 E29 E1 E36 E14 E45 E3 ENCBB 5 E18 E28 E26 E20 E31 E43 E41 E9 E34 E5 DGNDA R38 33k DGNDB R39 33k 1 AGNDB VCC U11 MC10EL16 NC = NO CONNECT C23 0.1F R53 25 NC 8 AGNDB AGNDB J11 SMA R52 100 C27 0.47F E8 E47 DGNDB E17 E27 E25 E21 E32 E44 E42 E10 E33 E6 5 NR E16 E12 DGNDB E37 E30 E2 E35 E13 E46 E4 AGNDB SO1 SO2 SO3 SO4 SO5 SO6 AD13280 Figure 11a. Top Silk Figure 11b. Top Layer –16– REV. 0 AD13280 Figure 11c. GND1 Figure 11d. GND2 REV. 0 –17– AD13280 Figure 11e. Bottom Silk Figure 11f. Bottom Layer –18– REV. 0 AD13280 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 68-Lead Ceramic Leaded Chip Carrier (ES-68C) 0.010 (0.25) 0.008 (0.20) 0.007 (0.18) 0.235 (5.97) MAX 0.960 (24.38) 0.950 (24.13) SQ 0.940 (23.88) 60 44 61 1.070 (27.18) MIN 43 PIN 1 0.800 (20.32) BSC 1.190 (30.23) 1.180 (29.97) SQ 1.170 (29.72) TOP VIEW (PINS DOWN) 9 27 10 0.060 (1.52) 0.050 (1.27) 0.040 (1.02) DETAIL A 0.175 (4.45) MAX REV. 0 26 0.055 (1.40) 0.050 (1.27) 0.045 (1.14) –19– 0.020 (0.508) 0.017 (0.432) 0.014 (0.356) AD13280 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 68-Lead Ceramic Leaded Chip Carrier With Non-Conductive Tie-Bar (ES-68C) 0.350 (8.89) TYP C02386–2.5–4/01(0) 0.960 (24.38) 0.950 (24.13) SQ 0.940 (23.88) 0.015 (0.3) 45 3 PLS PIN 1 2.000 (8.89) TYP 0.055 (1.40) 0.050 (1.27) 0.045 (1.14) TOP VIEW (PINS DOWN) 0.020 (0.508) 0.017 (0.432) 0.014 (0.356) 0.040 (1.02) 45 0.040 (1.02) R TYP 0.800 (20.32) BSC 0.175 (4.45) MAX 0.235 (5.97) MAX DETAIL A 0.010 (0.25) 0.008 (0.20) 0.007 (0.18) 0.010 (0.254) 30 0.050 (1.27) 0.020 (0.508) PRINTED IN U.S.A. DETAIL A –20– REV. 0