ETC RH1020

v3.0
Radiation-Hardened FPGAs
Fe a t ur es
• Non-Volatile, User Programmable Devices
• Guaranteed Total Dose Radiation Capability
• Fabricated in 0.8µ Epitaxial Bulk CMOS Process
• Low Single Event Upset Susceptibility
• High Dose Rate Survivability
• Unique In-System Diagnostic and Verification Capability
with Silicon Explorer
• Latch-Up Immunity Guaranteed
G en er al D e sc r i p t i on
• QML Qualified Devices
Actel Corporation, the leader in antifuse-based field
programmable gate arrays (FPGAs), offers fully guaranteed
RadHard versions of the A1280 and A1020 devices with gate
densities of 8,000 and 2,000 gate array gates, respectively.
• Commercial Devices Available for Prototyping and
Pre-Production Requirements
• Gate Capacities of 2,000 and 8,000 Gate Array Gates
• More Design Flexibility than Custom ASICs
• Significantly Greater Densities than Discrete Logic
Devices
• Replaces up to 200 TTL Packages
• Design Library with over 500 Macro Functions
• Single-Module Sequential Functions
• Wide-Input Combinatorial Functions
• Up to Two High-Speed, Low-Skew Clock Networks
• Two In-Circuit Diagnostic Probe Pins Support Speed
Analysis to 50 MHz
The RH1020 and RH1280 devices are processed in 0.8µ,
two-level metal epitaxial bulk CMOS technology. The devices
are based on Actel’s patented channeled array architecture,
and employ Actel’s PLICE antifuse technology. This
architecture offers gate array flexibility, high performance,
and fast design implementation through user programming.
Actel devices also provide unique on-chip diagnostic probe
capabilities, allowing convenient testing and debugging.
On-chip clock drivers with hard-wired distribution networks
provide efficient clock distribution with minimum skew. A
security fuse may be programmed to disable all further
programming, and to protect the design from being copied or
reverse engineered.
Pr od uc t F am i l y P r o f i l e
Device
RH1020
RH1280
3,000
2,000
6,000
50
20
12,000
8,000
20,000
200
80
Logic Modules
S-Modules
C-Modules
547
0
547
1,232
624
608
Flip-Flops (Maximum)
273
998
22
13
186,000
35
15
750,000
User I/Os (Maximum)
69
140
Packages (by Pin Count)
Ceramic Quad Flat Pack (CQFP)
84
172
Capacity
System Gates
Gate Array Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Packages
20-Pin PAL Equivalent Packages
Routing Resources
Horizontal Tracks/Channel
Vertical Tracks/Channel
PLICE Antifuse Elements
J an u a r y 2 0 0 0
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© 2000 Actel Corporation
1
The RH1020 and RH1280 are available as fully qualified QML
devices. Unlike traditional ASIC devices, the design does not
have to be finalized six months prior to receiving the devices.
Customers can make design modifications and program new
devices within hours. These devices are fabricated,
assembled, and tested at the Lockheed-Martin Space and
Electronics facility in Manassas, Virginia on an optimized
radiation-hardened CMOS process.
R ad i at i on Su r v i v a bi l i t y
In addition to all electrical limits, all radiation characteristics
are tested and guaranteed, reducing overall system-level
risks. With total dose hardness of 300Krad(Si), latch-up
immunity, and a tested single event upset (SEU) of less than
1x10–6 errors/bit-day, these are the only RadHard,
high-density field programmable products available today.
Q M L Q u al i f i c a t i on
Lockheed Martin Space and Electronics in Manassas, Virginia
has achieved full QML certification, assuring that quality
management, procedures, processes, and controls are in
place from wafer fabrication through final test. QML
qualification means that quality is built into the production
process rather than verified at the end of the line by
expensive and destructive testing. QML also ensures
continuous process improvement, a focus on enhanced quality
and reliability, and shortened product introduction and cycle
time.
Actel Corporation has also achieved QML certification. All
RH1020 and RH1280 devices will be shipped with a “QML”
marking, signifying that the devices and processes have been
reviewed and approved by DESC for QML status.
In addition, the RadHard devices contain ActionProbe
circuitry that provides built-in access to every node in a
design, enabling 100 percent real-time observation and
analysis of a device’s internal logic nodes without design
iteration. The probe circuitry is accessed by Silicon Explorer,
an easy to use integrated verification and logic analysis tool
that can sample data at 100 MHz (asynchronous) or 66 MHz
(synchronous). Silicon Explorer attaches to a PC’s standard
COM port, turning the PC into a fully functional 18 channel
logic analyzer. Silicon Explorer allows designers to complete
the design verification process at their desks and reduces
verification time from several hours per cycle to a few
seconds.
A pp l i c at i on s
The RH1020 and RH1280 devices are targeted for use in
military and space applications subject to radiation effects.
1.
With the significant increase in Earth-orbiting satellite
launches and the ever-decreasing time-to-launch design
cycles, the RH1020 and RH1280 devices offer the best
combination of total dose radiation hardness and quick
design implementation necessary for this increasingly
competitive industry. In addition, the high total dose
capability allows the use of these devices for deep space
probes, which encounter other planetary bodies where
the total dose radiation effects are more pronounced.
2.
2
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Single Event Effects (SEE)
Many space applications are more concerned with the
number of single event upsets and potential for latch-up
in space. The RH1020 and RH1280 devices are latch-up
immune, guaranteeing that no latch-up failures will
occur. Single event upsets can occur in these devices as
with all semiconductor products, but the rate of upset is
low, as shown in the RadHard Radiation specifications
table on page 7.
D ev el o pm e n t T oo l S up po r t
The RadHard devices are fully supported by Actel’s line of
FPGA development tools, including the Actel DeskTOP series
and Designer Advantage tools. The Actel DeskTOP Series is
an integrated design environment for PCs that includes
design entry, simulation, synthesis, and place and route tools.
Designer Advantage is Actel’s suite of FPGA development
point tools for PCs and Workstations that includes the
ACTgen Macro Builder, Designer with DirectTime timing
driven place and route and analysis tools, and device
programming software.
Accumulated Total Dose Effects
3.
High Dose Rate Survivability
An additional radiation concern is high dose rate
survivability. Solar flares and sudden nuclear events
can cause immediate high levels of radiation. The
RadHard devices are appropriate for use in these types
of
applications,
including
missile
systems,
ground-based communication systems, and orbiting
satellites.
R a d ia t io n -H a r d e n e d F PG A s
O r d e r i n g I nf o r m a t i o n
RH1280
–
CQ
172
V
Application
V = QML Qualified
Package Lead Count
Package Type
CQ = Ceramic Quad Flat Pack
Part Number
RH1280 = 8000 Gates
RH1020 = 2000 Gates
C er a m i c De v i ce R es ou r c es
CQFP 84-pin
CQFP 172-pin
RH1020
69
—
RH1280
—
140
A0
B0
S0
D00
D01
R ad H ar d A r c hi t e c t ur e
The RH1020 and RH1280 architecture is composed of
fine-grained building blocks that produce fast and efficient
logic designs. All the devices are composed of logic modules,
routing resources, clock networks, and I/O modules, which
are the building blocks for fast logic designs.
Y
D10
D11
A1
B1
S1
Logi c Modul es
RH1280 devices contain two types of logic modules,
combinatorial (C-modules) and sequential (S-modules).
RH1020 devices contain only C-modules.
The C-module, shown in Figure 1, implements the following
function:
Y=!S1*!S0*D00+!S1*S0*D01+S1*!S0*D10+S1*S0*D11
Figure 1 • C-Module Implementation
C-modules. For details see the Radiation Specifications table
on page 7 and the Design Techniques for RadHard Field
Programmable Gate Arrays application note at
http://www.actel.com/appnotes.
where:
Th e RH 1 02 0 Lo gi c M o du l e
S0=A0*B0
The RH1020 logic module is an 8-input, one-output logic
circuit chosen for the wide range of functions it implements
and for its efficient use of interconnect routing resources
(Figure 3 on page 4).
S1=A1+B1
The S-module, shown in Figure 2 on page 4, is designed to
implement high-speed sequential functions within a single
logic module. The S-module implements the same
combinatorial logic function as the C-module while adding a
sequential element. The sequential element can be
configured as either a D flip-flop or a transparent latch. To
increase flexibility, the S-module register can be by-passed so
it implements purely combinatorial logic.
Flip-flops can also be created using two C-modules. The single
event upset (SEU) characteristics differ between an
S-module flip-flop and a flip-flop created using two
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The logic module can implement the four basic logic
functions (NAND, AND, OR, and NOR) in gates of two, three,
or four inputs. Each function may have many versions, with
different combinations of active-low inputs. The logic module
can also implement a variety of D-latches, exclusivity
functions, AND-ORs, and OR-ANDs. No dedicated hardwired
latches or flip-flops are required in the array, since latches
and flip-flops may be constructed from logic modules
wherever needed in the application.
3
D00
D00
D01
Y
D10
D
S0
D11
S1
Q
OUT
D01
D11
S1
CLR
Up to 7-Input Function Plus D-Type Flip-Flop with Clear
Y
D10
S0
D
Q
OUT
GATE
Up to 7-Input Function Plus Latch
D00
D0
D01
Y
D1
S
D
Q
OUT
OUT
D10
D11
S1
GATE
CLR
Up to 4-Input Function Plus Latch with Clear
Y
S0
Up to 8-Input Function (Same as C-Module)
Figure 2 • S-Module Implementation
I / O Modu les
I/O modules provide the interface between the device pins
and the logic array. A variety of user functions, determined by
a library macro selection, can be implemented in the I/O
modules (refer to the Macro Library Guide for more
information). I/O modules contain a tri-state buffer, and input
and output latches which can be configured for input, output,
or bi-directional pins (Figure 4 on page 5).
RadHard devices contain flexible I/O structures in that each
output pin has a dedicated output enable control. The I/O
module can be used to latch input and/or output data,
providing a fast set-up time. In addition, the Actel Designer
Series software tools can build a D flip-flop, using a C-module,
to register input and/or output signals.
Actel’s Designer Series development tools provide a design
library of I/O macros that can implement all I/O
configurations supported by the RadHard FPGAs.
R out ing S t ruc tu re
Figure 3 • RH1020 Logic Module
4
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The RadHard device architecture uses vertical and horizontal
routing tracks to interconnect the various logic and I/O
modules. These routing tracks are metal interconnects that
may either be of continuous length or broken into segments.
R a d ia t io n -H a r d e n e d F PG A s
Vertical Routing
EN
Q
D
PAD
From Array
G/CLK*
Q
D
To Array
Another set of routing tracks run vertically through the
module. There are three types of vertical tracks, input,
output, and long, that can be divided into one or more
segments. Each segment in an input track is dedicated to the
input of a particular module. Each segment in an output track
is dedicated to the output of a particular module. Long
segments are uncommitted and can be assigned during
routing. Each output segment spans four channels (two above
and two below), except near the top and bottom of the array
where edge effects occur. Long vertical tracks contain either
one or two segments. An example of vertical routing tracks
and segments is shown in Figure 5.
G/CLK*
* Can be configured as a Latch or D Flip-Flop
(Using C-Module)
Segmented
Horizontal
Routing
Tracks
Figure 4 • I/O Module
Varying segment lengths allow over 90 percent of the circuit
interconnects to be made with only two antifuse connections.
Segments can be joined together at the ends, using antifuses
to increase their length up to the full length of the track. All
interconnects can be accomplished with a maximum of four
antifuses.
Horizontal Routing
Horizontal channels are located between the rows of
modules, and are composed of several routing tracks. The
horizontal routing tracks within the channel are divided into
one or more segments. The minimum horizontal segment
length is the width of a module-pair, and the maximum
horizontal segment length is the full length of the channel.
Any segment that spans more than one-third the row length is
considered a long horizontal segment. A typical channel is
shown in Figure 5. Non-dedicated horizontal routing tracks
are used to route signal nets. Dedicated routing tracks are
used for the global clock networks and for power and ground
tie-off tracks.
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Logic
Modules
Antifuses
Vertical Routing Tracks
Figure 5 • Routing Structure
Antifuse Structures
An antifuse is a “normally open” structure as opposed to the
normally closed fuse structure used in PROMs or PALs. The
use of antifuses to implement a programmable logic device
results in highly testable structures, as well as efficient
programming algorithms. The structure is highly testable
because there are no pre-existing connections, enabling
temporary connections to be made using pass transistors.
These temporary connections can isolate individual antifuses
to be programmed, as well as isolate individual circuit
structures to be tested. This can be done both before and
after programming. For example, all metal tracks can be
tested for continuity and shorts between adjacent tracks, and
the functionality of all logic modules can be verified.
5
Q M L F l ow
Test Inspection
Method
Wafer Lot Acceptance
LMFS Procedure MAN-STC-Q014
Serialization
Required—100%
Die Adhesion Test
2027 (Stud Pull)
Bond Pull Test
2011 (Wirebond)
Internal Visual
2010, Condition A
Temperature Cycle
1010, Condition C, 50 Cycles
Constant Acceleration
2001, Condition D or E, Y1 Orientation Only
Particle Impact Noise Detection (PIND)
2020, Condition A
X-Ray Radiography
2012
Pre Burn-In Electrical Parameters (T0)
Per Device Specification
Dynamic Burn-In
1015, 240 Hour Minimum, 125°C
Interim Electrical Parameters (T1)
Per Device Specification
Percent Defective Allowable (PDA)
LMFS Procedure MAN-STC-Q016
Static Burn-In
1015, 144 Hour Minimum, 125°C Minimum
Final Electrical Parameters (T2)
Per Device Specification
Percent Defective Allowable (PDA)
LMFS Procedure MAN-STC-Q016
Seal—Fine/Gross Leak
1014
External Visual (as required)
2009
A bs ol u t e M ax i m u m Ra t i n gs 1
R ec o m m en d ed O pe r a t i ng C on d i t i o ns
Fr ee Ai r T e mp er at u re Ran ge
Parameter
Symbol
VCC
Parameter
DC Supply Voltage
Limits
2,3,4
Units
°C
±10
%VCC
Power Supply Tolerance
Notes:
1. Case temperature (TC) is used.
2. All power supplies must be in the recommended operating range.
For more information, refer to the Power-Up Design Considerations
application note at http://www.actel.com/appnotes.
–0.5 to VCC +0.5
V
VO
Output Voltage
–0.5 to VCC +0.5
V
IIO
I/O Source/Sink
Current5
±20
mA
–65 to +150
°C
Notes:
1. Stresses beyond those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may
affect device reliability. Devices should not be operated outside
the recommended operating conditions.
2. VPP = VCC , except during device operation.
3. VSV = VCC , except during device operation.
4. VKS = GND , except during device operation.
5. Device inputs are normally high impedance and draw
extremely low current. However, when input voltage is greater
than VCC + 0.5V or less than GND – 0.5V, the internal protection
diode will be forward-biased and can draw excessive current.
6
–55 to +125
V
Input Voltage
Storage Temperature
2
Units
–0.5 to +7.0
VI
TSTG
Temperature Range1
Military
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R a d ia t io n -H a r d e n e d F PG A s
El e c t r i c al S p ec i f i c at i o n s
Limits
Symbol
Min.
(IOH = –4 mA)
1, 2, 3
3.7
(IOL = 4 mA)
1, 2, 3
Test Conditions
VOH1
VOL
Group A
Subgroups
1
VIH
VIL
Input Transition Time tR, tF
Max.
Units
V
0.4
V
1, 2, 3
2.2
VCC + 0.3
V
1, 2, 3
–0.3
0.8
V
—
500
ns
4
20
pF
2
2
CIO, I/O Capacitance
IIH, IIL
VIN = VCC or GND
VCC = 5.5V
1, 2, 3
–10
10
µA
IOZL, IOZH
VOUT = VCC or GND
VCC = 5.5V
1, 2, 3
–10
10
µA
25
mA
ICC Standby3
1, 2, 3
Notes:
1. Only one output tested at a time. VCC = min.
2. Not tested, for information only.
3. All outputs unloaded. All inputs = VCC or GND.
R ad i at i on Sp e ci f i c a t i o ns 1 ,
Symbol
RTD
2
Characteristics
Conditions
Min.
Total Dose
Max.
Units
300K
Rad(Si)
Single Event Latch-Up
–55°C ≤ Tcase ≤ 125°C
0
3
Single Event Upset for S-modules
–55°C ≤ Tcase ≤ 125°C
1E-6
Upsets/Bit-Day
3
SEU2
Single Event Upset for C-modules
–55°C ≤ Tcase ≤ 125°C
1E-7
Upsets/Bit-Day
SEU33
Single Event Fuse Rupture
–55°C ≤ Tcase ≤ 125°C
<1
RNF
Neutron Fluence
SEL
SEU1
>1E+12
Fails/Device-Day
FIT
(Fails/Device/1E9 Hrs)
N/cm2
Notes:
1. Measured at room temperature unless otherwise stated.
2. Device electrical characteristics are guaranteed for post-irradiation levels at 25°C.
3. 10% worst-case particle environment, geosynchronous orbit, 0.025” of aluminum shielding. Specification set using the CREME code upset
rate calculation method with a 2µ epi thickness.
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7
Pa c ka ge T he r m a l C ha r a ct e r i s t i c s
The device junction to case thermal characteristics is θjc, and
the junction to ambient air characteristics is θja. The thermal
characteristics for θja are listed with two different air flow
rates, as shown in the table below. Maximum junction
temperature is 150°C.
A sample calculation of the maximum power dissipation for
an 84-pin ceramic quad flat pack at commercial temperature
is as follows:
150°C – 70°C- = 2.0 W
Max
junction temp. ( °C ) – Max commercial temp. ( °C -) = --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------40°C/W
θja (°C/W)
Pin Count
θjc
θja
Still Air
θja
300 ft/min
Units
Ceramic Quad Flat Pack
84
7.8
40
30
°C/W
Ceramic Quad Flat Pack
172
6.8
28
20
°C/W
Package Type
Po w e r D i s s i pa t i o n
Gener al P ow er E quat i on
A ct iv e P ow er Co mp onen ts
P = [ICCstandby + ICCactive] * VCC + IOL * VOL * N + IOH *
(VCC – VOH) * M
N equals the number of outputs driving TTL loads to
VOL.
Power dissipation in CMOS devices is usually dominated by
the active (dynamic) power dissipation. This component is
frequency-dependent and a function of the logic and the
external I/O. Active power dissipation results from charging
internal chip capacitances of the interconnect,
unprogrammed antifuses, module inputs, and module
outputs, plus external capacitance due to PC board traces and
load device inputs. An additional component of the active
power dissipation is the totempole current in CMOS transistor
pairs. The net effect can be associated with an equivalent
capacitance that can be combined with frequency and voltage
to represent active power dissipation.
M equals the number of outputs driving TTL loads to
VOH.
The power dissipated by a CMOS circuit can be expressed by
Equation 1:
where:
ICCstandby is the current flowing when no inputs or
outputs are changing.
ICCactive is the current flowing due to CMOS switching.
IOL, IOH are TTL sink/source currents.
VOL, VOH are TTL level output voltages.
Power (uW) = CEQ * VCC2 * F
Accurate values for N and M are difficult to determine
because they depend on the family type, design details, and
on the system I/O. The power can be divided into two
components: static and active.
CEQ
= Equivalent capacitance in pF
S tat i c P ow er Co m ponen ts
VCC
= Power supply in volts (V)
F
= Switching frequency in MHz
Actel FPGAs have small static power components that result
in lower power dissipation than PALs or PLDs. By integrating
multiple PALs/PLDs into one FPGA, an even greater
reduction in board-level power dissipation can be achieved.
The power due to standby current is typically a small
component of the overall power. Standby power is calculated
below for military, worst case conditions.
8
ICC
VCC
Power
25 mA
5.5V
138 mW (max)
1 mA
5.5V
5.5 mW (typ)
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(1)
where:
E qui va len t Cap acit an ce
Equivalent capacitance is calculated by measuring ICC active
at a specified frequency and voltage for each circuit
component of interest. Measurements have been made over a
range of frequencies at a fixed value of VCC. Equivalent
capacitance is frequency-independent so the results may be
used over a wide range of operating conditions. Equivalent
capacitance values follow.
R a d ia t io n -H a r d e n e d F PG A s
C E Q Va lues f or Ac tel F PG A s
RH1020 RH1280
Modules (CEQM)
3.7
5.2
Input Buffers (CEQI)
22.1
11.6
Output Buffers (CEQO)
31.2
23.8
Routed Array Clock Buffer Loads (CEQCR)
4.6
3.5
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic must
be known. Equation 2 shows a piece-wise linear summation
over all components.
Power = VCC2 * [(m * CEQM* fm)modules +(n * CEQI* fn)inputs +
(p * (CEQO+ CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1
+ (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * fq2)routed_Clk2
+ (r2 * fq2)routed_Clk2]
(2)
where:
Fix ed Capa cit anc e V alu es for A ct el FP GAs
(pF)
Device Type
r1
routed_Clk1
r2
routed_Clk2
RH1020
RH1280
69
168
N/A
168
De ter m in ing Av er age S wi tc hing Fr equ ency
To determine the switching frequency for a design, you must
have a detailed understanding of the data input values to the
circuit. The following guidelines are meant to represent
worst-case scenarios, so they can be generally used to predict
the upper limits of power dissipation. These guidelines are as
follow:
Logic Modules (m)
= 80% of Modules
Inputs Switching (n)
= # Inputs/4
Outputs Switching (p)
= # Outputs/4
First Routed Array Clock Loads (q1)
= 40% of
Sequential
Modules
m
= Number of logic modules switching at fm
n
= Number of input buffers switching at fn
p
= Number of output buffers switching at fp
q1
= Number of clock loads on the first routed array
clock
Second Routed Array Clock Loads (q2) = 40% of
(RH1280 only)
Sequential
Modules
q2
= Number of clock loads on the second routed array
clock (RH1280 only)
Load Capacitance (CL)
r1
= Fixed capacitance due to first routed array clock
r2
= Fixed capacitance due to second routed array
clock (RH1280 only)
Average Logic Module Switching Rate = F/10
(fm)
CEQM = Equivalent capacitance of logic modules in pF
CEQI
= Equivalent capacitance of input buffers in pF
CEQO = Equivalent capacitance of output buffers in pF
CEQCR = Equivalent capacitance of routed array clock in
pF
CL
= Output lead capacitance in pF
fm
= Average logic module switching rate in MHz
fn
= Average input buffer switching rate in MHz
fp
= Average output buffer switching rate in MHz
fq1
= Average first routed array clock rate in MHz
fq2
= Average second routed array clock rate in MHz
(RH1280 only)
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= 35 pF
Average Input Switching Rate (fn)
= F/5
Average Output Switching Rate (fp)
= F/10
Average First Routed Array Clock Rate = F
(fq1)
Average Second Routed Array Clock = F/2
Rate (fq2) (RH1280 only)
9
R H1 0 20 Ti m i ng M od e l
Internal Delays
Input Delay
I/O Module
tINYL = 4.2 ns
Predicted
Routing
Delays
Output Delay
I/O Module
Logic Module
tIRD2 = 1.9 ns
tDLH = 9.1 ns
tIRD1 = 1.2 ns
tIRD4 = 4.2 ns
tIRD8 = 8.9 ns
ARRAY
CLOCK
tCKH = 7.6 ns
tPD = 3.9 ns
tCO = 3.9 ns
tRD1 = 1.2 ns
tRD2 = 1.9 ns
tRD4 = 4.2 ns
tRD8 = 8.9 ns
tENHZ = 13.5 ns
FO = 128
FMAX = 55 MHz
R H1 2 80 Ti m i ng M od e l
Input Delays
Internal Delays
Combinatorial
I/O Module
Logic Module
tINYL = 2.3 ns t
IRD2 = 7.5 ns†
Predicted
Routing
Delays
Output Delays
I/O Module
tDLH = 8.7 ns
D
Q
tRD1 = 2.7 ns
tRD2 = 3.4 ns
tRD4 = 4.8 ns
tRD8 = 9.0 ns
tPD = 4.7 ns
G
Sequential
Logic Module
tINH = 0.0 ns
tINSU = 0.6 ns
tINGL = 5.3 ns
Combinatorial
Logic
included
in tSUD
ARRAY
CLOCKS
tCKH = 11.2 ns
FO = 384
FMAX = 95 MHz
tSUD = 0.7 ns
tHD = 0.0 ns
D
Q
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Q
tRD1 = 2.7 ns
tENHZ = 9.7 ns
G
tCO = 4.7 ns
tLCO = 17.7 ns (64 loads, pad-pad)
† Input module predicted routing delay.
10
D
I/O Module
tDLH = 8.7 ns
tOUTH = 0.0 ns
tOUTSU = 0.6 ns
tGLH = 7.6 ns
R a d ia t io n -H a r d e n e d F PG A s
Pa r a m et er M ea su r e m en t
Out put B uffer Del ays
E
D
In
50%
PAD
VOL
50%
VOH
E
1.5V
1.5V
TRIBUFF
50%
VCC
PAD To AC Test Loads (shown below)
E
50%
1.5V
PAD
PAD
GND
10%
VOL
tDLH
tENZL
tDHL
50%
VOH
50%
tENLZ
90%
1.5V
tENHZ
tENZH
AC T es t Loa ds
Load 1
(Used to Measure Propagation Delay)
Load 2
(Used to Measure Rising/Falling Edges)
VCC
GND
To the Output Under Test
35 pF
R to VCC for tPLZ/tPZL
R to GND for tPHZ/tPZH
R = 1 kΩ
To the Output Under Test
35 pF
Inpu t Buffe r De lay s
PAD
M odul e D el ays
S
A
B
Y
INBUF
S, A or B
3V
PAD
1.5V 1.5V
VCC
Y
GND
0V
50%
tINYH
50% 50%
Y
tINYL
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50%
50%
tPLH
50%
Y
tPHL
Y
50%
tPHL
50%
tPLH
11
Se q ue nt i al M o du l e Ti m i ng C ha r a ct e r i s t i c s
Fli p- Flop s and Lat che s
D
E
CLK
Y
PRE
CLR
(Positive Edge Triggered)
tHD
1
D
tSUD
tA
tWCLKA
G, CLK
tSUENA
tWCLKI
tHENA
E
tCO
Q
tRS
PRE, CLR
tWASYN
Note:
12
D represents all data functions involving A, B, and S for multiplexed flip-flops.
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R a d ia t io n -H a r d e n e d F PG A s
Se q ue nt i al T i m i n g C h ar ac t er i st i c s (continued)
Inpu t Buffe r Lat che s
PAD
DATA
IBDL
G
PAD
CLK
CLKBUF
DATA
tINH
G
tINSU
tHEXT
CLK
tSUEXT
Out put B uffer Lat ches
D
PAD
OBDLHS
G
D
tOUTSU
G
tOUTH
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13
R H1 0 20 Ti m i ng C ha r a ct e r i s t i c s
(Worst-Case Military Conditions, V C C = 4.5V, T J = 125°C, RTD = 300Krad(Si))
Parameter
Description
Min.
Max.
Units
Logic Module Propagation Delays
tPD1
Single Module
3.9
ns
tPD2
Dual Module Macros
9.2
ns
tCO
Sequential Clk to Q
3.9
ns
tGO
Latch G to Q
3.9
ns
tRS
Flip-Flop (Latch) Reset to Q
3.9
ns
Logic Module Predicted Routing Delays
1
tRD1
FO=1 Routing Delay
1.2
ns
tRD2
FO=2 Routing Delay
1.9
ns
tRD3
FO=3 Routing Delay
2.8
ns
tRD4
FO=4 Routing Delay
4.2
ns
tRD8
FO=8 Routing Delay
8.9
ns
Logic Module Sequential Timing
2
tSUD
Flip-Flop (Latch) Data Input Set-Up
7.5
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
7.5
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse Width
9.2
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse Width
9.2
ns
tA
Flip-Flop Clock Input Period
19.2
ns
fMAX
Flip-Flop (Latch) Clock Frequency
50
MHz
4.2
ns
4.2
ns
Input Module Propagation Delays
tINYH
Pad to Y High
tINYL
Pad to Y Low
1, 3
Input Module Predicted Routing Delays
tIRD1
FO=1 Routing Delay
1.2
ns
tIRD2
FO=2 Routing Delay
1.9
ns
tIRD3
FO=3 Routing Delay
2.8
ns
tIRD4
FO=4 Routing Delay
4.2
ns
tIRD8
FO=8 Routing Delay
8.9
ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the DirectTime Analyzer utility.
3. Optimization techniques may further reduce delays by 0 to 4 ns.
4. The hold time for the DFME1A macro may be greater that 0 ns. Use the Designer Series 3.0 (or later) Timer to check the hold time for this
macro.
14
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R a d ia t io n -H a r d e n e d F PG A s
R H1 0 20 Ti m i ng C ha r a ct e r i s t i c s (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C, RT D = 300Kr ad(S i ))
Parameter
Description
Min.
Max.
Units
FO = 16
FO = 128
6.6
7.6
ns
FO = 16
FO = 128
8.7
9.5
ns
Global Clock Network
tCKH
tCKL
tPWH
tPWL
tCKSW
tP
fMAX
Input Low to High
Input High to Low
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
Minimum Period
Maximum Frequency
FO = 16
FO = 128
8.8
9.2
ns
FO = 16
FO = 128
1.6
2.4
ns
FO = 16
FO = 128
FO = 16
FO = 128
FO = 16
FO = 128
1.6
2.5
17.9
19.2
ns
ns
55
50
MHz
TTL Output Module Timing1
tDLH
Data to Pad High
9.1
ns
tDHL
Data to Pad Low
10.2
ns
tENZH
Enable Pad Z to High
8.9
ns
tENZL
Enable Pad Z to Low
10.7
ns
tENHZ
Enable Pad High to Z
13.5
ns
tENLZ
Enable Pad Low to Z
12.2
ns
dTLH
Delta Low to High
0.08
ns/pF
dTHL
Delta High to Low
0.11
ns/pF
CMOS Output Module Timing1
tDLH
Data to Pad High
10.7
ns
tDHL
Data to Pad Low
8.7
ns
tENZH
Enable Pad Z to High
8.1
ns
tENZL
Enable Pad Z to Low
11.2
ns
tENHZ
Enable Pad High to Z
13.5
ns
tENLZ
Enable Pad Low to Z
12.2
ns
dTLH
Delta Low to High
0.14
ns/pF
dTHL
Delta High to Low
0.08
ns/pF
Notes:
1. Delays based on 35 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
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15
R H1 2 80 Ti m i ng C ha r a ct e r i s t i c s
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C, RT D = 3 00Kr ad(S i ))
Parameter
Description
Min.
Max.
Units
1
Logic Module Propagation Delays
tPD1
Single Module
4.7
ns
tCO
Sequential Clk to Q
4.7
ns
tGO
Latch G to Q
4.7
ns
tRS
Flip-Flop (Latch) Reset to Q
4.7
ns
Logic Module Predicted Routing Delays
2
tRD1
FO=1 Routing Delay
2.7
ns
tRD2
FO=2 Routing Delay
3.4
ns
tRD3
FO=3 Routing Delay
4.1
ns
tRD4
FO=4 Routing Delay
4.8
ns
tRD8
FO=8 Routing Delay
9.0
ns
3, 4
Sequential Timing Characteristics
tSUD
Flip-Flop (Latch) Data Input Set-Up
0.7
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
1.4
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse Width
6.6
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse Width
6.6
ns
tA
Flip-Flop Clock Input Period
13.5
ns
tINH
Input Buffer Latch Hold
0.0
ns
tINSU
Input Buffer Latch Set-Up
0.6
ns
tOUTH
Output Buffer Latch Hold
0.0
ns
tOUTSU
Output Buffer Latch Set-Up
0.6
ns
fMAX
Flip-Flop (Latch) Clock Frequency
95
MHz
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from
the DirectTime Analyzer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal set-up (hold) time.
16
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R a d ia t io n -H a r d e n e d F PG A s
R H1 2 80 Ti m i ng C ha r a ct e r i s t i c s (continued)
(Worst-Case Military Conditions, V C C = 4.5V, T J = 125°C, RTD = 300Krad(Si))
Parameter
Description
Min.
Max.
Units
Input Module Propagation Delays
tINYH
Pad to Y High
1.9
ns
tINYL
Pad to Y Low
2.3
ns
tINGH
G to Y High
4.1
ns
tINGL
G to Y Low
5.3
ns
1
Input Module Predicted Routing Delays
tIRD1
FO=1 Routing Delay
6.8
ns
tIRD2
FO=2 Routing Delay
7.5
ns
tIRD3
FO=3 Routing Delay
8.2
ns
tIRD4
FO=4 Routing Delay
8.9
ns
tIRD8
FO=8 Routing Delay
11.7
ns
Global Clock Network
tCKH
Input Low to High
FO = 32
FO = 384
9.6
11.2
ns
tCKL
Input High to Low
FO = 32
FO = 384
9.6
11.2
ns
tPWH
Minimum Pulse Width High
FO = 32
FO = 384
5.8
6.2
ns
tPWL
Minimum Pulse Width Low
FO = 32
FO = 384
5.8
6.2
ns
tCKSW
Maximum Skew
FO = 32
FO = 384
tSUEXT
Input Latch External Set-Up
FO = 32
FO = 384
0.0
0.0
ns
tHEXT
Input Latch External Hold
FO = 32
FO = 384
4.6
5.8
ns
tP
Minimum Period
FO = 32
FO = 384
11.8
13.0
ns
fMAX
Maximum Frequency
FO = 32
FO = 384
1.1
1.1
105
95
ns
MHz
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce delays by 0
to 4 ns.
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17
R H1 2 80 Ti m i ng C ha r a ct e r i s t i c s (continued)
(Worst-Case Military Conditions, V C C = 4. 5V, T J = 125° C , R T D = 300 Kra d(S i) )
Parameter
Description
Min.
Max.
Units
TTL Output Module Timing1
tDLH
Data to Pad High
6.8
ns
tDHL
Data to Pad Low
7.6
ns
tENZH
Enable Pad Z to High
6.8
ns
tENZL
Enable Pad Z to Low
7.6
ns
tENHZ
Enable Pad High to Z
9.7
ns
tENLZ
Enable Pad Low to Z
9.7
ns
tGLH
G to Pad High
7.6
ns
tGHL
G to Pad Low
8.9
ns
tLCO
I/O Latch Clock-Out (Pad-to-Pad), 64 Clock Loading
17.7
ns
tACO
Array Clock-Out (Pad-to-Pad), 64 Clock Loading
25.0
ns
dTLH
Capacitive Loading, Low to High
0.07
ns/pF
dTHL
Capacitive Loading, High to Low
0.09
ns/pF
1
CMOS Output Module Timing
tDLH
Data to Pad High
8.7
ns
tDHL
Data to Pad Low
6.4
ns
tENZH
Enable Pad Z to High
6.8
ns
tENZL
Enable Pad Z to Low
7.6
ns
tENHZ
Enable Pad High to Z
9.7
ns
tENLZ
Enable Pad Low to Z
9.7
ns
tGLH
G to Pad High
7.6
ns
tGHL
G to Pad Low
8.9
ns
tLCO
I/O Latch Clock-Out (Pad-to-Pad), 64 Clock Loading
20.1
ns
tACO
Array Clock-Out (Pad-to-Pad), 64 Clock Loading
29.5
ns
dTLH
Capacitive Loading, Low to High
0.09
ns/pF
dTHL
Capacitive Loading, High to Low
0.08
ns/pF
Notes:
1. Delays based on 35 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
18
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R a d ia t io n -H a r d e n e d F PG A s
Pi n D es c ri pt i on
CLKA
Clock A (Input)
TTL clock input for clock distribution networks. The clock
input is buffered prior to clocking the logic modules. This pin
can also be used as an I/O.
CLKB
Clock B (Input)
Not applicable for RH1020. TTL clock input for clock
distribution networks. The clock input is buffered prior to
clocking the logic modules. This pin can also be used as an
I/O.
DCLK
Diagnostic Clock (Input)
TTL clock input for diagnostic probe and device
programming. DCLK is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
GND
Ground
LOW supply voltage.
I/O
Input/Output (Input, Output)
The I/O pin functions as an input, output, three-state, or
bi-directional buffer. Input and output levels are compatible
with standard TTL and CMOS specifications. Unused I/O pins
are automatically driven LOW by the Designer software.
MODE
Mode (Input)
The MODE pin controls the use of multi-function pins (DCLK,
PRA, PRB, SDI). When the MODE pin is HIGH, the special
functions are active. When the MODE pin is LOW, the pins
function as I/Os. To provide debugging capability, the MODE
pin should be terminated to GND through a 10 kΩ resistor so
that the MODE pin can be pulled HIGH when required.
NC
PRA, I/O
Probe A (Output)
The Probe A pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin can be used in conjunction with the Probe B pin to allow
real-time diagnostic output of any signal path within the
device. The Probe A pin can be used as a user-defined I/O
when verification has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality. PRA is accessible when
the MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
PRB, I/O
Probe B (Output)
The Probe B pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin can be used in conjunction with the Probe A pin to allow
real-time diagnostic output of any signal path within the
device. The Probe B pin can be used as a user-defined I/O
when verification has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality. PRB is accessible when
the MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
SDI
Serial Data Input (Input)
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH. This
pin functions as an I/O when the MODE pin is LOW.
V CC
5.0V Supply Voltage
HIGH supply voltage.
No Connection
This pin is not connected to circuitry within the device.
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19
Pa c ka ge P i n A s si g nm e n t s
84- Pi n CQFP (To p V iew )
Pin #1
Index
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
84-Pin
CQFP
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
20
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63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
R a d ia t io n -H a r d e n e d F PG A s
84-Pin CQFP
Pin Number
RH1020
Function
Pin Number
RH1020
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
NC
I/O
I/O
I/O
I/O
I/O
GND
GND
I/O
I/O
I/O
I/O
I/O
VCC
VCC
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
I/O
I/O
CLKA, I/O
I/O
MODE
VCC
VCC
I/O
I/O
I/O
SDI, I/O
DCLK, I/O
PRA, I/O
PRB, I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
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21
Pa c ka ge P i n A s si g nm e n t s (continued)
172- P in CQF P (T op Vie w)
172 171 170 169 168 167 166 165 164
137 136 135 134 133 132 131 130
Pin #1
Index
1
129
2
128
3
127
4
126
5
125
6
124
7
123
8
122
172-Pin
CQFP
35
95
36
94
37
93
38
92
39
91
40
90
41
89
42
88
43
87
44 45 46 47 48 49 50 51 52
22
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79 80 81 82 83 84 85 86
R a d ia t io n -H a r d e n e d F PG A s
172-Pin CQFP
Pin Number
RH1280A
Function
Pin Number
RH1280A
Function
Pin Number
RH1280A
Function
Pin Number
1
2
RH1280A
Function
MODE
44
I/O
87
I/O
130
I/O
I/O
45
I/O
88
I/O
131
SDI, I/O
3
I/O
46
I/O
89
I/O
132
I/O
4
I/O
47
I/O
90
I/O
133
I/O
5
I/O
48
I/O
91
I/O
134
I/O
6
I/O
49
I/O
92
I/O
135
I/O
7
GND
50
VCC
93
I/O
136
VCC
8
I/O
51
I/O
94
I/O
137
I/O
9
I/O
52
I/O
95
I/O
138
I/O
10
I/O
53
I/O
96
I/O
139
I/O
11
I/O
54
I/O
97
I/O
140
I/O
12
VCC
55
GND
98
GND
141
GND
13
I/O
56
I/O
99
I/O
142
I/O
14
I/O
57
I/O
100
I/O
143
I/O
15
I/O
58
I/O
101
I/O
144
I/O
16
I/O
59
I/O
102
I/O
145
I/O
17
GND
60
I/O
103
GND
146
I/O
18
I/O
61
I/O
104
I/O
147
I/O
19
I/O
62
I/O
105
I/O
148
PRA, I/O
20
I/O
63
I/O
106
GND
149
I/O
21
I/O
64
I/O
107
VCC
150
CLKA, I/O
22
GND
65
GND
108
GND
151
VCC
23
VCC
66
VCC
109
VCC
152
GND
24
VCC
67
I/O
110
VCC
153
I/O
25
I/O
68
I/O
111
I/O
154
CLKB, I/O
26
I/O
69
I/O
112
I/O
155
I/O
27
VCC
70
I/O
113
VCC
156
PRB, I/O
28
I/O
71
I/O
114
I/O
157
I/O
29
I/O
72
I/O
115
I/O
158
I/O
30
I/O
73
I/O
116
I/O
159
I/O
31
I/O
74
I/O
117
I/O
160
I/O
32
GND
75
GND
118
GND
161
GND
33
I/O
76
I/O
119
I/O
162
I/O
34
I/O
77
I/O
120
I/O
163
I/O
35
I/O
78
I/O
121
I/O
164
I/O
36
I/O
79
I/O
122
I/O
165
I/O
37
GND
80
VCC
123
GND
166
VCC
38
I/O
81
I/O
124
I/O
167
I/O
39
I/O
82
I/O
125
I/O
168
I/O
40
I/O
83
I/O
126
I/O
169
I/O
41
I/O
84
I/O
127
I/O
170
I/O
42
I/O
85
I/O
128
I/O
171
DCLK, I/O
43
I/O
86
I/O
129
I/O
172
I/O
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23
Pa c ka ge M e ch an i c al D r a w i ng s
84-Pin CQFP (Cavity Up)
Top View
D1
D2
H
E2
F
e
b
L1
Side View
A
Lid
c
A1
Notes:
1. Seal ring and lid are connected to Ground.
2. Lead material is Kovar with minimum 50 microinches gold plate over nickel.
3. Packages are shipped unformed with the ceramic tie bar in a test carrier.
24
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E1
Pa c ka ge M e ch an i c al D r a w i ng s (continued)
172-Pin CQFP (Cavity Up)
Top View
H
D1
D2
No. 1
Ceramic
Tie Bar
L1
E2
E1
K
F
e
b
Side View
Lid
A1
A
C
Lead Kovar
Notes:
1. Seal Ring and Lid are connected to Ground.
2. Lead material is Kovar with minimum 50 microinches gold plate over nickel.
3. Packages are shipped unformed with the ceramic tie bar in a test carrier.
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25
Cer am i c Qu ad Flat Pa ck
CQFP 84
CQFP 172
Symbol
Min
Nom.
Max
Min
Nom.
Max
A
0.070
0.090
0.100
0.094
0.105
0.116
A1
0.060
0.075
0.080
0.080
0.090
0.100
b
0.008
0.010
0.012
0.007
0.008
0.010
c
0.004
0.006
0.008
0.004
0.006
0.008
D1/E1
0.640
0.650
0.660
1.168
1.180
1.192
D2/E2
0.500 BSC
1.050 BSC
e
0.025 BSC
0.025 BSC
F
0.130
0.140
0.150
0.175
0.200
H
1.460 BSC
2.320 BSC
K
—
2.140 BSC
L1
1.595
1.600
1.615
2.485
2.495
0.225
2.505
Note:
1. All dimensions are in inches.
2. BSC equals Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
26
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27
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
http://www.actel.com
Actel Europe Ltd.
Daneshill House, Lutyens Close
Basingstoke, Hampshire RG24 8AG
United Kingdom
Tel: +44-(0)125-630-5600
Fax: +44-(0)125-635-5420
Actel Corporation
955 East Arques Avenue
Sunnyvale, California 94086
USA
Tel: (408) 739-1010
Fax: (408) 739-1540
Actel Asia-Pacific
EXOS Ebisu Bldg. 4F
1-24-14 Ebisu Shibuya-ku
Tokyo 150 Japan
Tel: +81-(0)3-3445-7671
Fax: +81-(0)3-3445-7668
5172123-2/1.00
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