ETC STD19NE06LT4

STD19NE06L
N-CHANNEL 60V - 0.038 Ω - 19A IPAK/DPAK
STripFET POWER MOSFET
TYPE
STD19NE06L
■
■
■
■
■
VDSS
RDS(on)
ID
60 V
<0.05 Ω
19 A
TYPICAL RDS(on) = 0.038 Ω
100% AVALANCHE TESTED
LOW GATE CHARGE
THROUGH-HOLE IPAK (TO-251) POWER
PACKAGE IN TUBE (SUFFIX “-1”)
SURFACE-MOUNTING DPAK (TO-252)
POWER PACKAGE IN TAPE & REEL
(SUFFIX “T4”)
3
3
1
2
1
IPAK
TO-251
(Suffix “-1”)
DPAK
TO-252
(Suffix “T4”)
DESCRIPTION
This Power MOSFET is the latest development of
STMicroelectronis unique ”Single Feature Size ” stripbased process. The resulting transistor shows extremely
high packing density for low on-resistance, rugged
avalanche characteristics and less critical alignment
steps
therefore
a
remarkable
manufacturing
reproducibility.
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ SOLENOID AND RALAY DRIVERS
■ MOTOR CONTROL, AUDIO AMPLIFIERS
■ DC-DC & DC-AC CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Symbol
V DS
V DGR
VGS
Parameter
Unit
Drain-source Voltage (VGS = 0)
60
V
Drain-gate Voltage (RGS = 20 kΩ)
60
V
± 20
V
Gate- source Voltage
ID
Drain Current (continuous) at TC = 25°C
19
A
ID
Drain Current (continuous) at TC = 100°C
13
A
IDM(•)
Ptot
E AS (1)
Tstg
Tj
Drain Current (pulsed)
76
A
Total Dissipation at TC = 25°C
Derating Factor
70
W
0.3
W/°C
Single Pulse Avalanche Energy
450
mJ
-55 to 175
°C
Storage Temperature
Max. Operating Junction Temperature
(•) Pulse width limit ed by safe operating area
September 2002
.
Value
(1) Starting Tj = 25 oC, ID = 9.5 A, VDD = 35 V
1/9
STD19NE06L
THERMAL DATA
Rthj-case
Rthj-amb
Rthc-sink
Tl
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Thermal Resistance Case-sink
Maximum Lead Temperature For Soldering Purpose
Max
Max
Typ
°C/W
°C/W
°C/W
°C
2.14
100
1.5
300
ELECTRICAL CHARACTERISTICS (Tcase = 25 °C unless otherwise specified)
OFF
Symbol
Parameter
Test Conditions
Drain-source
Breakdown Voltage
ID = 250 µA, VGS = 0
IDSS
Zero Gate Voltage
Drain Current (V GS = 0)
VDS = Max Rating
VDS = Max Rating TC = 125°C
IGSS
Gate-body Leakage
Current (VDS = 0)
VGS = ± 20 V
V(BR)DSS
Min.
Typ.
Max.
60
Unit
V
1
10
µA
µA
±100
nA
ON (*)
Symbol
Parameter
Test Conditions
VGS(th)
Gate Threshold Voltage
VDS = VGS
I D = 250 µA
R DS(on)
Static Drain-source On
Resistance
VGS = 5 V
VGS = 10 V
ID = 9.5 A
ID = 9.5 A
Min.
Typ.
Max.
Unit
1
1.7
2.5
V
0.048
0.038
0.06
0.05
Ω
Ω
Min.
Typ.
Max.
Unit
7
14
S
1350
195
58
pF
pF
pF
DYNAMIC
Symbol
2/9
Parameter
Test Conditions
gfs (*)
Forward Transconductance
VDS > ID(on) x RDS(on)max,
ID = 9.5 A
C iss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
VDS = 25V, f = 1 MHz, VGS = 0
STD19NE06L
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
td(on)
tr
Turn-on Delay Time
Rise Time
VDD = 30 V
I D = 15 A
VGS = 4.5 V
R G = 4.7 Ω
(Resistive Load, Figure 3)
25
105
Qg
Qgs
Q gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD = 48 V ID = 30 A VGS= 5V
20
8
10
28
nC
nC
nC
Typ.
Max.
Unit
ns
ns
SWITCHING OFF
Symbol
Parameter
Test Conditions
Min.
td(off)
tf
Turn-off Delay Time
Fall Time
VDD = 30 V
ID = 15 A
VGS = 4.5 V
RG = 4.7Ω,
(Resistive Load, Figure 3)
50
20
ns
ns
tr(Voff)
tf
tc
Off-voltage Rise Time
Fall Time
Cross-over Time
Vclamp = 48 V
ID = 12 A
VGS = 5V
RG = 4.7Ω,
(Inductive Load, Figure 5)
15
40
60
ns
ns
ns
SOURCE DRAIN DIODE
Symbol
Parameter
ISD
ISDM (•)
Source-drain Current
Source-drain Current (pulsed)
VSD (*)
Forward On Voltage
ISD = 30 A
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD = 30 A
di/dt = 100A/µs
T j = 150°C
VDD = 30 V
(see test circuit, Figure 5)
trr
Qrr
IRRM
Test Conditions
Min.
Typ.
V GS = 0
80
0.18
4.5
Max.
Unit
19
76
A
A
1.5
V
ns
µC
A
(*)Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
(•)Pulse width limited by safe operating area.
Safe Operating Area
Thermal Impedance
3/9
STD19NE06L
Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
4/9
STD19NE06L
Normalized Gate Threshold Voltage vs Temperature
Normalized on Resistance vs Temperature
Source-drain Diode Forward Characteristics
.
.
.
5/9
STD19NE06L
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive
Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
6/9
STD19NE06L
TO-251 (IPAK) MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.2
2.4
0.086
0.094
A1
0.9
1.1
0.035
0.043
A3
0.7
1.3
0.027
0.051
B
0.64
0.9
0.025
0.031
B2
5.2
5.4
0.204
0.212
B3
0.85
B5
0.033
0.3
0.012
B6
0.95
0.037
C
0.45
0.6
0.017
0.023
C2
0.48
0.6
0.019
0.023
D
6
6.2
0.236
0.244
E
6.4
6.6
0.252
0.260
G
4.4
4.6
0.173
0.181
H
15.9
16.3
0.626
0.641
L
9
9.4
0.354
0.370
L1
0.8
1.2
0.031
0.047
L2
0.8
1
0.031
0.039
A1
C2
A3
A
C
H
B
B3
=
1
=
2
G
=
=
=
E
B2
=
3
B5
L
D
B6
L2
L1
0068771-E
7/9
STD19NE06L
TO-252 (DPAK) MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.2
2.4
0.086
0.094
A1
0.9
1.1
0.035
0.043
A2
0.03
0.23
0.001
0.009
B
0.64
0.9
0.025
0.035
B2
5.2
5.4
0.204
0.212
C
0.45
0.6
0.017
0.023
C2
0.48
0.6
0.019
0.023
D
6
6.2
0.236
0.244
E
6.4
6.6
0.252
0.260
G
4.4
4.6
0.173
0.181
H
9.35
10.1
0.368
0.397
L2
0.8
L4
0.031
0.6
1
0.023
0.039
A1
C2
A
H
A2
C
DETAIL ”A”
L2
D
=
1
=
G
2
=
=
=
E
=
B2
3
B
DETAIL ”A”
L4
0068772-B
8/9
STD19NE06L
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express writt en approval of STMicroelectronics.
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