Product Brief February 2002 TSRD1003G ~1.06—3.2 Gbits/s Serializer and Deserializer (Macro) ■ 100 MHz—168 MHz reference clock frequency range. ■ 16-bit or 20-bit parallel I/O interface in full-rate mode. ■ Programmable control and configuration interface to define the various device configurations. ■ Analog modularity and digital library interface for design flexibility. ■ Automatic lock-to-reference in absence of receive data. ■ CML high-speed interface I/O for use with backplane or cable media. ■ Programmable transmit pre-emphasis optimized for backplane applications. ■ Requires one external resistor for bias current generation. ■ Requires no external components for clock recovery and frequency synthesis. ■ 105 mW per transceiver (typical). ■ Low powerdown dissipation. ■ Half amplitude mode for reduced power consumption in chip-to-chip applications. ■ 1.5 V ± 5% power supply. ■ 1.8 V ± 5% power supply option for differential high-speed I/O circuits. ■ SONET ■ Fibre Channel ■ InifiniBand ■ 10 Gbit Ethernet (XAUI) Description The TSRD1003G is a high-speed serializer/deserializer (SERDES) macrocell. This macro cell includes a current mode logic (CML) high-speed serial interface and makes use of a proprietary CDR architecture along with the sharing of a PLL across multiple RX and TX channels to reduce area and power consumption. These characteristics make it suitable for applications that require high channel counts. DIN RX D19 D0 CKOUT PLL REFCLK DIGITAL LIBRARY INTERFACE PARALLEL LOOPBACK Selectable data rate (1.06 Gbits/s—3.2 Gbits/s). ■ DEMUX ■ Drives chip-to-chip and across backplanes. D19 MUX Designed to operate in Ethernet, fibre channel, InfiniBand ™, and SONET/SDH (synchronous digital hierarchy) applications. CDR ■ Potential Applications SERIAL LOOPBACK Features DOUT DO 0 °C—125 °C junction temperature. DIV TX SERIAL INTERFACE Figure 1. TSRD1003G for COM2/2H TSRD1003G ~1.06—3.2 Gbits/s Serializer and Deserializer (Macro) Channels Product Brief February 2002 Reset ■ 10 TxRx pairs maximum per macro. ■ ■ User-selectable from 6—10 channels by eliminating or selectively powering-off unnecessary blocks. Resets any macro or any RX/TX block within the device. ■ Includes a power-on reset circuit within the macros. This circuit is used solely to reset the SERDES blocks within a macro after a powerup event. (No external access to the output of this circuit is provided.) Modular Macrocell ■ ■ The macrocell consists of three smaller blocks as follows: — PLL. — Transmit channel block (TX). — Receiver channel block (RX). Four different configurations as follows: — Ten RX blocks and one PLL. — Ten TX blocks and one PLL. — Ten RX/TX block pairs and one PLL. — One TX block and one PLL. Interfaces ■ High speed: current mode logic (CML). LVDS and LVPECL compatibility is available with off-chip components. ■ Parallel data: CMOS selectable between a 16-bit or 20-bit parallel I/O. ■ Registers and control logic: a four-line serial interface, allowing each channel to be addressed individually with minimal routing. Power Consumption ■ 105 mW per channel (typical, including common circuitry) consumed when all 10 channels are operating. ■ If less than 10 channels are operating, the power consumption per channel increases to include more of the common circuitry. PLL (Phase-Locked Loop) ■ The PLL is based on a differential ring oscillator at half of the intended data rate. ■ The synthesized frequency can be programmed to either 8X or 10X the reference frequency. ■ PLL relock without reset: the PLL can relock without requiring a reset (for example, after switching reference clocks). ■ A PLL lock indicator is provided. Transmitter ■ Each transmit (TX) block serializes a parallel data word with a width of 16 bits or 20 bits depending on the control register setting. ■ The TX block transforms the parallel input word into a serial data stream by using a high-speed clock that is synthesized from the reference clock by the PLL. Transmit Pre-Emphasis ■ The transmit block output buffer can be programmed through the serial register interface to select between no pre-emphasis, a 12.5% level, or a 25% level. ■ Pre-emphasis boosts the high frequencies in the transmitted data to compensate for losses present in backplanes, thus extending the useful range of transmission. Independent Powerdown ■ 2 Independent user-selectable powerdown of the following: — CML buffers. — Individual transmit blocks. — Individual receive blocks. — Transmit low-speed clock generation. — PLL. Agere Systems Inc. Product Brief February 2002 TSRD1003G ~1.06—3.2 Gbits/s Serializer and Deserializer (Macro) Half Amplitude Output ■ The TX block output buffer can be programmed through the serial interface to provide either of two different levels of output amplitude, full or half. ■ The half amplitude mode allows chip-to-chip applications and other less stringent applications to reduce the power consumption. Loss of Reference Clock ■ If the reference clock (REFCLK) bit is lost, the VCO in the PLL is forced to its lowest frequency. ■ An alarm bit in the PLL status register indicates this condition. This condition is also indicated by the core output signals of the PLL. High-Speed Clock Output Skew Between Blocks ■ ■ The skew will be less than 1.25 UI between transmit blocks if the blocks are within a macro or within an adjacent macro and use the same reference clock with a maximum skew of 100 ps (±50 ps) between macros. Receiver ■ ■ ■ The receive (RX) block transforms a high-speed serial bit stream into a stream of parallel words and recovers a high-speed clock from the serial data. The receive (RX) block further divides this clock down to provide a clock that has a frequency equal to the parallel word rate and that is phase-aligned to the word boundary. The CDR block that forms the core of the receiver is a proprietary design which results in significant power and area savings. Loss of Signal and Signal Level Detector ■ Simple analog loss-of-signal detector with a fixed threshold between a 100 mVp-p differential and 175 mVp-p differential. A clock at a 1/8 or 1/10 data rate from both the transmitter and the receiver blocks is provided to circuitry outside the macrocell. Testability Features ■ Allows testability within the ASIC. ■ Test modes are not encoded, allowing mixing and matching of test modes. ■ Self-synchronizing PRBS compatible with Agilent ® and Anritsu ® bit error rate test systems. ■ Internal loopback for parallel and serial data for TxRx macro option. ■ Independent transmit and receive built-in self-test. Digital Library Interface ■ Standard digital library interface allowing digital blocks from the Agere library or custom blocks to be integrated into the device. ■ Examples include PRBS, link state machine, SONET framer, 8B/10B encoder, 64/66 encoder, byte aligner, custom blocks. Automatic Lock-To Reference ■ The receive CDR automatically locks to reference in the absence of receive data. When a loss-of-signal is indicated, the reference clock bit is automatically switched to the RX serial inputs (this can also be disabled by setting a bit in the serial control I/F). ■ The receiver can also be forced to lock-to reference by setting a bit in the serial control I/F. Agere Systems Inc. 3 TSRD1003G ~1.06—3.2 Gbits/s Serializer and Deserializer (Macro) Product Brief February 2002 InfiniBand is a trademark of InfiniBand Trade Association. Agilent is a registered trademark of Agilent Technologies, Inc. Anritsu is a registered trademark of Anritsu Corporation. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: [email protected] N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TIAWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Copyright © 2002 Agere Systems Inc. All Rights Reserved February 2002 PB02-064HSPL (Replaces PB01-156HSPL)