áç PRELIMINARY XRT73L06 SIX-CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT APRIL 2002 GENERAL DESCRIPTION The XRT73L06 is a Six-Channel fully integrated Line Interface Unit (LIU) for E3/DS3/STS-1 applications. It incorporates six independent Receivers and Transmitters in a single 208-pin QFP package. Each channel of the XRT73L06 can be configured to operate in E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 (51.84 MHz) rates that are independent of each other. Each transmitter can be turned off and tristated for redundancy support and power conservation. The XRT73L06’s differential receivers provide high noise interference margin and are able to receive the data over 1000 feet of cable, or with up to 12 dB of cable attenuation. The XRT73L06 provides a Parallel Microprocessor Interface for programming and control. The XRT73L06 supports local, remote and digital loop-backs. The XRT73L06 also contains an onboard Pseudo Random Binary Sequence (PRBS) generator and detector with the ability to insert and detect single bit error. REV. P1.0.0 • Provides low jitter clock outputs for either E3, DS3 or STS-1 rates • Meets Jitter Tolerance Requirements, as specified in ITU-T G.823_1993 for E3 Applications • Meets Jitter Tolerance Requirements, as specified in Bellcore GR-499-CORE for DS3 Applications Transmitter: • Compliant with Bellcore GR-499, GR-253 and ANSI T1.102 Specification for transmit pulse • Tri-state Transmit output capability for Redundancy applications • Transmitters can be turned on or off Control and Diagnostics: • Parallel Microprocessor Interface for control and configuration • Supports optional internal Transmit Driver Monitoring • PRBS Error Counter Register to accumulate errors • Supports Local, Remote and Digital Loop-backs • Single 3.3 V ± 5% power supply FEATURES Receiver: • 5 V Tolerant I/O • On chip Clock and Data Recovery circuit for high input jitter tolerance • Available in 208 pin QFP package • Detects and Clears LOS as per G.775 APPLICATIONS • Receiver Monitor mode handles up to 20 dB flat loss with 6 dB cable attenuation • E3/DS3 Access Equipment • On chip B3ZS/HDB3 encoder and decoder that can be either enabled or disabled • DSLAMs • On-chip Clock Synthesizer generates the appropriate rate clock from a single frequency Crystal • CSU/DSU Equipment • Maximum Power Dissipation 2.5W. • -40°C to 85°C Industrial Temperature Range • STS1-SPE to DS3 Mapper • Digital Cross Connect Systems • Routers • Fiber Optic Terminals Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com áç XRT73L06 SIX-CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.0.0 FIGURE 1. BLOCK DIAGRAM OF THE XRT73L06 INT PCLK RESET ADDR [7:0] CS RD WR PMODE D [7:0] RDY XRT73L06 CLKOUT_(n) E3CLK,DS3CLK, STS-1CLK Microprocessor Interface RLOL_(n) Clock Synthesizer Peak Detector RTIP_(n) RRING_(n) Clock & Data Recovery Slicer AGC/ Equalizer MUX LOS Detector Local LoopBack Invert RxCLK_(n) HDB3/ B3ZS Decoder RPOS_(n) RNEG_(n)/ LCV_(n) Remote LoopBack RLOS_(n) TTIP_(n) TRING_(n) MTIP_(n) MRING_(n) Line Driver Device Monitor Tx Pulse Shaping Timing Control MUX TPOS_(n) HDB3/ B3ZS Encoder TNEG_(n) TxCLK_(n) Tx Control TxON_n Channel 0 DMO_(n) Channels 1 to 4 Channel 5 Note: (n) = 0, 1... 5 for respective Channels • Transmitters can be turned off in order to support redundancy designs Transmit Interface Characteristics • Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal to the line Receive Interface Characteristics • Integrated Pulse Shaping Circuit • Integrated Adaptive Receive Equalization for optimal Clock and Data Recovery • Built-in B3ZS/HDB3 Encoder (which can be disabled) • Declares and Clears the LOS defect per ITU-T G.775 requirements for E3 and DS3 applications • Accepts Transmit Clock with duty cycle of 30%-70% • Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms • Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications • Built-in B3ZS/HDB3 Decoder (which can be disabled) • Generates pulses that comply with the DSX-3 pulse template, as specified in Bellcore GR-499-CORE and ANSI T1.102_1993 • Recovered Data can be muted while the LOS Condition is declared • Outputs either Single-Rail or Dual-Rail data to the Terminal Equipment • Generates pulses that comply with the STSX-1 pulse template, as specified in Bellcore GR-253CORE ORDERING INFORMATION PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE XRT73L06IQ 208 LEAD PLASTIC QUAD FLAT PACK (28 mm x 28 mm) -40°C to +85°C 2